ATE541312T1 - Chip mit zwei gruppen von chipkontakten - Google Patents

Chip mit zwei gruppen von chipkontakten

Info

Publication number
ATE541312T1
ATE541312T1 AT05747294T AT05747294T ATE541312T1 AT E541312 T1 ATE541312 T1 AT E541312T1 AT 05747294 T AT05747294 T AT 05747294T AT 05747294 T AT05747294 T AT 05747294T AT E541312 T1 ATE541312 T1 AT E541312T1
Authority
AT
Austria
Prior art keywords
chip
contacts
groups
passivating layer
conductor
Prior art date
Application number
AT05747294T
Other languages
English (en)
Inventor
Heimo Scheucher
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE541312T1 publication Critical patent/ATE541312T1/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
AT05747294T 2004-05-28 2005-05-18 Chip mit zwei gruppen von chipkontakten ATE541312T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04102408 2004-05-28
PCT/IB2005/051613 WO2005117109A1 (en) 2004-05-28 2005-05-18 Chip having two groups of chip contacts

Publications (1)

Publication Number Publication Date
ATE541312T1 true ATE541312T1 (de) 2012-01-15

Family

ID=34970726

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05747294T ATE541312T1 (de) 2004-05-28 2005-05-18 Chip mit zwei gruppen von chipkontakten

Country Status (7)

Country Link
US (1) US9318428B2 (de)
EP (1) EP1754256B1 (de)
JP (1) JP2008501231A (de)
KR (1) KR20070034530A (de)
CN (1) CN1961424B (de)
AT (1) ATE541312T1 (de)
WO (1) WO2005117109A1 (de)

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ATE485597T1 (de) 2007-07-12 2010-11-15 Nxp Bv Integrierte schaltungen auf einem wafer und verfahren zur herstellung integrierter schaltungen
US20150129665A1 (en) * 2013-11-13 2015-05-14 David Finn Connection bridges for dual interface transponder chip modules
US11068770B2 (en) 2014-03-08 2021-07-20 Féinics AmaTech Teoranta Lower Churchfield Connection bridges for dual interface transponder chip modules
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof
US9842831B2 (en) 2015-05-14 2017-12-12 Mediatek Inc. Semiconductor package and fabrication method thereof
AU2017226865B2 (en) * 2016-03-01 2022-08-25 Cardlab Aps A circuit layer for an integrated circuit card
JP6867400B2 (ja) 2016-03-02 2021-04-28 ピーエー コット ファミリー ホールディング ゲーエムベーハーＰＡ．ＣＯＴＴＥ Ｆａｍｉｌｙ Ｈｏｌｄｉｎｇ ＧｍｂＨ 表示装置の製造方法および表示装置

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EP1754256B1 (de) 2012-01-11
EP1754256A1 (de) 2007-02-21
CN1961424B (zh) 2010-08-11
WO2005117109A1 (en) 2005-12-08
US9318428B2 (en) 2016-04-19
CN1961424A (zh) 2007-05-09
JP2008501231A (ja) 2008-01-17
US20080017980A1 (en) 2008-01-24
KR20070034530A (ko) 2007-03-28

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