ATE535911T1 - Hochgeschwindigkeits-dram-architektur mit einheitlicher zugriffslatenz - Google Patents

Hochgeschwindigkeits-dram-architektur mit einheitlicher zugriffslatenz

Info

Publication number
ATE535911T1
ATE535911T1 AT09151003T AT09151003T ATE535911T1 AT E535911 T1 ATE535911 T1 AT E535911T1 AT 09151003 T AT09151003 T AT 09151003T AT 09151003 T AT09151003 T AT 09151003T AT E535911 T1 ATE535911 T1 AT E535911T1
Authority
AT
Austria
Prior art keywords
word line
write
read
dram
access latency
Prior art date
Application number
AT09151003T
Other languages
English (en)
Inventor
Paul Demone
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Application granted granted Critical
Publication of ATE535911T1 publication Critical patent/ATE535911T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/2281Timing of a read operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/229Timing of a write operation
AT09151003T 2000-07-07 2001-06-29 Hochgeschwindigkeits-dram-architektur mit einheitlicher zugriffslatenz ATE535911T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US21667900P 2000-07-07 2000-07-07
CA002313954A CA2313954A1 (en) 2000-07-07 2000-07-07 High speed dram architecture with uniform latency

Publications (1)

Publication Number Publication Date
ATE535911T1 true ATE535911T1 (de) 2011-12-15

Family

ID=4166723

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09151003T ATE535911T1 (de) 2000-07-07 2001-06-29 Hochgeschwindigkeits-dram-architektur mit einheitlicher zugriffslatenz

Country Status (5)

Country Link
EP (1) EP2276033B1 (de)
CN (1) CN100568383C (de)
AT (1) ATE535911T1 (de)
CA (3) CA2313954A1 (de)
ES (1) ES2516791T3 (de)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324398B2 (en) 2013-02-04 2016-04-26 Micron Technology, Inc. Apparatuses and methods for targeted refreshing of memory
US9047978B2 (en) 2013-08-26 2015-06-02 Micron Technology, Inc. Apparatuses and methods for selective row refreshes
JP2015219938A (ja) 2014-05-21 2015-12-07 マイクロン テクノロジー, インク. 半導体装置
KR102389232B1 (ko) * 2015-10-16 2022-04-22 에스케이하이닉스 주식회사 메모리 장치 및 이를 포함하는 시스템
JP2017182854A (ja) 2016-03-31 2017-10-05 マイクロン テクノロジー, インク. 半導体装置
KR102533236B1 (ko) * 2016-06-20 2023-05-17 삼성전자주식회사 개선된 레이턴시를 갖는 메모리 장치 및 그것의 동작 방법
US9805786B1 (en) * 2017-01-06 2017-10-31 Micron Technology, Inc. Apparatuses and methods for a memory device with dual common data I/O lines
US10490251B2 (en) 2017-01-30 2019-11-26 Micron Technology, Inc. Apparatuses and methods for distributing row hammer refresh events across a memory device
US10127971B1 (en) * 2017-05-01 2018-11-13 Micron Technology, Inc. Systems and methods for memory cell array initialization
US10665295B2 (en) * 2017-11-15 2020-05-26 Samsung Electronics Co., Ltd. Static random-access memory with virtual banking architecture, and system and method including the same
KR20190070158A (ko) * 2017-12-12 2019-06-20 에스케이하이닉스 주식회사 어드레스 디코더 및 이를 포함하는 반도체 메모리 장치
US10580475B2 (en) 2018-01-22 2020-03-03 Micron Technology, Inc. Apparatuses and methods for calculating row hammer refresh addresses in a semiconductor device
KR102476789B1 (ko) * 2018-03-16 2022-12-13 에스케이하이닉스 주식회사 센스 앰프 및 이를 이용한 반도체 메모리 장치
CN112106138B (zh) 2018-05-24 2024-02-27 美光科技公司 用于行锤击刷新采样的纯时间自适应采样的设备和方法
US11152050B2 (en) 2018-06-19 2021-10-19 Micron Technology, Inc. Apparatuses and methods for multiple row hammer refresh address sequences
US10685696B2 (en) 2018-10-31 2020-06-16 Micron Technology, Inc. Apparatuses and methods for access based refresh timing
WO2020117686A1 (en) 2018-12-03 2020-06-11 Micron Technology, Inc. Semiconductor device performing row hammer refresh operation
CN111354393B (zh) 2018-12-21 2023-10-20 美光科技公司 用于目标刷新操作的时序交错的设备和方法
US10770127B2 (en) 2019-02-06 2020-09-08 Micron Technology, Inc. Apparatuses and methods for managing row access counts
US11043254B2 (en) 2019-03-19 2021-06-22 Micron Technology, Inc. Semiconductor device having cam that stores address signals
US11227649B2 (en) 2019-04-04 2022-01-18 Micron Technology, Inc. Apparatuses and methods for staggered timing of targeted refresh operations
CN111833940B (zh) * 2019-04-15 2022-06-24 华邦电子股份有限公司 一种存储芯片及其控制方法
US11264096B2 (en) 2019-05-14 2022-03-01 Micron Technology, Inc. Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits
US11158364B2 (en) 2019-05-31 2021-10-26 Micron Technology, Inc. Apparatuses and methods for tracking victim rows
US11069393B2 (en) 2019-06-04 2021-07-20 Micron Technology, Inc. Apparatuses and methods for controlling steal rates
US11158373B2 (en) 2019-06-11 2021-10-26 Micron Technology, Inc. Apparatuses, systems, and methods for determining extremum numerical values
US10832792B1 (en) 2019-07-01 2020-11-10 Micron Technology, Inc. Apparatuses and methods for adjusting victim data
US11139015B2 (en) 2019-07-01 2021-10-05 Micron Technology, Inc. Apparatuses and methods for monitoring word line accesses
US11386946B2 (en) 2019-07-16 2022-07-12 Micron Technology, Inc. Apparatuses and methods for tracking row accesses
US10943636B1 (en) 2019-08-20 2021-03-09 Micron Technology, Inc. Apparatuses and methods for analog row access tracking
US10964378B2 (en) 2019-08-22 2021-03-30 Micron Technology, Inc. Apparatus and method including analog accumulator for determining row access rate and target row address used for refresh operation
US11200942B2 (en) 2019-08-23 2021-12-14 Micron Technology, Inc. Apparatuses and methods for lossy row access counting
US11302374B2 (en) 2019-08-23 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic refresh allocation
US11302377B2 (en) 2019-10-16 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic targeted refresh steals
US11100966B2 (en) * 2020-01-09 2021-08-24 Winbond Electronics Corp. Array edge repeater in memory device
US11309010B2 (en) 2020-08-14 2022-04-19 Micron Technology, Inc. Apparatuses, systems, and methods for memory directed access pause
US11380382B2 (en) 2020-08-19 2022-07-05 Micron Technology, Inc. Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit
US11348631B2 (en) 2020-08-19 2022-05-31 Micron Technology, Inc. Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed
US11222682B1 (en) 2020-08-31 2022-01-11 Micron Technology, Inc. Apparatuses and methods for providing refresh addresses
US11557331B2 (en) 2020-09-23 2023-01-17 Micron Technology, Inc. Apparatuses and methods for controlling refresh operations
US11222686B1 (en) 2020-11-12 2022-01-11 Micron Technology, Inc. Apparatuses and methods for controlling refresh timing
US11462291B2 (en) 2020-11-23 2022-10-04 Micron Technology, Inc. Apparatuses and methods for tracking word line accesses
US11264079B1 (en) 2020-12-18 2022-03-01 Micron Technology, Inc. Apparatuses and methods for row hammer based cache lockdown
US11482275B2 (en) 2021-01-20 2022-10-25 Micron Technology, Inc. Apparatuses and methods for dynamically allocated aggressor detection
US11600314B2 (en) 2021-03-15 2023-03-07 Micron Technology, Inc. Apparatuses and methods for sketch circuits for refresh binning
US11664063B2 (en) 2021-08-12 2023-05-30 Micron Technology, Inc. Apparatuses and methods for countering memory attacks
US11688451B2 (en) 2021-11-29 2023-06-27 Micron Technology, Inc. Apparatuses, systems, and methods for main sketch and slim sketch circuit for row address tracking
CN116741223A (zh) * 2022-03-03 2023-09-12 长鑫存储技术有限公司 数据读出电路、数据读出方法和存储器

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5808959A (en) * 1996-08-07 1998-09-15 Alliance Semiconductor Corporation Staggered pipeline access scheme for synchronous random access memory
US6072743A (en) * 1998-01-13 2000-06-06 Mitsubishi Denki Kabushiki Kaisha High speed operable semiconductor memory device with memory blocks arranged about the center

Also Published As

Publication number Publication date
EP2276033B1 (de) 2014-07-16
CA2313954A1 (en) 2002-01-07
CA2805048A1 (en) 2002-01-17
CA2805048C (en) 2015-02-10
CA2414920C (en) 2013-04-23
ES2516791T3 (es) 2014-10-31
CN101038785A (zh) 2007-09-19
EP2276033A1 (de) 2011-01-19
CA2414920A1 (en) 2002-01-17
CN100568383C (zh) 2009-12-09

Similar Documents

Publication Publication Date Title
ATE535911T1 (de) Hochgeschwindigkeits-dram-architektur mit einheitlicher zugriffslatenz
WO2002005281A3 (en) A high speed dram architecture with uniform access latency
US7551502B2 (en) Semiconductor device
JP3490887B2 (ja) 同期型半導体記憶装置
US7333363B2 (en) Semiconductor storage apparatus
KR950006608A (ko) 고속순차 액세스용 행어드레스 버퍼 유니트에 독자적인 캐쉬 메모리로서 역할하는 감지 증폭기를 가진 동적 랜덤 액세스 메모리 장치
JP2001222885A5 (de)
JPH05159567A (ja) デュアルポートメモリ
IL185249A0 (en) Register read for volatile memory
US6181620B1 (en) Semiconductor storage device
KR20030014629A (ko) 반도체기억장치
JPS6378396A (ja) 半導体メモリ
JP3103575B2 (ja) 半導体記憶装置
JPH06124587A (ja) ダイナミックランダムアクセスメモリ装置
US6456563B1 (en) Semiconductor memory device that operates in sychronization with a clock signal
FR2864321B1 (fr) Memoire dynamique a acces aleatoire ou dram comportant au moins deux registres tampons et procede de commande d'une telle memoire
KR920020720A (ko) 소비 전류를 증가시키지 않고 검사용이성을 개량한 동적 랜덤 억세스 메모리 디바이스
EP0488593B1 (de) Dynamische Direktzugriffspeicheranordnung mit verbesserter Auffrischungsschaltung
KR100614640B1 (ko) 워드라인 부분활성화 커맨드를 갖는 반도체메모리장치
US7088637B2 (en) Semiconductor memory device for high speed data access
JP3708801B2 (ja) 半導体記憶装置
MY103962A (en) Multiport memory
KR970023401A (ko) 디램(dram) 어레이
KR20010102846A (ko) 동기형 반도체 기억 장치
KR20030067462A (ko) 반도체 기억 장치 및 프리차지 방법