ATE527686T1 - Prozess für soi-einrichtungen mit ultradünnem körper, die epi-siliziumspitzen enthalten, und dadurch hergestellte artikel - Google Patents

Prozess für soi-einrichtungen mit ultradünnem körper, die epi-siliziumspitzen enthalten, und dadurch hergestellte artikel

Info

Publication number
ATE527686T1
ATE527686T1 AT03764362T AT03764362T ATE527686T1 AT E527686 T1 ATE527686 T1 AT E527686T1 AT 03764362 T AT03764362 T AT 03764362T AT 03764362 T AT03764362 T AT 03764362T AT E527686 T1 ATE527686 T1 AT E527686T1
Authority
AT
Austria
Prior art keywords
ultra
thin body
made therefrom
articles made
devices containing
Prior art date
Application number
AT03764362T
Other languages
English (en)
Inventor
Anand Murthy
Brian Doyle
Jack Kavalieros
Robert Chau
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE527686T1 publication Critical patent/ATE527686T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
AT03764362T 2002-07-12 2003-07-03 Prozess für soi-einrichtungen mit ultradünnem körper, die epi-siliziumspitzen enthalten, und dadurch hergestellte artikel ATE527686T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/194,506 US7473947B2 (en) 2002-07-12 2002-07-12 Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
PCT/US2003/021131 WO2004008489A2 (en) 2002-07-12 2003-07-03 Process for ultra-thin body soi devices that incorporate epi silicon tips and article made thereby

Publications (1)

Publication Number Publication Date
ATE527686T1 true ATE527686T1 (de) 2011-10-15

Family

ID=30114761

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03764362T ATE527686T1 (de) 2002-07-12 2003-07-03 Prozess für soi-einrichtungen mit ultradünnem körper, die epi-siliziumspitzen enthalten, und dadurch hergestellte artikel

Country Status (7)

Country Link
US (2) US7473947B2 (de)
EP (1) EP1428263B1 (de)
CN (1) CN100353564C (de)
AT (1) ATE527686T1 (de)
AU (1) AU2003249726A1 (de)
TW (1) TWI236699B (de)
WO (1) WO2004008489A2 (de)

Families Citing this family (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227176B2 (en) * 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
EP1309989B1 (de) * 2000-08-16 2007-01-10 Massachusetts Institute Of Technology Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
WO2002082514A1 (en) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
US7301180B2 (en) * 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
WO2003015142A2 (en) * 2001-08-06 2003-02-20 Massachusetts Institute Of Technology Formation of planar strained layers
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US7138649B2 (en) * 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
AU2002331077A1 (en) * 2001-08-13 2003-03-03 Amberwave Systems Corporation Dram trench capacitor and method of making the same
US6831292B2 (en) * 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
AU2002341803A1 (en) 2001-09-24 2003-04-07 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
US7060632B2 (en) * 2002-03-14 2006-06-13 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
AU2003238963A1 (en) * 2002-06-07 2003-12-22 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7615829B2 (en) * 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
AU2003247513A1 (en) * 2002-06-10 2003-12-22 Amberwave Systems Corporation Growing source and drain elements by selecive epitaxy
US6982474B2 (en) * 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US7473947B2 (en) * 2002-07-12 2009-01-06 Intel Corporation Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
JP2004079790A (ja) * 2002-08-19 2004-03-11 Oki Electric Ind Co Ltd 完全空乏型ｓｏｉ−ｍｏｓトランジスタおよびその製造方法
US20040154083A1 (en) * 2002-12-23 2004-08-12 Mcvicker Henry J. Sports pad closure system with integrally molded hooks
CN100437970C (zh) * 2003-03-07 2008-11-26 琥珀波系统公司 一种结构及用于形成半导体结构的方法
US9673280B2 (en) 2003-06-12 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Cobalt silicidation process for substrates comprised with a silicon-germanium layer
TW594872B (en) * 2003-06-12 2004-06-21 Taiwan Semiconductor Mfg Self-aligned silicided process and structure
US6924517B2 (en) * 2003-08-26 2005-08-02 International Business Machines Corporation Thin channel FET with recessed source/drains and extensions
JP2005158786A (ja) * 2003-11-20 2005-06-16 Seiko Epson Corp 半導体装置及びその製造方法
US6989322B2 (en) * 2003-11-25 2006-01-24 International Business Machines Corporation Method of forming ultra-thin silicidation-stop extensions in mosfet devices
JP4610205B2 (ja) * 2004-02-18 2011-01-12 株式会社リコー 半導体装置
KR100577020B1 (ko) * 2004-04-09 2006-05-10 매그나칩 반도체 유한회사 반도체 소자의 레지듀 및 열 특성 개선 방법
US7247535B2 (en) * 2004-09-30 2007-07-24 Texas Instruments Incorporated Source/drain extensions having highly activated and extremely abrupt junctions
KR100612420B1 (ko) * 2004-10-20 2006-08-16 삼성전자주식회사 반도체 소자 및 그 제조 방법
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
KR100602122B1 (ko) * 2004-12-03 2006-07-19 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
US7195985B2 (en) * 2005-01-04 2007-03-27 Intel Corporation CMOS transistor junction regions formed by a CVD etching and deposition sequence
US7335959B2 (en) * 2005-01-06 2008-02-26 Intel Corporation Device with stepped source/drain region profile
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7501336B2 (en) * 2005-06-21 2009-03-10 Intel Corporation Metal gate device with reduced oxidation of a high-k gate dielectric
US7439576B2 (en) * 2005-08-29 2008-10-21 Micron Technology, Inc. Ultra-thin body vertical tunneling transistor
US8003470B2 (en) 2005-09-13 2011-08-23 Infineon Technologies Ag Strained semiconductor device and method of making the same
US7572705B1 (en) * 2005-09-21 2009-08-11 Advanced Micro Devices, Inc. Semiconductor device and method of manufacturing a semiconductor device
JP2007103456A (ja) * 2005-09-30 2007-04-19 Toshiba Corp 半導体装置及びその製造方法
JP5567247B2 (ja) * 2006-02-07 2014-08-06 セイコーインスツル株式会社 半導体装置およびその製造方法
JP2007317796A (ja) * 2006-05-24 2007-12-06 Toshiba Corp 半導体装置および半導体装置の製造方法
US7541239B2 (en) * 2006-06-30 2009-06-02 Intel Corporation Selective spacer formation on transistors of different classes on the same device
US7897493B2 (en) * 2006-12-08 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Inducement of strain in a semiconductor layer
DE102007010563A1 (de) * 2007-02-22 2008-08-28 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Selektives Wachstum von polykristallinem siliziumhaltigen Halbleitermaterial auf siliziumhaltiger Halbleiteroberfläche
US7825003B2 (en) * 2007-06-26 2010-11-02 International Business Machines Corporation Method of doping field-effect-transistors (FETs) with reduced stress/strain relaxation and resulting FET devices
US20090001430A1 (en) * 2007-06-29 2009-01-01 International Business Machines Corporation Eliminate notching in si post si-recess rie to improve embedded doped and instrinsic si epitazial process
US7795605B2 (en) * 2007-06-29 2010-09-14 International Business Machines Corporation Phase change material based temperature sensor
US7692213B2 (en) * 2007-08-07 2010-04-06 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing a condensation process
US7947545B2 (en) * 2007-10-31 2011-05-24 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Method for producing a transistor gate with sub-photolithographic dimensions
US8030163B2 (en) * 2007-12-26 2011-10-04 Intel Corporation Reducing external resistance of a multi-gate device using spacer processing techniques
US7763943B2 (en) * 2007-12-26 2010-07-27 Intel Corporation Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin
US20090206404A1 (en) * 2008-02-15 2009-08-20 Ravi Pillarisetty Reducing external resistance of a multi-gate device by silicidation
US8264048B2 (en) * 2008-02-15 2012-09-11 Intel Corporation Multi-gate device having a T-shaped gate structure
US8022487B2 (en) * 2008-04-29 2011-09-20 Intel Corporation Increasing body dopant uniformity in multi-gate transistor devices
US7776624B2 (en) * 2008-07-08 2010-08-17 International Business Machines Corporation Method for improving semiconductor surfaces
US7951657B2 (en) * 2009-05-21 2011-05-31 International Business Machines Corporation Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor
US9305779B2 (en) * 2009-08-11 2016-04-05 Bae Systems Information And Electronic Systems Integration Inc. Method for growing germanium epitaxial films
US8598003B2 (en) 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication
US8299546B2 (en) * 2010-03-25 2012-10-30 International Business Machines Corporation Semiconductor devices with vertical extensions for lateral scaling
CN102376769B (zh) * 2010-08-18 2013-06-26 中国科学院微电子研究所 超薄体晶体管及其制作方法
KR101776926B1 (ko) * 2010-09-07 2017-09-08 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8288758B2 (en) 2010-12-02 2012-10-16 International Business Machines Corporation SOI SiGe-base lateral bipolar junction transistor
US8455930B2 (en) 2011-01-05 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Strained semiconductor device with facets
CN102891178A (zh) * 2011-07-19 2013-01-23 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
CN102891177B (zh) * 2011-07-19 2016-03-02 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
CN103137480B (zh) * 2011-11-25 2015-07-08 中芯国际集成电路制造(上海)有限公司 Mos器件的形成方法及其形成的mos器件
KR101427726B1 (ko) * 2011-12-27 2014-08-07 가부시키가이샤 히다치 고쿠사이 덴키 기판 처리 장치 및 반도체 장치의 제조 방법
US8698230B2 (en) * 2012-02-22 2014-04-15 Eastman Kodak Company Circuit including vertical transistors with a conductive stack having reentrant profile
CN102832238A (zh) * 2012-09-17 2012-12-19 东莞市天域半导体科技有限公司 一种具有欧姆接触保护层的碳化硅器件及其制作方法
JP6094159B2 (ja) * 2012-11-13 2017-03-15 三菱電機株式会社 半導体装置の製造方法
CN103400858B (zh) * 2013-08-02 2016-01-20 清华大学 绝缘体上三维半导体器件及其形成方法
CN104733309A (zh) * 2013-12-18 2015-06-24 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US9343589B2 (en) 2014-01-22 2016-05-17 Globalfoundries Inc. Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures
US9716160B2 (en) * 2014-08-01 2017-07-25 International Business Machines Corporation Extended contact area using undercut silicide extensions
US9240454B1 (en) 2014-10-22 2016-01-19 Stmicroelectronics, Inc. Integrated circuit including a liner silicide with low contact resistance
US9768254B2 (en) * 2015-07-30 2017-09-19 International Business Machines Corporation Leakage-free implantation-free ETSOI transistors
FR3046876B1 (fr) * 2016-01-19 2018-12-14 Commissariat A L'energie Atomique Et Aux Energies Alternatives Consommation du canal d'un transistor par oxydation sacrificielle
US10141426B2 (en) * 2016-02-08 2018-11-27 International Business Macahines Corporation Vertical transistor device
US9935186B1 (en) 2016-09-21 2018-04-03 International Business Machines Corporation Method of manufacturing SOI lateral Si-emitter SiGe base HBT
US11887988B2 (en) 2019-08-01 2024-01-30 Intel Corporation Thin film transistor structures with regrown source and drain
US11164785B2 (en) * 2019-12-27 2021-11-02 Intel Corporation Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material
US11244943B2 (en) 2019-12-27 2022-02-08 Intel Corporation Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material
US11328988B2 (en) 2019-12-27 2022-05-10 Intel Corporation Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication
CN113629144B (zh) * 2020-05-08 2023-07-07 长鑫存储技术有限公司 半导体器件及其制备方法
FR3116380B1 (fr) * 2020-11-18 2022-12-16 Commissariat Energie Atomique Procédé de fabrication d’une zone dopée d’un dispositif microélectronique

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4052251A (en) 1976-03-02 1977-10-04 Rca Corporation Method of etching sapphire utilizing sulfur hexafluoride
US5043778A (en) * 1986-08-11 1991-08-27 Texas Instruments Incorporated Oxide-isolated source/drain transistor
US4963502A (en) * 1988-08-25 1990-10-16 Texas Instruments, Incorporated Method of making oxide-isolated source/drain transistor
US4876213A (en) 1988-10-31 1989-10-24 Motorola, Inc. Salicided source/drain structure
US5310626A (en) * 1993-03-01 1994-05-10 Motorola, Inc. Method for forming a patterned layer using dielectric materials as a light-sensitive material
JP3761918B2 (ja) * 1994-09-13 2006-03-29 株式会社東芝 半導体装置の製造方法
US5915164A (en) 1995-12-28 1999-06-22 U.S. Philips Corporation Methods of making high voltage GaN-A1N based semiconductor devices
US6037627A (en) * 1996-08-02 2000-03-14 Seiko Instruments Inc. MOS semiconductor device
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US5824587A (en) * 1997-07-09 1998-10-20 Advanced Micro Devices, Inc. Method for making convex device with elevated gate structure
US5869359A (en) * 1997-08-20 1999-02-09 Prabhakar; Venkatraman Process for forming silicon on insulator devices having elevated source and drain regions
US6060403A (en) * 1997-09-17 2000-05-09 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US6140230A (en) 1998-02-19 2000-10-31 Micron Technology, Inc. Methods of forming metal nitride and silicide structures
US6071783A (en) * 1998-08-13 2000-06-06 Taiwan Semiconductor Manufacturing Company Pseudo silicon on insulator MOSFET device
KR100347544B1 (ko) * 1999-02-13 2002-08-07 주식회사 하이닉스반도체 반도체 소자의 접합 제조 방법
KR100332106B1 (ko) * 1999-06-29 2002-04-10 박종섭 반도체 소자의 트랜지스터 제조 방법
US6403433B1 (en) 1999-09-16 2002-06-11 Advanced Micro Devices, Inc. Source/drain doping technique for ultra-thin-body SOI MOS transistors
US6559011B1 (en) * 2000-10-19 2003-05-06 Muhammed Ayman Shibib Dual level gate process for hot carrier control in double diffused MOS transistors
JP2002186080A (ja) * 2000-12-19 2002-06-28 Citizen Electronics Co Ltd 多機能型音響装置
US6406951B1 (en) 2001-02-12 2002-06-18 Advanced Micro Devices, Inc. Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology
US6548364B2 (en) * 2001-03-29 2003-04-15 Sharp Laboratories Of America, Inc. Self-aligned SiGe HBT BiCMOS on SOI substrate and method of fabricating the same
US6521949B2 (en) * 2001-05-03 2003-02-18 International Business Machines Corporation SOI transistor with polysilicon seed
EP1278234B1 (de) * 2001-07-19 2012-01-11 STMicroelectronics Srl MOS Transistor und Verfahren zu dessen Herstellung
US6642133B2 (en) * 2001-12-20 2003-11-04 Intel Corporation Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
US6696345B2 (en) * 2002-01-07 2004-02-24 Intel Corporation Metal-gate electrode for CMOS transistor applications
US6784076B2 (en) * 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source
US7473947B2 (en) * 2002-07-12 2009-01-06 Intel Corporation Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
US6909145B2 (en) * 2002-09-23 2005-06-21 International Business Machines Corporation Metal spacer gate for CMOS FET
US6774000B2 (en) * 2002-11-20 2004-08-10 International Business Machines Corporation Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6933577B2 (en) 2003-10-24 2005-08-23 International Business Machines Corporation High performance FET with laterally thin extension
US6949482B2 (en) 2003-12-08 2005-09-27 Intel Corporation Method for improving transistor performance through reducing the salicide interface resistance
US7045407B2 (en) * 2003-12-30 2006-05-16 Intel Corporation Amorphous etch stop for the anisotropic etching of substrates
US7402872B2 (en) 2004-11-18 2008-07-22 Intel Corporation Method for forming an integrated circuit
US7518196B2 (en) * 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060252191A1 (en) 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions
US7858481B2 (en) * 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel

Also Published As

Publication number Publication date
AU2003249726A1 (en) 2004-02-02
US20050272187A1 (en) 2005-12-08
EP1428263B1 (de) 2011-10-05
TWI236699B (en) 2005-07-21
US20040007724A1 (en) 2004-01-15
US7422971B2 (en) 2008-09-09
EP1428263A2 (de) 2004-06-16
CN100353564C (zh) 2007-12-05
TW200409174A (en) 2004-06-01
AU2003249726A8 (en) 2004-02-02
US7473947B2 (en) 2009-01-06
CN1543679A (zh) 2004-11-03
WO2004008489A3 (en) 2004-03-18
WO2004008489A2 (en) 2004-01-22

Similar Documents

Publication Publication Date Title
ATE527686T1 (de) Prozess für soi-einrichtungen mit ultradünnem körper, die epi-siliziumspitzen enthalten, und dadurch hergestellte artikel
WO2005101515A3 (en) Process to improve transistor drive current through the use of strain
TWI264048B (en) Method for selectively forming strained etch stop layers to improve FET charge carrier mobility
WO2005043591A8 (en) HIGH PERFORMANCE STRESS-ENHANCED MOSFETs USING Si:C AND SiGe EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE
SG143174A1 (en) Method to form selective strained si using lateral epitaxy
TW200605322A (en) Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility
TW200511575A (en) Method of fabricating a double gate field effect transistor device, and such a double gate field effect transistor device
EP1521298A3 (de) Verfahren zur Herstellung eines Hochspannungsfeldeffekttransistors
GB2491778A (en) A P-Fet with a strained nanowire channel and embedded sige source and drain stressors
WO2006039038A3 (en) Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
TW200739819A (en) Semiconductor device, and method for manufacturing the same
WO2008005916A3 (en) Method for making planar nanowire surround gate mosfet
WO2003026019A1 (fr) Dispositif a semi-conducteurs et procede de production correspondant
GB2442689A (en) Methods for fabricating a stressed MOS device
TW200711148A (en) Stressed field effect transistors on hybrid orientation substrate
TW200729465A (en) An embedded strain layer in thin SOI transistors and a method of forming the same
WO2002078091A3 (en) Field effect transistor structure and method of manufacture
CN101295647A (zh) 增强mos器件沟道区应变的方法
TW200504359A (en) Single-electron transistor, field-effect transistor, sensor, method for producing sensor, and sensing method
WO2005053032A3 (en) Trench insulated gate field effect transistor
TWI256129B (en) Integrated circuit with strained and non-strained transistors, and method of forming thereof
ATE524831T1 (de) Nanoskaliger inp fet
TW201712758A (en) Carbon-based interface for epitaxially grown source/drain transistor regions
WO2008117431A1 (ja) 半導体装置および半導体装置の製造方法
TW200618042A (en) Field effect transistor having a carrier exclusion layer

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties