ATE526634T1 - Skalierbare busstruktur - Google Patents

Skalierbare busstruktur

Info

Publication number
ATE526634T1
ATE526634T1 AT09177248T AT09177248T ATE526634T1 AT E526634 T1 ATE526634 T1 AT E526634T1 AT 09177248 T AT09177248 T AT 09177248T AT 09177248 T AT09177248 T AT 09177248T AT E526634 T1 ATE526634 T1 AT E526634T1
Authority
AT
Austria
Prior art keywords
read
write
control signals
address information
channel
Prior art date
Application number
AT09177248T
Other languages
English (en)
Inventor
Richard Gerard Hofmann
Mark Michael Schaffer
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE526634T1 publication Critical patent/ATE526634T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Small-Scale Networks (AREA)
AT09177248T 2004-02-04 2005-02-03 Skalierbare busstruktur ATE526634T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54211404P 2004-02-04 2004-02-04
US10/921,053 US7209998B2 (en) 2004-02-04 2004-08-17 Scalable bus structure

Publications (1)

Publication Number Publication Date
ATE526634T1 true ATE526634T1 (de) 2011-10-15

Family

ID=34811473

Family Applications (2)

Application Number Title Priority Date Filing Date
AT09177248T ATE526634T1 (de) 2004-02-04 2005-02-03 Skalierbare busstruktur
AT05722790T ATE477542T1 (de) 2004-02-04 2005-02-03 Skalierbare busstruktur

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT05722790T ATE477542T1 (de) 2004-02-04 2005-02-03 Skalierbare busstruktur

Country Status (12)

Country Link
US (3) US7209998B2 (de)
EP (2) EP1714218B9 (de)
JP (2) JP4685800B2 (de)
KR (1) KR100876575B1 (de)
CN (2) CN100481053C (de)
AT (2) ATE526634T1 (de)
DE (1) DE602005022829D1 (de)
ES (1) ES2348582T3 (de)
HK (1) HK1099823A1 (de)
IL (3) IL177240A (de)
PL (1) PL1714218T3 (de)
WO (1) WO2005078594A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7209998B2 (en) * 2004-02-04 2007-04-24 Qualcomm Incorporated Scalable bus structure
US7617343B2 (en) * 2005-03-02 2009-11-10 Qualcomm Incorporated Scalable bus structure
US8108563B2 (en) 2006-02-24 2012-01-31 Qualcomm Incorporated Auxiliary writes over address channel
US7822903B2 (en) * 2006-02-24 2010-10-26 Qualcomm Incorporated Single bus command having transfer information for transferring data in a processing system
US8107492B2 (en) * 2006-02-24 2012-01-31 Qualcomm Incorporated Cooperative writes over the address channel of a bus
BRPI0709486A2 (pt) 2006-04-10 2011-07-19 Elta Systems Ltd sistema de transmissor eletrÈnico de interferência distribuìdo
JP5166922B2 (ja) * 2008-03-10 2013-03-21 キヤノン株式会社 共有バス制御装置及びその制御方法
KR20100063219A (ko) * 2008-12-03 2010-06-11 삼성전자주식회사 시스템 온 칩에서 비트 단위의 데이터 쓰기 방법 및 장치
US9768945B2 (en) 2012-04-23 2017-09-19 Analog Devices, Inc. Isolated system data communication
US9972196B2 (en) * 2012-04-23 2018-05-15 Analog Devices, Inc. Isolator system with status data integrated with measurement data
US9280503B2 (en) * 2013-04-12 2016-03-08 Apple Inc. Round robin arbiter handling slow transaction sources and preventing block
KR101925694B1 (ko) * 2013-12-26 2018-12-05 인텔 코포레이션 멀티칩 패키지 링크
US11086803B2 (en) * 2018-10-05 2021-08-10 Micron Technology, Inc. Dynamically configuring transmission lines of a bus
WO2020252791A1 (zh) * 2019-06-21 2020-12-24 华为技术有限公司 一种集成芯片及数据处理方法

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63146148A (ja) * 1986-12-09 1988-06-18 Nec Corp バス方式
US5065396A (en) * 1990-01-02 1991-11-12 At&T Bell Laboratories Inverse multiplexer and demultiplexer techniques
US5161162A (en) * 1990-04-12 1992-11-03 Sun Microsystems, Inc. Method and apparatus for system bus testability through loopback
US5418785A (en) * 1992-06-04 1995-05-23 Gte Laboratories Incorporated Multiple-channel token ring network with single optical fiber utilizing subcarrier multiplexing with a dedicated control channel
US5303227A (en) * 1992-08-03 1994-04-12 Motorola, Inc. Method and apparatus for enhanced modes in SPI communication
US5450547A (en) 1992-10-01 1995-09-12 Xerox Corporation Bus interface using pending channel information stored in single circular queue for controlling channels of data transfer within multiple FIFO devices
US5699540A (en) * 1992-11-16 1997-12-16 Intel Corporation Pseudo-concurrent access to a cached shared resource
JPH06259343A (ja) * 1993-03-10 1994-09-16 Hitachi Ltd 多重バス制御方式及びそれを用いたシステム
US5752076A (en) * 1995-08-31 1998-05-12 Intel Corporation Dynamic programming of bus master channels by intelligent peripheral devices using communication packets
US6209071B1 (en) * 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US5812878A (en) * 1996-05-10 1998-09-22 Apple Computer, Inc. System for DMA transfer wherein controller waits before execution of next instruction until a counter counts down from a value loaded by said controller
US5896513A (en) * 1996-07-03 1999-04-20 Intel Corporation Computer system providing a universal architecture adaptive to a variety of processor types and bus protocols
US5925118A (en) * 1996-10-11 1999-07-20 International Business Machines Corporation Methods and architectures for overlapped read and write operations
US5926831A (en) * 1996-10-11 1999-07-20 International Business Machines Corporation Methods and apparatus for control of speculative memory accesses
US5870406A (en) * 1997-02-19 1999-02-09 Ericsson Inc. Automatic repeat request(ARQ) data communications method and apparatus
JPH10289202A (ja) * 1997-04-16 1998-10-27 Seiko Epson Corp マイコン回路
US5944805A (en) * 1997-08-21 1999-08-31 Advanced Micro Devices, Inc. System and method for transmitting data upon an address portion of a computer system bus during periods of maximum utilization of a data portion of the bus
US5991841A (en) * 1997-09-24 1999-11-23 Intel Corporation Memory transactions on a low pin count bus
US6081860A (en) * 1997-11-20 2000-06-27 International Business Machines Corporation Address pipelining for data transfers
US6292705B1 (en) * 1998-09-29 2001-09-18 Conexant Systems, Inc. Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system
US6167475A (en) * 1998-07-06 2000-12-26 International Business Machines Corporation Data transfer method/engine for pipelining shared memory bus accesses
US6430641B1 (en) * 1999-05-04 2002-08-06 International Business Machines Corporation Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system
US6427193B1 (en) * 1999-05-18 2002-07-30 Advanced Micro Devices, Inc. Deadlock avoidance using exponential backoff
JP3853114B2 (ja) * 1999-07-30 2006-12-06 松下電器産業株式会社 インターフェースの設計方法
JP2001092662A (ja) * 1999-09-22 2001-04-06 Toshiba Corp プロセッサコア及びこれを用いたプロセッサ
CN1129071C (zh) 1999-10-27 2003-11-26 盖内蒂克瓦尔有限公司 元件之间的通道传输结构及其传输方法
JP2001154981A (ja) * 1999-11-12 2001-06-08 Geneticware Corp Ltd エレメント間のチャンネル通信方法およびそのチャンネル通信装置
US6628166B2 (en) * 2000-03-03 2003-09-30 Tripath Technology, Inc. RF communication system using an RF digital amplifier
JP2001265711A (ja) * 2000-03-17 2001-09-28 Casio Comput Co Ltd データ転送装置およびバスシステム
JP3714104B2 (ja) * 2000-03-31 2005-11-09 セイコーエプソン株式会社 電子印刷装置用の画像処理コントローラ及びそれを有する電子印刷装置。
US6654836B1 (en) * 2000-06-20 2003-11-25 International Business Machines Corporation Dual master device for improved utilization of a processor local bus
US6772254B2 (en) * 2000-06-21 2004-08-03 International Business Machines Corporation Multi-master computer system with overlapped read and write operations and scalable address pipelining
US6629166B1 (en) 2000-06-29 2003-09-30 Intel Corporation Methods and systems for efficient connection of I/O devices to a channel-based switched fabric
US6594712B1 (en) 2000-10-20 2003-07-15 Banderacom, Inc. Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link
US7076595B1 (en) * 2001-05-18 2006-07-11 Xilinx, Inc. Programmable logic device including programmable interface core and central processing unit
US6842816B1 (en) * 2001-07-31 2005-01-11 Network Elements, Inc. Configurable glueless microprocessor interface
US7191271B2 (en) * 2001-09-20 2007-03-13 Lockheed Martin Corporation Two level multi-tier system bus
US20030112805A1 (en) 2001-12-19 2003-06-19 Stanton Kevin B. Method and apparatus for providing device-to-device connectivity using shared infiniband NIC device
US7035958B2 (en) * 2002-10-03 2006-04-25 International Business Machines Corporation Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target
JP4314460B2 (ja) * 2003-02-20 2009-08-19 ソニー株式会社 データ転送方法、データ転送装置およびデータ転送システム
US7136953B1 (en) * 2003-05-07 2006-11-14 Nvidia Corporation Apparatus, system, and method for bus link width optimization
US7782325B2 (en) * 2003-10-22 2010-08-24 Alienware Labs Corporation Motherboard for supporting multiple graphics cards
US20050182884A1 (en) * 2004-01-22 2005-08-18 Hofmann Richard G. Multiple address two channel bus structure
WO2005071556A1 (en) * 2004-01-22 2005-08-04 Qualcomm Incorporated A two channel bus structure to support address information, data, and transfer qualifiers
US7209998B2 (en) * 2004-02-04 2007-04-24 Qualcomm Incorporated Scalable bus structure
US8028143B2 (en) * 2004-08-27 2011-09-27 Qualcomm Incorporated Method and apparatus for transmitting memory pre-fetch commands on a bus
US7185123B2 (en) * 2004-09-15 2007-02-27 Qualcomm Incorporated Method and apparatus for allocating bandwidth on a transmit channel of a bus

Also Published As

Publication number Publication date
EP1714218B9 (de) 2012-03-14
US7913021B2 (en) 2011-03-22
JP2011044154A (ja) 2011-03-03
JP5180268B2 (ja) 2013-04-10
CN101493805A (zh) 2009-07-29
CN1934557A (zh) 2007-03-21
KR100876575B1 (ko) 2008-12-31
US20090327548A1 (en) 2009-12-31
US20070088894A1 (en) 2007-04-19
KR20060120272A (ko) 2006-11-24
HK1099823A1 (en) 2007-08-24
ES2348582T3 (es) 2010-12-09
JP4685800B2 (ja) 2011-05-18
IL177240A0 (en) 2006-12-10
US7209998B2 (en) 2007-04-24
DE602005022829D1 (de) 2010-09-23
EP2163993B1 (de) 2011-09-28
JP2007520832A (ja) 2007-07-26
EP1714218A1 (de) 2006-10-25
IL209278A0 (en) 2011-01-31
CN100481053C (zh) 2009-04-22
WO2005078594A1 (en) 2005-08-25
IL177240A (en) 2011-01-31
ATE477542T1 (de) 2010-08-15
EP2163993A1 (de) 2010-03-17
PL1714218T3 (pl) 2011-02-28
CN101493805B (zh) 2015-07-15
IL209279A0 (en) 2011-01-31
EP1714218B1 (de) 2010-08-11
US20050172063A1 (en) 2005-08-04

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