ATE521033T1 - Dynamisch umkonfigurierbarer datenraum - Google Patents

Dynamisch umkonfigurierbarer datenraum

Info

Publication number
ATE521033T1
ATE521033T1 AT02752011T AT02752011T ATE521033T1 AT E521033 T1 ATE521033 T1 AT E521033T1 AT 02752011 T AT02752011 T AT 02752011T AT 02752011 T AT02752011 T AT 02752011T AT E521033 T1 ATE521033 T1 AT E521033T1
Authority
AT
Austria
Prior art keywords
memory
data space
dynamic reconfigurable
reconfigurable data
space
Prior art date
Application number
AT02752011T
Other languages
English (en)
Inventor
Michael Catherwood
Joseph Triece
Michael Pyska
Joshua Conner
Original Assignee
Microchip Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Tech Inc filed Critical Microchip Tech Inc
Application granted granted Critical
Publication of ATE521033T1 publication Critical patent/ATE521033T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
AT02752011T 2001-06-01 2002-05-30 Dynamisch umkonfigurierbarer datenraum ATE521033T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/870,448 US6601160B2 (en) 2001-06-01 2001-06-01 Dynamically reconfigurable data space
PCT/US2002/016970 WO2002099634A1 (en) 2001-06-01 2002-05-30 Dynamically reconfigurable data space

Publications (1)

Publication Number Publication Date
ATE521033T1 true ATE521033T1 (de) 2011-09-15

Family

ID=25355395

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02752011T ATE521033T1 (de) 2001-06-01 2002-05-30 Dynamisch umkonfigurierbarer datenraum

Country Status (5)

Country Link
US (1) US6601160B2 (de)
EP (1) EP1393166B1 (de)
AT (1) ATE521033T1 (de)
TW (1) TWI223147B (de)
WO (1) WO2002099634A1 (de)

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US6820189B1 (en) * 1999-05-12 2004-11-16 Analog Devices, Inc. Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation
US7107302B1 (en) 1999-05-12 2006-09-12 Analog Devices, Inc. Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units
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US20050036357A1 (en) * 2003-08-15 2005-02-17 Broadcom Corporation Digital signal processor having a programmable address generator, and applications thereof
US7581074B2 (en) * 2006-05-19 2009-08-25 International Business Machines Corporation Facilitating use of storage access keys to access storage
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WO2008010146A2 (en) * 2006-07-14 2008-01-24 Nxp B.V. Dual interface memory arrangement and method

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Also Published As

Publication number Publication date
WO2002099634A1 (en) 2002-12-12
US6601160B2 (en) 2003-07-29
EP1393166B1 (de) 2011-08-17
TWI223147B (en) 2004-11-01
EP1393166A1 (de) 2004-03-03
US20030028743A1 (en) 2003-02-06

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