ATE5115T1 - Gold-metallisierung in halbleiteranordnungen. - Google Patents

Gold-metallisierung in halbleiteranordnungen.

Info

Publication number
ATE5115T1
ATE5115T1 AT81301648T AT81301648T ATE5115T1 AT E5115 T1 ATE5115 T1 AT E5115T1 AT 81301648 T AT81301648 T AT 81301648T AT 81301648 T AT81301648 T AT 81301648T AT E5115 T1 ATE5115 T1 AT E5115T1
Authority
AT
Austria
Prior art keywords
gold
titanium
layer
semiconductor
substrate
Prior art date
Application number
AT81301648T
Other languages
English (en)
Inventor
Christopher John Heslop
Original Assignee
The Post Office
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Post Office filed Critical The Post Office
Application granted granted Critical
Publication of ATE5115T1 publication Critical patent/ATE5115T1/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53247Noble-metal alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Catalysts (AREA)
  • Weting (AREA)
  • Physical Vapour Deposition (AREA)
AT81301648T 1980-04-17 1981-04-14 Gold-metallisierung in halbleiteranordnungen. ATE5115T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8012688 1980-04-17
EP81301648A EP0039174B1 (de) 1980-04-17 1981-04-14 Gold-Metallisierung in Halbleiteranordnungen

Publications (1)

Publication Number Publication Date
ATE5115T1 true ATE5115T1 (de) 1983-11-15

Family

ID=10512847

Family Applications (1)

Application Number Title Priority Date Filing Date
AT81301648T ATE5115T1 (de) 1980-04-17 1981-04-14 Gold-metallisierung in halbleiteranordnungen.

Country Status (5)

Country Link
US (1) US4417387A (de)
EP (1) EP0039174B1 (de)
JP (1) JPS56164573A (de)
AT (1) ATE5115T1 (de)
DE (1) DE3161228D1 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL186354C (nl) * 1981-01-13 1990-11-01 Sharp Kk Halfgeleiderinrichting die uit iii-v verbindingen bestaat, met een samengestelde elektrode.
JPS59167096A (ja) * 1983-03-11 1984-09-20 日本電気株式会社 回路基板
JPS60253958A (ja) * 1984-05-31 1985-12-14 Sharp Corp センサ
US4772935A (en) * 1984-12-19 1988-09-20 Fairchild Semiconductor Corporation Die bonding process
USH434H (en) 1985-02-15 1988-02-02 American Telephone And Telegraph Company, At&T Bell Laboratories Contacts to III-V semiconductors
US4843453A (en) * 1985-05-10 1989-06-27 Texas Instruments Incorporated Metal contacts and interconnections for VLSI devices
US4716071A (en) * 1985-08-22 1987-12-29 Harris Corporation Method of ensuring adhesion of chemically vapor deposited oxide to gold integrated circuit interconnect lines
US4866505A (en) * 1986-03-19 1989-09-12 Analog Devices, Inc. Aluminum-backed wafer and chip
US4740485A (en) * 1986-07-22 1988-04-26 Monolithic Memories, Inc. Method for forming a fuse
US5055908A (en) * 1987-07-27 1991-10-08 Texas Instruments Incorporated Semiconductor circuit having metallization with TiW
US4990995A (en) * 1987-09-08 1991-02-05 General Electric Company Low reflectance conductor in an integrated circuit
JPH01199310A (ja) * 1987-10-27 1989-08-10 Fuji Photo Film Co Ltd 薄膜磁気ヘッド
JPH01302842A (ja) * 1988-05-31 1989-12-06 Nec Corp 多層配線構造の半導体装置
US5118584A (en) * 1990-06-01 1992-06-02 Eastman Kodak Company Method of producing microbump circuits for flip chip mounting
US5406122A (en) * 1993-10-27 1995-04-11 Hughes Aircraft Company Microelectronic circuit structure including conductor bridges encapsulated in inorganic dielectric passivation layer
US5807453A (en) * 1995-05-04 1998-09-15 Tessera, Inc. Fabrication of leads on semiconductor connection components
US5783487A (en) * 1996-02-20 1998-07-21 Motorola, Inc. Method of coupling titanium to a semiconductor substrate and semiconductor device thereof
JP3378505B2 (ja) * 1998-06-23 2003-02-17 株式会社東芝 半導体装置およびその製造方法
US6306312B1 (en) * 1999-06-30 2001-10-23 Lam Research Corporation Method for etching a gold metal layer using a titanium hardmask
ITMI20022482A1 (it) * 2002-11-22 2004-05-23 Silverstar S R L Materiale metallico dotato di strato protettivo realizzato mediante
US20070297081A1 (en) * 2006-06-27 2007-12-27 Seagate Technology Llc Magnetic device for current assisted magnetic recording
US20080259493A1 (en) * 2007-02-05 2008-10-23 Seagate Technology Llc Wire-assisted write device with high thermal reliability
US7855853B2 (en) * 2007-06-20 2010-12-21 Seagate Technology Llc Magnetic write device with a cladded write assist element
US8339736B2 (en) * 2007-06-20 2012-12-25 Seagate Technology Llc Wire-assisted magnetic write device with low power consumption
US7983002B2 (en) * 2007-06-26 2011-07-19 Seagate Technology Llc Wire-assisted magnetic write device with a gapped trailing shield
US8098455B2 (en) * 2007-06-27 2012-01-17 Seagate Technology Llc Wire-assisted magnetic write device with phase shifted current
US20120175755A1 (en) * 2011-01-12 2012-07-12 Infineon Technologies Ag Semiconductor device including a heat spreader
US9956396B2 (en) * 2012-02-08 2018-05-01 Medtronic Bakken Research Center B.V. Thin film for a lead for brain applications
WO2016039073A1 (ja) 2014-09-08 2016-03-17 富士電機株式会社 半導体装置および半導体装置の製造方法
US10507321B2 (en) 2014-11-25 2019-12-17 Medtronic Bakken Research Center B.V. Multilayer structure and method of manufacturing a multilayer structure

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USB392136I5 (de) * 1964-08-26
US3647585A (en) * 1969-05-23 1972-03-07 Bell Telephone Labor Inc Method of eliminating pinhole shorts in an air-isolated crossover
US3601666A (en) * 1969-08-21 1971-08-24 Texas Instruments Inc Titanium tungsten-gold contacts for semiconductor devices
US3686080A (en) * 1971-07-21 1972-08-22 Rca Corp Method of fabrication of semiconductor devices
US3900944A (en) * 1973-12-19 1975-08-26 Texas Instruments Inc Method of contacting and connecting semiconductor devices in integrated circuits
US4005455A (en) * 1974-08-21 1977-01-25 Intel Corporation Corrosive resistant semiconductor interconnect pad

Also Published As

Publication number Publication date
JPS56164573A (en) 1981-12-17
EP0039174A1 (de) 1981-11-04
DE3161228D1 (en) 1983-11-24
EP0039174B1 (de) 1983-10-19
US4417387A (en) 1983-11-29

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee