ATE493759T1 - Verfahren zur herstellung einer in harz eingebetteten elektronischen vorrichtung - Google Patents
Verfahren zur herstellung einer in harz eingebetteten elektronischen vorrichtungInfo
- Publication number
- ATE493759T1 ATE493759T1 AT04104575T AT04104575T ATE493759T1 AT E493759 T1 ATE493759 T1 AT E493759T1 AT 04104575 T AT04104575 T AT 04104575T AT 04104575 T AT04104575 T AT 04104575T AT E493759 T1 ATE493759 T1 AT E493759T1
- Authority
- AT
- Austria
- Prior art keywords
- resin
- producing
- electronic device
- dam frame
- embedded electronic
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Casting Or Compression Moulding Of Plastics Or The Like (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003342932A JP4152855B2 (ja) | 2003-10-01 | 2003-10-01 | 樹脂封止型の電子デバイスの製造方法。 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE493759T1 true ATE493759T1 (de) | 2011-01-15 |
Family
ID=34309103
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT04104575T ATE493759T1 (de) | 2003-10-01 | 2004-09-21 | Verfahren zur herstellung einer in harz eingebetteten elektronischen vorrichtung |
Country Status (6)
Country | Link |
---|---|
US (1) | US7135358B2 (de) |
EP (1) | EP1521304B1 (de) |
JP (1) | JP4152855B2 (de) |
AT (1) | ATE493759T1 (de) |
DE (1) | DE602004030752D1 (de) |
SG (1) | SG110183A1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6947748B2 (en) | 2000-12-15 | 2005-09-20 | Adaptix, Inc. | OFDMA with adaptive subcarrier-cluster configuration and selective loading |
JP2006100489A (ja) * | 2004-09-29 | 2006-04-13 | Ricoh Co Ltd | プリント基板及びそのプリント基板を用いた電子ユニット並びに樹脂流出防止用ダムの形成方法 |
US7573851B2 (en) | 2004-12-07 | 2009-08-11 | Adaptix, Inc. | Method and system for switching antenna and channel assignments in broadband wireless networks |
DE102005005750B4 (de) * | 2005-02-07 | 2009-06-04 | Infineon Technologies Ag | Verfahren zum Verbinden eines thermoplastischen Materials mit einem duroplastischen Material und Thermoplast-Duroplast-Verbund |
CN104392968B (zh) * | 2008-11-21 | 2018-05-18 | 先进封装技术私人有限公司 | 半导体基板 |
JP5263009B2 (ja) * | 2009-06-02 | 2013-08-14 | 株式会社村田製作所 | 基板の製造方法 |
CN102097340A (zh) * | 2010-12-14 | 2011-06-15 | 沈阳中光电子有限公司 | 用cob灌胶封装制作smd的方法 |
JP2013058330A (ja) * | 2011-09-07 | 2013-03-28 | Sumitomo Wiring Syst Ltd | シールド線のコネクタ接続端末処理構造部及びシールド線のコネクタ接続端末処理構造部の製造方法 |
JP2014533258A (ja) | 2011-11-15 | 2014-12-11 | ゼンション・リミテッドXention Limited | カリウムチャネル阻害剤としてのチエノ[2,3−c]ピラゾールの使用 |
JP2016162964A (ja) * | 2015-03-04 | 2016-09-05 | ローム株式会社 | 半導体装置の製造方法および半導体装置 |
CN106876342A (zh) * | 2016-12-19 | 2017-06-20 | 杰群电子科技(东莞)有限公司 | 一种双面散热半导体元件的制造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5612513A (en) * | 1995-09-19 | 1997-03-18 | Micron Communications, Inc. | Article and method of manufacturing an enclosed electrical circuit using an encapsulant |
JPH09301480A (ja) * | 1996-05-13 | 1997-11-25 | Hitachi Ltd | 搬送用トレイ |
US5776798A (en) * | 1996-09-04 | 1998-07-07 | Motorola, Inc. | Semiconductor package and method thereof |
JP3819574B2 (ja) * | 1997-12-25 | 2006-09-13 | 三洋電機株式会社 | 半導体装置の製造方法 |
US6130473A (en) * | 1998-04-02 | 2000-10-10 | National Semiconductor Corporation | Lead frame chip scale package |
US6580159B1 (en) * | 1999-11-05 | 2003-06-17 | Amkor Technology, Inc. | Integrated circuit device packages and substrates for making the packages |
US6444499B1 (en) * | 2000-03-30 | 2002-09-03 | Amkor Technology, Inc. | Method for fabricating a snapable multi-package array substrate, snapable multi-package array and snapable packaged electronic components |
DE10024336A1 (de) * | 2000-05-17 | 2001-11-22 | Heidenhain Gmbh Dr Johannes | Bauelementanordnung und Verfahren zur Herstellung einer Bauelementanordnung |
JP2003142634A (ja) * | 2001-08-20 | 2003-05-16 | Sony Corp | 半導体装置、その製造方法及び電子機器 |
JP2003218251A (ja) * | 2002-01-28 | 2003-07-31 | Murata Mfg Co Ltd | 電子デバイスおよびその製造方法 |
-
2003
- 2003-10-01 JP JP2003342932A patent/JP4152855B2/ja not_active Expired - Lifetime
-
2004
- 2004-09-21 EP EP04104575A patent/EP1521304B1/de not_active Expired - Fee Related
- 2004-09-21 AT AT04104575T patent/ATE493759T1/de not_active IP Right Cessation
- 2004-09-21 DE DE602004030752T patent/DE602004030752D1/de active Active
- 2004-09-24 US US10/948,164 patent/US7135358B2/en active Active
- 2004-10-01 SG SG200405591A patent/SG110183A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
DE602004030752D1 (de) | 2011-02-10 |
SG110183A1 (en) | 2005-04-28 |
EP1521304B1 (de) | 2010-12-29 |
EP1521304A2 (de) | 2005-04-06 |
US20050074922A1 (en) | 2005-04-07 |
JP2005109300A (ja) | 2005-04-21 |
JP4152855B2 (ja) | 2008-09-17 |
US7135358B2 (en) | 2006-11-14 |
EP1521304A3 (de) | 2006-10-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |