ATE486409T1 - Ereignisgesteuerte dynamische logik für verringerte stromaufnahme - Google Patents

Ereignisgesteuerte dynamische logik für verringerte stromaufnahme

Info

Publication number
ATE486409T1
ATE486409T1 AT03749010T AT03749010T ATE486409T1 AT E486409 T1 ATE486409 T1 AT E486409T1 AT 03749010 T AT03749010 T AT 03749010T AT 03749010 T AT03749010 T AT 03749010T AT E486409 T1 ATE486409 T1 AT E486409T1
Authority
AT
Austria
Prior art keywords
clock
state
power consumption
logic
clock signal
Prior art date
Application number
AT03749010T
Other languages
English (en)
Inventor
Sung-Mo Kang
Seung-Moon Yoo
Original Assignee
Univ California
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ California filed Critical Univ California
Application granted granted Critical
Publication of ATE486409T1 publication Critical patent/ATE486409T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Dc Digital Transmission (AREA)
AT03749010T 2002-09-03 2003-08-07 Ereignisgesteuerte dynamische logik für verringerte stromaufnahme ATE486409T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US40840702P 2002-09-03 2002-09-03
US10/325,594 US6977528B2 (en) 2002-09-03 2002-12-20 Event driven dynamic logic for reducing power consumption
PCT/US2003/024833 WO2004023240A2 (en) 2002-09-03 2003-08-07 Event driven dynamic logic for reducing power consumption

Publications (1)

Publication Number Publication Date
ATE486409T1 true ATE486409T1 (de) 2010-11-15

Family

ID=31981095

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03749010T ATE486409T1 (de) 2002-09-03 2003-08-07 Ereignisgesteuerte dynamische logik für verringerte stromaufnahme

Country Status (10)

Country Link
US (1) US6977528B2 (de)
EP (1) EP1537667B1 (de)
JP (1) JP2006511986A (de)
KR (1) KR20050034758A (de)
CN (1) CN1679237B (de)
AT (1) ATE486409T1 (de)
AU (1) AU2003268059A1 (de)
DE (1) DE60334702D1 (de)
TW (1) TWI323086B (de)
WO (1) WO2004023240A2 (de)

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US7839173B1 (en) * 2009-08-11 2010-11-23 Xilinx, Inc. High speed, low power signal level shifter
JP5402852B2 (ja) * 2009-12-04 2014-01-29 富士電機株式会社 レベルシフト回路
US8169246B2 (en) * 2010-02-26 2012-05-01 Apple Inc. Dynamic-to-static converter latch with glitch suppression
US20120106351A1 (en) * 2010-11-03 2012-05-03 Gohel Tushar K Determining a Logic State of a Device
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CN103973296B (zh) * 2013-01-29 2018-04-10 中国航空工业集团公司西安飞机设计研究所 一种基于时序逻辑的双座舱指令综合方法及其电路
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CN103269213A (zh) * 2013-04-11 2013-08-28 南京互信系统工程有限公司 无时钟缓冲器触发器
KR20160069283A (ko) * 2014-12-08 2016-06-16 에스케이하이닉스 주식회사 데이터 출력 회로
US9947406B2 (en) * 2015-02-23 2018-04-17 Qualcomm Incorporated Dynamic tag compare circuits employing P-type field-effect transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and related systems and methods
KR102216807B1 (ko) 2015-03-25 2021-02-19 삼성전자주식회사 반도체 회로
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US9401715B1 (en) * 2015-05-21 2016-07-26 Stmicroelectronics International N.V. Conditional pulse generator circuit for low power pulse triggered flip flop
US10581410B2 (en) * 2015-09-10 2020-03-03 Samsung Electronics Co., Ltd High speed domino-based flip flop
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KR102636098B1 (ko) * 2016-10-31 2024-02-13 삼성전자주식회사 플립 플롭 및 이를 포함하는 반도체 시스템
KR102596875B1 (ko) 2016-11-23 2023-11-01 삼성전자주식회사 플립 플롭
KR102076416B1 (ko) * 2018-07-31 2020-03-17 류성윤 멀티 칩 패키지의 결함 컴포넌트 수정 방법 및 이를 이용한 멀티 칩 패키지
US11048292B2 (en) 2018-12-13 2021-06-29 Nxp Usa, Inc. Duty cycle control for reduced dynamic power consumption
CN109743041B (zh) * 2018-12-30 2021-08-06 成都海光微电子技术有限公司 锁存输入数据的电路、芯片、电子产品及方法
US10715149B1 (en) * 2019-07-16 2020-07-14 Xilinx, Inc. Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements
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CN113098495B (zh) * 2021-06-07 2022-01-04 杭州士兰微电子股份有限公司 包含门电路的数字电路
CN118709645B (zh) * 2024-08-30 2024-11-08 英诺达(成都)电子科技有限公司 泄露功耗计算方法、装置、电子设备、存储介质及计算机程序产品

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Also Published As

Publication number Publication date
CN1679237A (zh) 2005-10-05
JP2006511986A (ja) 2006-04-06
EP1537667B1 (de) 2010-10-27
KR20050034758A (ko) 2005-04-14
US6977528B2 (en) 2005-12-20
TWI323086B (en) 2010-04-01
EP1537667A4 (de) 2005-09-14
CN1679237B (zh) 2010-12-08
WO2004023240A2 (en) 2004-03-18
EP1537667A2 (de) 2005-06-08
DE60334702D1 (de) 2010-12-09
US20040041594A1 (en) 2004-03-04
AU2003268059A8 (en) 2004-03-29
AU2003268059A1 (en) 2004-03-29
TW200408193A (en) 2004-05-16
WO2004023240A3 (en) 2004-07-22

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