ATE171011T1 - Verfahren zur herstellung einer mos-eeprom- transistorzelle mit schwebendem gate - Google Patents

Verfahren zur herstellung einer mos-eeprom- transistorzelle mit schwebendem gate

Info

Publication number
ATE171011T1
ATE171011T1 AT92900715T AT92900715T ATE171011T1 AT E171011 T1 ATE171011 T1 AT E171011T1 AT 92900715 T AT92900715 T AT 92900715T AT 92900715 T AT92900715 T AT 92900715T AT E171011 T1 ATE171011 T1 AT E171011T1
Authority
AT
Austria
Prior art keywords
field oxide
floating gate
drain
walls
design
Prior art date
Application number
AT92900715T
Other languages
English (en)
Inventor
Steven J Schumann
James Cheng Hu
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Application granted granted Critical
Publication of ATE171011T1 publication Critical patent/ATE171011T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
AT92900715T 1990-11-21 1991-11-13 Verfahren zur herstellung einer mos-eeprom- transistorzelle mit schwebendem gate ATE171011T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/616,460 US5086325A (en) 1990-11-21 1990-11-21 Narrow width EEPROM with single diffusion electrode formation

Publications (1)

Publication Number Publication Date
ATE171011T1 true ATE171011T1 (de) 1998-09-15

Family

ID=24469563

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92900715T ATE171011T1 (de) 1990-11-21 1991-11-13 Verfahren zur herstellung einer mos-eeprom- transistorzelle mit schwebendem gate

Country Status (7)

Country Link
US (1) US5086325A (de)
EP (1) EP0511370B1 (de)
JP (1) JP3129438B2 (de)
KR (1) KR100193551B1 (de)
AT (1) ATE171011T1 (de)
DE (1) DE69130163T2 (de)
WO (1) WO1992010002A1 (de)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3344598B2 (ja) * 1993-11-25 2002-11-11 株式会社デンソー 半導体不揮発メモリ装置
EP0757835A1 (de) * 1994-04-29 1997-02-12 Atmel Corporation Nicht-flüchtige hochgeschwindigkeits-eeprom-zelle und verfahren
DE19526012C2 (de) * 1995-07-17 1997-09-11 Siemens Ag Elektrisch lösch- und programmierbare nicht-flüchtige Speicherzelle
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6614692B2 (en) * 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6369422B1 (en) 2001-05-01 2002-04-09 Atmel Corporation Eeprom cell with asymmetric thin window
US7098107B2 (en) * 2001-11-19 2006-08-29 Saifun Semiconductor Ltd. Protective layer in memory device and method therefor
US6583007B1 (en) * 2001-12-20 2003-06-24 Saifun Semiconductors Ltd. Reducing secondary injection effects
US6700818B2 (en) * 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6917544B2 (en) * 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7178004B2 (en) * 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7123532B2 (en) * 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7484329B2 (en) 2003-11-20 2009-02-03 Seaweed Bio-Technology Inc. Technology for cultivation of Porphyra and other seaweeds in land-based sea water ponds
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US20060068551A1 (en) * 2004-09-27 2006-03-30 Saifun Semiconductors, Ltd. Method for embedding NROM
US7638850B2 (en) * 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US20060146624A1 (en) * 2004-12-02 2006-07-06 Saifun Semiconductors, Ltd. Current folding sense amplifier
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
EP1684308A1 (de) 2005-01-19 2006-07-26 Saifun Semiconductors Ltd. Verfahren zur Verhinderung von Feststrukturprogrammierung
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US20070141788A1 (en) * 2005-05-25 2007-06-21 Ilan Bloom Method for embedding non-volatile memory with logic circuitry
US7804126B2 (en) * 2005-07-18 2010-09-28 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US20070096199A1 (en) * 2005-09-08 2007-05-03 Eli Lusky Method of manufacturing symmetric arrays
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US20070087503A1 (en) * 2005-10-17 2007-04-19 Saifun Semiconductors, Ltd. Improving NROM device characteristics using adjusted gate work function
US20070120180A1 (en) * 2005-11-25 2007-05-31 Boaz Eitan Transition areas for dense memory arrays
US7352627B2 (en) * 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) * 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US20070173017A1 (en) * 2006-01-20 2007-07-26 Saifun Semiconductors, Ltd. Advanced non-volatile memory array and method of fabrication thereof
US7760554B2 (en) * 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7692961B2 (en) * 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7701779B2 (en) * 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7605579B2 (en) * 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US8963971B2 (en) 2010-06-04 2015-02-24 Think Laboratory Co., Ltd Laser exposure method and product
IN2014CN04042A (de) 2012-02-07 2015-10-23 Think Labs Kk

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4132904A (en) * 1977-07-28 1979-01-02 Hughes Aircraft Company Volatile/non-volatile logic latch circuit
US4203158A (en) * 1978-02-24 1980-05-13 Intel Corporation Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
US4377818A (en) * 1978-11-02 1983-03-22 Texas Instruments Incorporated High density electrically programmable ROM
US4375087C1 (en) * 1980-04-09 2002-01-01 Hughes Aircraft Co Electrically erasable programmable read-only memory
US4477825A (en) * 1981-12-28 1984-10-16 National Semiconductor Corporation Electrically programmable and erasable memory cell
JPS58147154A (ja) * 1982-02-26 1983-09-01 Toshiba Corp 不揮発性半導体メモリ装置
US4822750A (en) * 1983-08-29 1989-04-18 Seeq Technology, Inc. MOS floating gate memory cell containing tunneling diffusion region in contact with drain and extending under edges of field oxide
DE3481667D1 (de) * 1983-08-29 1990-04-19 Seeq Technology Inc Mos-speicherzelle mit schwimmendem gate und verfahren zu ihrer verfertigung.
JPS60161673A (ja) * 1984-02-02 1985-08-23 Toshiba Corp 不揮発性半導体メモリ
EP0164605B1 (de) * 1984-05-17 1990-02-28 Kabushiki Kaisha Toshiba Verfahren zur Herstellung eines nichtflüchtigen Halbleiter-EEPROM-Elementes
JPS6415985A (en) * 1987-07-09 1989-01-19 Fujitsu Ltd Manufacture of semiconductor device
JPS6437876A (en) * 1987-08-03 1989-02-08 Fujitsu Ltd Manufacture of semiconductor device
JP2672530B2 (ja) * 1987-10-30 1997-11-05 松下電子工業株式会社 半導体記憶装置の製造方法
US4851361A (en) * 1988-02-04 1989-07-25 Atmel Corporation Fabrication process for EEPROMS with high voltage transistors
US5008721A (en) * 1988-07-15 1991-04-16 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel
FR2638285B1 (fr) * 1988-10-25 1992-06-19 Commissariat Energie Atomique Circuit integre a haute densite d'integration tel que memoire eprom et procede d'obtention correspondant
JPH081933B2 (ja) * 1989-12-11 1996-01-10 株式会社東芝 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
WO1992010002A1 (en) 1992-06-11
EP0511370A1 (de) 1992-11-04
DE69130163T2 (de) 1999-05-20
US5086325A (en) 1992-02-04
DE69130163D1 (de) 1998-10-15
EP0511370A4 (en) 1993-04-21
JP3129438B2 (ja) 2001-01-29
KR100193551B1 (ko) 1999-07-01
KR920704358A (ko) 1992-12-19
JPH05508262A (ja) 1993-11-18
EP0511370B1 (de) 1998-09-09

Similar Documents

Publication Publication Date Title
ATE171011T1 (de) Verfahren zur herstellung einer mos-eeprom- transistorzelle mit schwebendem gate
EP0389721A3 (de) Flash-EPROM-Zelle und Verfahren zu ihrer Herstellung
US5479367A (en) N-channel single polysilicon level EPROM cell
ATE104473T1 (de) Elektrisch programmierbare eintransistorvorrichtung und verfahren.
KR970007965B1 (en) Structure and fabrication method of tft
KR970072485A (ko) 반도체 장치 및 그 제조 방법
KR960008735B1 (en) Mos transistor and the manufacturing method thereof
DE3481667D1 (de) Mos-speicherzelle mit schwimmendem gate und verfahren zu ihrer verfertigung.
ATE510300T1 (de) Verfahren zur herstellung einer vertikalen mos- transistoranordnung
KR930005272A (ko) Ldd형 mos 트랜지스터 및 그의 제조방법
KR940016927A (ko) 트렌치(Trench) 구조를 이용한 수직 채널을 갖는 모스트랜지스터(MOS-FET) 제조방법
JPS57153474A (en) Manufacture of insulation gate field effect transistor
DE3472500D1 (en) Method of making floating gate mos field-effect transistor memory cells
KR910017645A (ko) 반도체불휘발성메모리 및 그 제조방법
JPS6469054A (en) Manufacture of mis type transistor
RU2002130226A (ru) Способ изготовления мдп транзистора с локальными участками захороненного изолятора
JPS5710265A (en) Field effect transistor
JPS57120371A (en) Manufacture of complementary type mos semiconductor
JPS5772379A (en) Manufacture of semiconductor devuce
KR100198607B1 (ko) 마스크 롬 제조방법
KR940010308A (ko) 박막 트랜지스터 및 그 제조 방법
KR910019204A (ko) 슬롭형 게이트를 이용한 ldd제조방법
TW370712B (en) Method for manufacturing ETOX cell without hurting drains
JPS572579A (en) Manufacture of junction type field effect transistor
TW251387B (en) Process of flash memory

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties