ATE135848T1 - Verfahren zum herstellen einer halbleiteranordnung mit einer ausrichtungsmarke - Google Patents

Verfahren zum herstellen einer halbleiteranordnung mit einer ausrichtungsmarke

Info

Publication number
ATE135848T1
ATE135848T1 AT91305871T AT91305871T ATE135848T1 AT E135848 T1 ATE135848 T1 AT E135848T1 AT 91305871 T AT91305871 T AT 91305871T AT 91305871 T AT91305871 T AT 91305871T AT E135848 T1 ATE135848 T1 AT E135848T1
Authority
AT
Austria
Prior art keywords
semiconductor device
making
alignment mark
apertures
forming
Prior art date
Application number
AT91305871T
Other languages
English (en)
Inventor
Takahiko C O Canon Kabus Okabe
Genzo C O Canon Kabushik Monma
Hiroshi C O Canon K Yuzurihara
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2169949A external-priority patent/JPH0461219A/ja
Priority claimed from JP2169948A external-priority patent/JP2863277B2/ja
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of ATE135848T1 publication Critical patent/ATE135848T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
AT91305871T 1990-06-29 1991-06-28 Verfahren zum herstellen einer halbleiteranordnung mit einer ausrichtungsmarke ATE135848T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2169949A JPH0461219A (ja) 1990-06-29 1990-06-29 半導体装置、その製造方法およびアライメント法
JP2169948A JP2863277B2 (ja) 1990-06-29 1990-06-29 半導体装置、その製造方法およびアライメント法

Publications (1)

Publication Number Publication Date
ATE135848T1 true ATE135848T1 (de) 1996-04-15

Family

ID=26493124

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91305871T ATE135848T1 (de) 1990-06-29 1991-06-28 Verfahren zum herstellen einer halbleiteranordnung mit einer ausrichtungsmarke

Country Status (7)

Country Link
US (2) US5482893A (de)
EP (1) EP0465152B1 (de)
KR (1) KR940010490B1 (de)
CN (1) CN1024730C (de)
AT (1) ATE135848T1 (de)
DE (1) DE69118031T2 (de)
MY (1) MY109605A (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0608628A3 (de) * 1992-12-25 1995-01-18 Kawasaki Steel Co Verfahren zur Herstellung einer Halbleitervorrichtung mit Mehrlagen-Verbindungsstruktur.
JPH0831575B2 (ja) * 1993-02-12 1996-03-27 日本電気株式会社 半導体記憶装置
JP3219909B2 (ja) * 1993-07-09 2001-10-15 株式会社東芝 半導体装置の製造方法
KR0135840B1 (ko) * 1994-07-26 1998-04-29 김광호 개구부 매몰(filling)장치와 이를 이용한 반도체소자 제조방법
JP3528350B2 (ja) * 1995-08-25 2004-05-17 ソニー株式会社 半導体装置の製造方法
US5904563A (en) * 1996-05-20 1999-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for metal alignment mark generation
US6020263A (en) * 1996-10-31 2000-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of recovering alignment marks after chemical mechanical polishing of tungsten
US5898227A (en) * 1997-02-18 1999-04-27 International Business Machines Corporation Alignment targets having enhanced contrast
US5783490A (en) * 1997-04-21 1998-07-21 Vanguard International Semiconductor Corporation Photolithography alignment mark and manufacturing method
US5972793A (en) * 1997-06-09 1999-10-26 Vanguard International Semiconductor Corporation Photolithography alignment mark manufacturing process in tungsten CMP metallization
US5863825A (en) * 1997-09-29 1999-01-26 Lsi Logic Corporation Alignment mark contrast enhancement
US6184104B1 (en) 1998-09-10 2001-02-06 Chartered Semiconductor Manufacturing Ltd. Alignment mark strategy for oxide CMP
DE19903196A1 (de) * 1999-01-27 2000-08-10 Siemens Ag Verfahren zur Verbesserung der Erkennbarkeit von Alignmentmarken
KR100293378B1 (ko) * 1999-08-31 2001-06-15 윤종용 반도체 장치의 제조방법
DE10000759C1 (de) * 2000-01-11 2001-05-23 Infineon Technologies Ag Verfahren zur Erzeugung von Justiermarken
US6780775B2 (en) * 2001-01-24 2004-08-24 Infineon Technologies Ag Design of lithography alignment and overlay measurement marks on CMP finished damascene surface
JP4468609B2 (ja) * 2001-05-21 2010-05-26 株式会社ルネサステクノロジ 半導体装置
US6979526B2 (en) * 2002-06-03 2005-12-27 Infineon Technologies Ag Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs
US6858441B2 (en) * 2002-09-04 2005-02-22 Infineon Technologies Ag MRAM MTJ stack to conductive line alignment method
US7508034B2 (en) * 2002-09-25 2009-03-24 Sharp Kabushiki Kaisha Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device
US7675174B2 (en) 2003-05-13 2010-03-09 Stmicroelectronics, Inc. Method and structure of a thick metal layer using multiple deposition chambers
CN100426476C (zh) * 2003-06-24 2008-10-15 国际商业机器公司 具有凹陷的对准标记的平面磁隧道结衬底
TWI288428B (en) * 2004-01-21 2007-10-11 Seiko Epson Corp Alignment method, method for manufacturing a semiconductor device, substrate for a semiconductor device, electronic equipment
US7223612B2 (en) * 2004-07-26 2007-05-29 Infineon Technologies Ag Alignment of MTJ stack to conductive lines in the absence of topography
US7442624B2 (en) * 2004-08-02 2008-10-28 Infineon Technologies Ag Deep alignment marks on edge chips for subsequent alignment of opaque layers
JP4968063B2 (ja) * 2005-03-01 2012-07-04 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP4610447B2 (ja) * 2005-08-31 2011-01-12 Ｏｋｉセミコンダクタ株式会社 半導体装置とその製造方法及び検査方法
JP2008166351A (ja) * 2006-12-27 2008-07-17 Nec Electronics Corp 半導体装置
JP2011238652A (ja) * 2010-05-06 2011-11-24 Renesas Electronics Corp 半導体装置およびその製造方法
CN102569257B (zh) * 2010-12-08 2016-01-20 无锡华润上华科技有限公司 线宽测试结构
WO2018117654A1 (ko) 2016-12-20 2018-06-28 에스케이이노베이션 주식회사 파우치형 이차 전지 및 이의 제조 방법
US10515903B2 (en) * 2018-05-18 2019-12-24 International Business Machines Corporation Selective CVD alignment-mark topography assist for non-volatile memory
CN113903657A (zh) * 2021-09-27 2022-01-07 材料科学姑苏实验室 一种芯片的制作方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60229334A (ja) * 1984-04-26 1985-11-14 Fujitsu Ltd 半導体装置の製造方法
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material
EP0199030A3 (de) * 1985-04-11 1987-08-26 Siemens Aktiengesellschaft Verfahren zum Herstellen einer Mehrlagenverdrahtung von integrierten Halbleiterschaltungen mit mindestens einer aus einer Aluminiumlegierung bestehenden Leitbahnebene mit Kontaktlochauffüllung
US4630357A (en) * 1985-08-02 1986-12-23 Ncr Corporation Method for forming improved contacts between interconnect layers of an integrated circuit
US4632724A (en) * 1985-08-19 1986-12-30 International Business Machines Corporation Visibility enhancement of first order alignment marks
DE3735449A1 (de) * 1987-10-20 1989-05-03 Convac Gmbh Fertigungssystem fuer halbleitersubstrate
JP2788275B2 (ja) * 1988-06-06 1998-08-20 キヤノン株式会社 半導体装置の製造方法
JPH0230113A (ja) * 1988-07-20 1990-01-31 Sony Corp 半導体集積回路装置
JPH0250414A (ja) * 1988-08-12 1990-02-20 Oki Electric Ind Co Ltd 半導体素子の製造方法
PT95232B (pt) * 1989-09-09 1998-06-30 Canon Kk Processo de producao de uma pelicula de aluminio depositada

Also Published As

Publication number Publication date
MY109605A (en) 1997-03-31
CN1061872A (zh) 1992-06-10
CN1024730C (zh) 1994-05-25
EP0465152A3 (en) 1992-04-15
KR920001622A (ko) 1992-01-30
DE69118031T2 (de) 1996-09-05
EP0465152A2 (de) 1992-01-08
US5663099A (en) 1997-09-02
KR940010490B1 (ko) 1994-10-24
DE69118031D1 (de) 1996-04-25
EP0465152B1 (de) 1996-03-20
US5482893A (en) 1996-01-09

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