ATE131948T1 - Transformationsverarbeitungsschaltung - Google Patents

Transformationsverarbeitungsschaltung

Info

Publication number
ATE131948T1
ATE131948T1 AT88907212T AT88907212T ATE131948T1 AT E131948 T1 ATE131948 T1 AT E131948T1 AT 88907212 T AT88907212 T AT 88907212T AT 88907212 T AT88907212 T AT 88907212T AT E131948 T1 ATE131948 T1 AT E131948T1
Authority
AT
Austria
Prior art keywords
circuit
fft
ifft
input
sample points
Prior art date
Application number
AT88907212T
Other languages
English (en)
Inventor
Kien Thanh Hua
John David O'sullivan
Colin Eric Jacka
David Ross Brown
Original Assignee
Commw Scient Ind Res Org
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commw Scient Ind Res Org filed Critical Commw Scient Ind Res Org
Application granted granted Critical
Publication of ATE131948T1 publication Critical patent/ATE131948T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/14Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141Discrete Fourier transforms
    • G06F17/142Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/015Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising having at least two separately controlled shifting levels, e.g. using shifting matrices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4806Computations with complex numbers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Discrete Mathematics (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Complex Calculations (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Hardware Redundancy (AREA)
  • Radar Systems Or Details Thereof (AREA)
AT88907212T 1987-08-21 1988-08-22 Transformationsverarbeitungsschaltung ATE131948T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AUPI388887 1987-08-21

Publications (1)

Publication Number Publication Date
ATE131948T1 true ATE131948T1 (de) 1996-01-15

Family

ID=3772401

Family Applications (1)

Application Number Title Priority Date Filing Date
AT88907212T ATE131948T1 (de) 1987-08-21 1988-08-22 Transformationsverarbeitungsschaltung

Country Status (8)

Country Link
US (1) US5297070A (de)
EP (1) EP0377604B1 (de)
JP (1) JPH02504682A (de)
KR (1) KR890702151A (de)
AT (1) ATE131948T1 (de)
AU (1) AU610934B2 (de)
DE (1) DE3854818T2 (de)
WO (1) WO1989001668A1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0569438A1 (de) * 1991-01-31 1993-11-18 Ecogen Inc BACILLUS THURINGIENSIS-CRYIIIC(b) TOXINGEN UND PROTEIN, DAS TOXISCH FUER COLEOPETERAN-INSEKTEN IST
DE4130451B4 (de) * 1991-09-13 2004-09-16 Diehl Stiftung & Co.Kg Schaltungsstruktur zur Durchführung der schnellen Fourier-Transformation
US5682340A (en) * 1995-07-03 1997-10-28 Motorola, Inc. Low power consumption circuit and method of operation for implementing shifts and bit reversals
SE509108C2 (sv) * 1997-01-15 1998-12-07 Ericsson Telefon Ab L M Förfarande och anordning för beräkning av FFT
KR100201946B1 (ko) * 1997-03-19 1999-06-15 윤종용 Fft 망의 첵섬 계산장치 및 방법
US6035313A (en) * 1997-03-24 2000-03-07 Motorola, Inc. Memory address generator for an FFT
US6169723B1 (en) * 1997-07-02 2001-01-02 Telefonaktiebolaget Lm Ericsson Computationally efficient analysis and synthesis of real signals using discrete fourier transforms and inverse discrete fourier transforms
JP3900670B2 (ja) * 1998-04-17 2007-04-04 ソニー株式会社 通信装置
US6240141B1 (en) 1998-05-09 2001-05-29 Centillium Communications, Inc. Lower-complexity peak-to-average reduction using intermediate-result subset sign-inversion for DSL
SE9802059D0 (sv) * 1998-06-10 1998-06-10 Ericsson Telefon Ab L M Digital channeliser and De-shanneliser
US6532484B1 (en) * 1999-06-21 2003-03-11 Sun Microsystems, Inc. Parallel system and method for performing fast fourier transform
US6477554B1 (en) * 1999-09-17 2002-11-05 Globespanvirata, Inc. Circuit and method for computing a fast fourier transform
KR100477649B1 (ko) * 2002-06-05 2005-03-23 삼성전자주식회사 다양한 프레임 사이즈를 지원하는 정수 코딩 방법 및 그를적용한 코덱 장치
TWI281619B (en) * 2002-12-20 2007-05-21 Realtek Semiconductor Corp Data processing structure and method for fast Fourier transformation/inverse fast Fourier transformation
JP2008506191A (ja) * 2004-07-08 2008-02-28 アソクス リミテッド 可変サイズの高速直交変換を実施する方法および機器
SG133451A1 (en) * 2005-12-30 2007-07-30 Oki Techno Ct Singapore Pte A processor and method for performing a fast fourier transform and/or an inverse fast fourier transform of a complex input signal
US7702713B2 (en) * 2006-03-24 2010-04-20 Debashis Goswami High speed FFT hardware architecture for an OFDM processor
US8275822B2 (en) * 2007-01-10 2012-09-25 Analog Devices, Inc. Multi-format multiplier unit
US20090172062A1 (en) * 2007-12-31 2009-07-02 Broadcom Corporation Efficient fixed-point implementation of an fft
US8572148B1 (en) * 2009-02-23 2013-10-29 Xilinx, Inc. Data reorganizer for fourier transformation of parallel data streams
US8583718B2 (en) * 2010-08-17 2013-11-12 Fujitsu Limited Comparing boolean functions representing sensor data
US8787422B2 (en) * 2011-12-13 2014-07-22 Qualcomm Incorporated Dual fixed geometry fast fourier transform (FFT)
US9459865B2 (en) * 2011-12-23 2016-10-04 Intel Corporation Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction
EP3583617B1 (de) * 2017-02-14 2024-08-21 Heldeis, Christoph Verfahren zum betreiben eines aktiven eingabeelements und entsprechendes eingabeelement, eingabeanordnung und computerprogrammprodukt

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3174106A (en) * 1961-12-04 1965-03-16 Sperry Rand Corp Shift-register employing rows of flipflops having serial input and output but with parallel shifting between rows
US3673399A (en) * 1970-05-28 1972-06-27 Ibm Fft processor with unique addressing
US3702393A (en) * 1970-10-21 1972-11-07 Bell Telephone Labor Inc Cascade digital fast fourier analyzer
US3892956A (en) * 1971-12-27 1975-07-01 Bell Telephone Labor Inc Cascade digital fast fourier analyzer
US3818203A (en) * 1973-08-27 1974-06-18 Honeywell Inc Matrix shifter
US3943347A (en) * 1974-11-27 1976-03-09 Rca Corporation Data processor reorder random access memory
FR2326743A1 (fr) * 1975-10-02 1977-04-29 Thomson Csf Calculateur de transformee de fourier discrete
JPS549543A (en) * 1977-06-24 1979-01-24 Hitachi Ltd Signal processing system
JPS5523501A (en) * 1978-06-29 1980-02-20 Fujitsu Ltd Shift operation unit
US4181976A (en) * 1978-10-10 1980-01-01 Raytheon Company Bit reversing apparatus
US4241411A (en) * 1978-11-16 1980-12-23 Probe Systems, Incorporated FFT Parallel processor having mutually connected, multiple identical cards
US4547862A (en) * 1982-01-11 1985-10-15 Trw Inc. Monolithic fast fourier transform circuit
US4563750A (en) * 1983-03-04 1986-01-07 Clarke William L Fast Fourier transform apparatus with data timing schedule decoupling
US4689762A (en) * 1984-09-10 1987-08-25 Sanders Associates, Inc. Dynamically configurable fast Fourier transform butterfly circuit
JPS6178240A (ja) * 1984-09-25 1986-04-21 Nippon Telegr & Teleph Corp <Ntt> Des暗号装置
EP0197122B1 (de) * 1984-10-16 1992-08-12 The Commonwealth Of Australia Zellularer gleitkommamultiplizierer mit seriellem fliessbandbetrieb
US4984189A (en) * 1985-04-03 1991-01-08 Nec Corporation Digital data processing circuit equipped with full bit string reverse control circuit and shifter to perform full or partial bit string reverse operation and data shift operation
JPS62175866A (ja) * 1986-01-30 1987-08-01 Nec Corp シグナルプロセツサ

Also Published As

Publication number Publication date
AU2327388A (en) 1989-03-09
WO1989001668A1 (en) 1989-02-23
JPH02504682A (ja) 1990-12-27
US5297070A (en) 1994-03-22
EP0377604B1 (de) 1995-12-20
AU610934B2 (en) 1991-05-30
EP0377604A4 (en) 1991-09-18
DE3854818D1 (de) 1996-02-01
KR890702151A (ko) 1989-12-23
EP0377604A1 (de) 1990-07-18
DE3854818T2 (de) 1996-05-15

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