AT524458A3 - Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren - Google Patents
Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren Download PDFInfo
- Publication number
- AT524458A3 AT524458A3 ATA50956/2021A AT509562021A AT524458A3 AT 524458 A3 AT524458 A3 AT 524458A3 AT 509562021 A AT509562021 A AT 509562021A AT 524458 A3 AT524458 A3 AT 524458A3
- Authority
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- Austria
- Prior art keywords
- chip
- contact layer
- chip module
- conductive adhesive
- conductive
- Prior art date
Links
- 238000010998 test method Methods 0.000 title 1
- 239000000853 adhesive Substances 0.000 abstract 4
- 230000001070 adhesive effect Effects 0.000 abstract 4
- 229910000679 solder Inorganic materials 0.000 abstract 1
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- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Remote Sensing (AREA)
- Radar, Positioning & Navigation (AREA)
- Computer Networks & Wireless Communication (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Electromagnetism (AREA)
- Environmental & Geological Engineering (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Signal Processing (AREA)
- Wire Bonding (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Die vorliegende Anmeldung betrifft ein Chipmodul, umfassend einen Chip (1), aufweisend eine Vor- der- und eine Rückseite (12); einen Chipträger (2), aufweisend eine dem Chip (1) zugewandte Oberseite (21); eine auf der Oberseite (21) des Chipträger (2)s und zwischen der Rückseite (12) des Chips (1) und der Oberseite (21) des Chipträger (2)s angeordnete leitfähige Kontaktschicht (3), ein auf einer dem Chip (1) zugewandten Oberseite (21) der Kontaktschicht (3) zumindest bereichsweise angeordneter, elektrisch leitfähiger Klebstoff (4), der die Oberseite (21) der Kontaktschicht (3) und eine Rückseite (12) des Chips (1) miteinander verbindet. Die Kontaktschicht (3) weist zumindest zwei voneinander elektrisch isolierte Bereiche (3A, 3B) auf, die jeweils über den im jeweiligen isolierten Bereich (3A, 3B) auf der Oberseite (21) der Kontaktschicht (3) angeordneten leitfähigen Klebstoff (4) mit dem Chip (1) elektrisch verbunden sind. Ein leitfähiger Klebstoff (4) kann in der vorliegenden Anmeldung sowohl ein leitfähiger Klebstoff (4) im engeren Sinne als auch eine geeignete leitfähige Verbindung sein, z.B. Lot.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102020215388.4A DE102020215388A1 (de) | 2020-12-04 | 2020-12-04 | Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren |
Publications (2)
Publication Number | Publication Date |
---|---|
AT524458A2 AT524458A2 (de) | 2022-06-15 |
AT524458A3 true AT524458A3 (de) | 2023-03-15 |
Family
ID=81655432
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ATA50956/2021A AT524458A3 (de) | 2020-12-04 | 2021-11-30 | Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren |
Country Status (5)
Country | Link |
---|---|
US (1) | US20220181247A1 (de) |
CN (1) | CN114597186A (de) |
AT (1) | AT524458A3 (de) |
CH (1) | CH718117B1 (de) |
DE (1) | DE102020215388A1 (de) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19831634A1 (de) * | 1998-07-15 | 2000-01-27 | Pac Tech Gmbh | Chipträgeranordnung sowie Verfahren zur Herstellung einer Chipträgeranordnung mit elektrischem Test |
GB2516234A (en) * | 2013-07-15 | 2015-01-21 | Novalia Ltd | Circuit sheet arrangement |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7198969B1 (en) * | 1990-09-24 | 2007-04-03 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US6774315B1 (en) * | 2000-05-24 | 2004-08-10 | International Business Machines Corporation | Floating interposer |
US6936495B1 (en) * | 2002-01-09 | 2005-08-30 | Bridge Semiconductor Corporation | Method of making an optoelectronic semiconductor package device |
US8648473B2 (en) * | 2012-03-27 | 2014-02-11 | Infineon Technologies Ag | Chip arrangement and a method for forming a chip arrangement |
US8991711B2 (en) | 2012-07-19 | 2015-03-31 | Infineon Technologies Ag | Chip card module |
US9147671B2 (en) * | 2014-02-26 | 2015-09-29 | J-Devices Corporation | Semiconductor device, semiconductor stacked module structure, stacked module structure and method of manufacturing same |
US10678046B2 (en) * | 2018-03-21 | 2020-06-09 | Infineon Technologies Ag | Packages for microelectromechanical system (MEMS) mirror and methods of manufacturing the same |
-
2020
- 2020-12-04 DE DE102020215388.4A patent/DE102020215388A1/de active Pending
-
2021
- 2021-11-04 US US17/518,987 patent/US20220181247A1/en active Pending
- 2021-11-30 AT ATA50956/2021A patent/AT524458A3/de not_active Application Discontinuation
- 2021-12-01 CH CH070628/2021A patent/CH718117B1/de unknown
- 2021-12-02 CN CN202111458775.XA patent/CN114597186A/zh active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19831634A1 (de) * | 1998-07-15 | 2000-01-27 | Pac Tech Gmbh | Chipträgeranordnung sowie Verfahren zur Herstellung einer Chipträgeranordnung mit elektrischem Test |
GB2516234A (en) * | 2013-07-15 | 2015-01-21 | Novalia Ltd | Circuit sheet arrangement |
Also Published As
Publication number | Publication date |
---|---|
US20220181247A1 (en) | 2022-06-09 |
CH718117B1 (de) | 2023-06-15 |
AT524458A2 (de) | 2022-06-15 |
CH718117A2 (de) | 2022-06-15 |
CH718117A8 (de) | 2022-08-15 |
DE102020215388A1 (de) | 2022-06-09 |
CN114597186A (zh) | 2022-06-07 |
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