AT524458A3 - Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren - Google Patents

Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren Download PDF

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Publication number
AT524458A3
AT524458A3 ATA50956/2021A AT509562021A AT524458A3 AT 524458 A3 AT524458 A3 AT 524458A3 AT 509562021 A AT509562021 A AT 509562021A AT 524458 A3 AT524458 A3 AT 524458A3
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AT
Austria
Prior art keywords
chip
contact layer
chip module
conductive adhesive
conductive
Prior art date
Application number
ATA50956/2021A
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English (en)
Other versions
AT524458A2 (de
Inventor
Dobritz Stefan
Findeisen Christoph
Pierschel Dr -Ing Michael
Original Assignee
First Sensor AG
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Publication date
Application filed by First Sensor AG filed Critical First Sensor AG
Publication of AT524458A2 publication Critical patent/AT524458A2/de
Publication of AT524458A3 publication Critical patent/AT524458A3/de

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    • HELECTRICITY
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

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  • Signal Processing (AREA)
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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Die vorliegende Anmeldung betrifft ein Chipmodul, umfassend einen Chip (1), aufweisend eine Vor- der- und eine Rückseite (12); einen Chipträger (2), aufweisend eine dem Chip (1) zugewandte Oberseite (21); eine auf der Oberseite (21) des Chipträger (2)s und zwischen der Rückseite (12) des Chips (1) und der Oberseite (21) des Chipträger (2)s angeordnete leitfähige Kontaktschicht (3), ein auf einer dem Chip (1) zugewandten Oberseite (21) der Kontaktschicht (3) zumindest bereichsweise angeordneter, elektrisch leitfähiger Klebstoff (4), der die Oberseite (21) der Kontaktschicht (3) und eine Rückseite (12) des Chips (1) miteinander verbindet. Die Kontaktschicht (3) weist zumindest zwei voneinander elektrisch isolierte Bereiche (3A, 3B) auf, die jeweils über den im jeweiligen isolierten Bereich (3A, 3B) auf der Oberseite (21) der Kontaktschicht (3) angeordneten leitfähigen Klebstoff (4) mit dem Chip (1) elektrisch verbunden sind. Ein leitfähiger Klebstoff (4) kann in der vorliegenden Anmeldung sowohl ein leitfähiger Klebstoff (4) im engeren Sinne als auch eine geeignete leitfähige Verbindung sein, z.B. Lot.
ATA50956/2021A 2020-12-04 2021-11-30 Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren AT524458A3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102020215388.4A DE102020215388A1 (de) 2020-12-04 2020-12-04 Chipmodul, Verwendung des Chipmoduls, Prüfanordnung sowie Prüfverfahren

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AT524458A2 AT524458A2 (de) 2022-06-15
AT524458A3 true AT524458A3 (de) 2023-03-15

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US (1) US20220181247A1 (de)
CN (1) CN114597186A (de)
AT (1) AT524458A3 (de)
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Citations (2)

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Publication number Priority date Publication date Assignee Title
DE19831634A1 (de) * 1998-07-15 2000-01-27 Pac Tech Gmbh Chipträgeranordnung sowie Verfahren zur Herstellung einer Chipträgeranordnung mit elektrischem Test
GB2516234A (en) * 2013-07-15 2015-01-21 Novalia Ltd Circuit sheet arrangement

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US7198969B1 (en) * 1990-09-24 2007-04-03 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US6774315B1 (en) * 2000-05-24 2004-08-10 International Business Machines Corporation Floating interposer
US6936495B1 (en) * 2002-01-09 2005-08-30 Bridge Semiconductor Corporation Method of making an optoelectronic semiconductor package device
US8648473B2 (en) * 2012-03-27 2014-02-11 Infineon Technologies Ag Chip arrangement and a method for forming a chip arrangement
US8991711B2 (en) 2012-07-19 2015-03-31 Infineon Technologies Ag Chip card module
US9147671B2 (en) * 2014-02-26 2015-09-29 J-Devices Corporation Semiconductor device, semiconductor stacked module structure, stacked module structure and method of manufacturing same
US10678046B2 (en) * 2018-03-21 2020-06-09 Infineon Technologies Ag Packages for microelectromechanical system (MEMS) mirror and methods of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19831634A1 (de) * 1998-07-15 2000-01-27 Pac Tech Gmbh Chipträgeranordnung sowie Verfahren zur Herstellung einer Chipträgeranordnung mit elektrischem Test
GB2516234A (en) * 2013-07-15 2015-01-21 Novalia Ltd Circuit sheet arrangement

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US20220181247A1 (en) 2022-06-09
CH718117B1 (de) 2023-06-15
AT524458A2 (de) 2022-06-15
CH718117A2 (de) 2022-06-15
CH718117A8 (de) 2022-08-15
DE102020215388A1 (de) 2022-06-09
CN114597186A (zh) 2022-06-07

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