AR241397A1 - Un controlador de e/s de un dispositivo de computacion de multiples memorias. - Google Patents

Un controlador de e/s de un dispositivo de computacion de multiples memorias.

Info

Publication number
AR241397A1
AR241397A1 AR85300632A AR30063285A AR241397A1 AR 241397 A1 AR241397 A1 AR 241397A1 AR 85300632 A AR85300632 A AR 85300632A AR 30063285 A AR30063285 A AR 30063285A AR 241397 A1 AR241397 A1 AR 241397A1
Authority
AR
Argentina
Prior art keywords
memory
controller
cache
link
common
Prior art date
Application number
AR85300632A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of AR241397A1 publication Critical patent/AR241397A1/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

UN CONTROLADOR DE E/S PARA DISPOSITIVOS DE COMPUTACION DE MULTIPLES MEMORIAS, QUE COMPRENDE: UN ENLACE COMUN DE DISPOSITIVO CON UN MEDIO DE INTERFAZ DISTINTO ASOCIADO A CADA MEMORIA PARA TRANSFERIR DATOS ENTRE LA MEMORIA Y EL ENLACE COMUN; UNA MEMORIA INTERMEDIA Y UN REGISTRO SEPARADOR ASOCIADO CON UNA MEMORIA RAPIDA UNIDOS AL ENLACE COMUN DE DISPOSITIVO; UN PRIMER MEDIO LOGICO DE CONTROL DEL FLUJO DE DATOS SOBRE EL ENLACE COMUN, UN REGISTRO DE CANAL PARA REALIZAR LA INTERFAZ ENTRE EL CONTROLADOR DE E/S Y EL DISPOSITIVO COMPUTADOR; Y UN SEGUNDO MEDIO LOGICO DE CONTROL DEL FLUJODE DATOS ENTRE EL REGISTRO DE BUFFER, LA MEMORIA RAPIDA Y EL REGISTRO DE CANAL.
AR85300632A 1984-06-15 1985-06-05 Un controlador de e/s de un dispositivo de computacion de multiples memorias. AR241397A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US62098184A 1984-06-15 1984-06-15

Publications (1)

Publication Number Publication Date
AR241397A1 true AR241397A1 (es) 1992-06-30

Family

ID=24488225

Family Applications (1)

Application Number Title Priority Date Filing Date
AR85300632A AR241397A1 (es) 1984-06-15 1985-06-05 Un controlador de e/s de un dispositivo de computacion de multiples memorias.

Country Status (9)

Country Link
US (1) US4825357A (es)
EP (1) EP0164550B1 (es)
JP (1) JPS617967A (es)
AR (1) AR241397A1 (es)
AU (1) AU4193585A (es)
BR (1) BR8502592A (es)
CA (1) CA1235231A (es)
DE (1) DE3586299T2 (es)
ES (1) ES8702678A1 (es)

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US5218685A (en) * 1987-01-02 1993-06-08 General Electric Company System for write once read many optical storage devices to appear rewritable
JP2767587B2 (ja) * 1988-02-02 1998-06-18 富士通株式会社 ローカル端末シミュレータ
JPH01204167A (ja) * 1988-02-09 1989-08-16 Fujitsu Ltd ローカル端末シミュレータにおける入出力動作シミュレート方式
US5016121A (en) * 1988-02-25 1991-05-14 Tandon Corporation Disk drive controller system
US5121480A (en) * 1988-07-18 1992-06-09 Western Digital Corporation Data recording system buffer management and multiple host interface control
US5253351A (en) * 1988-08-11 1993-10-12 Hitachi, Ltd. Memory controller with a cache memory and control method of cache memory including steps of determining memory access threshold values
EP0377970B1 (en) * 1989-01-13 1995-08-16 International Business Machines Corporation I/O caching
US5689670A (en) * 1989-03-17 1997-11-18 Luk; Fong Data transferring system with multiple port bus connecting the low speed data storage unit and the high speed data storage unit and the method for transferring data
EP0398523A3 (en) * 1989-05-19 1991-08-21 Hitachi, Ltd. A device for data i/o and execution support in digital processors
JPH03100718A (ja) * 1989-09-13 1991-04-25 Hitachi Ltd バッファ付きディスク装置の入出力処理方法
US5297270A (en) * 1989-11-13 1994-03-22 Zenith Data Systems Corporation Programmable cache memory which associates each section of main memory to be cached with a status bit which enables/disables the caching accessibility of the particular section, and with the capability of functioning with memory areas of varying size
FR2659460B1 (fr) * 1990-03-08 1992-05-22 Bull Sa Sous-systeme peripherique de memoire de masse.
US5289581A (en) * 1990-06-29 1994-02-22 Leo Berenguel Disk driver with lookahead cache
JP2550444B2 (ja) * 1991-03-07 1996-11-06 富士通株式会社 デバイス制御装置
JP2836283B2 (ja) * 1991-04-11 1998-12-14 日本電気株式会社 バッファ管理方式
US5577213A (en) * 1994-06-03 1996-11-19 At&T Global Information Solutions Company Multi-device adapter card for computer
EP0685803B1 (en) 1994-06-03 2001-04-18 Hyundai Electronics America Method of producing an electrical device adapter
US5559422A (en) * 1994-07-01 1996-09-24 Welch Allyn, Inc. Wall transformer
US5661848A (en) * 1994-09-08 1997-08-26 Western Digital Corp Multi-drive controller with encoder circuitry that generates ECC check bytes using the finite field for optical data for appending to data flowing to HDA
US5893147A (en) * 1994-12-22 1999-04-06 Intel Corporation Method and apparatus for distinguishing system memory data from alternative memory data in a shared cache memory
US6421755B1 (en) 1999-05-26 2002-07-16 Dell Usa, L.P. System resource assignment for a hot inserted device
US6728823B1 (en) * 2000-02-18 2004-04-27 Hewlett-Packard Development Company, L.P. Cache connection with bypassing feature
US6701390B2 (en) * 2001-06-06 2004-03-02 Koninklijke Philips Electronics N.V. FIFO buffer that can read and/or write multiple and/or selectable number of data words per bus cycle
US20060282602A1 (en) * 2005-06-09 2006-12-14 Tse-Hsine Liao Data transmission device and method thereof
KR20100085564A (ko) * 2009-01-21 2010-07-29 삼성전자주식회사 데이터 처리 시스템과 데이터 처리 방법
CN102437843B (zh) * 2011-11-30 2013-10-16 中国科学院微电子研究所 高电压开关电路

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US3931615A (en) * 1974-07-22 1976-01-06 Scientific Micro Systems Controller for digital devices
US3980993A (en) * 1974-10-17 1976-09-14 Burroughs Corporation High-speed/low-speed interface for data processing systems
US4084231A (en) * 1975-12-18 1978-04-11 International Business Machines Corporation System for facilitating the copying back of data in disc and tape units of a memory hierarchial system
US4210959A (en) * 1978-05-10 1980-07-01 Apple Computer, Inc. Controller for magnetic disc, recorder, or the like
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US4245307A (en) * 1979-09-14 1981-01-13 Formation, Inc. Controller for data processing system
US4392200A (en) * 1980-01-28 1983-07-05 Digital Equipment Corporation Cached multiprocessor system with pipeline timing
US4371929A (en) * 1980-05-05 1983-02-01 Ibm Corporation Multiprocessor system with high density memory set architecture including partitionable cache store interface to shared disk drive memory
JPS5759243A (en) * 1980-09-26 1982-04-09 Toshiba Corp Buffer circuit
US4394733A (en) * 1980-11-14 1983-07-19 Sperry Corporation Cache/disk subsystem
SE445270B (sv) * 1981-01-07 1986-06-09 Wang Laboratories Dator med ett fickminne, vars arbetscykel er uppdelad i tva delcykler
JPS57120144A (en) * 1981-01-16 1982-07-27 Toshiba Corp Data transfer system
DE3278891D1 (en) * 1981-06-05 1988-09-15 Ibm I/o controller with a dynamically adjustable cache memory
US4476526A (en) * 1981-11-27 1984-10-09 Storage Technology Corporation Cache buffered memory subsystem
US4530055A (en) * 1982-03-03 1985-07-16 Sperry Corporation Hierarchical memory system with variable regulation and priority of writeback from cache memory to bulk memory
US4500958A (en) * 1982-04-21 1985-02-19 Digital Equipment Corporation Memory controller with data rotation arrangement
US4811280A (en) * 1983-06-16 1989-03-07 American Telephone And Telegraph Company Dual mode disk controller

Also Published As

Publication number Publication date
BR8502592A (pt) 1986-02-04
JPS617967A (ja) 1986-01-14
EP0164550A2 (en) 1985-12-18
DE3586299T2 (de) 1993-04-15
EP0164550A3 (en) 1988-08-24
EP0164550B1 (en) 1992-07-08
AU4193585A (en) 1985-12-19
DE3586299D1 (de) 1992-08-13
US4825357A (en) 1989-04-25
CA1235231A (en) 1988-04-12
ES8702678A1 (es) 1986-12-16
JPH0332093B2 (es) 1991-05-09
ES544045A0 (es) 1986-12-16

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