ES2030524T3 - Sistema de conmutacion de informaciones con prioridades. - Google Patents

Sistema de conmutacion de informaciones con prioridades.

Info

Publication number
ES2030524T3
ES2030524T3 ES198888460011T ES88460011T ES2030524T3 ES 2030524 T3 ES2030524 T3 ES 2030524T3 ES 198888460011 T ES198888460011 T ES 198888460011T ES 88460011 T ES88460011 T ES 88460011T ES 2030524 T3 ES2030524 T3 ES 2030524T3
Authority
ES
Spain
Prior art keywords
memory
temporary
outgoing
map
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198888460011T
Other languages
English (en)
Inventor
Jean-Paul Quinquis
Albert Lespagnol
Jacques Yvon Kerberenes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ministere des PTT
Original Assignee
Ministere des PTT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ministere des PTT filed Critical Ministere des PTT
Application granted granted Critical
Publication of ES2030524T3 publication Critical patent/ES2030524T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/205—Quality of Service based
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

EL SISTEMA CONMUTA LOS PAQUETES DE INFORMACION AFECTADOS DE PRIORIDADES SEMANTICAS Y EVENTUALMENTE DE PRIORIDADES TEMPORALES ENTRE LOS MULTIPLEX TEMPORALES ENTRANTES Y LOS MULTIPLEX TEMPORALES SALIENTES. LA DIRECCION DE MEMORIZACION (K) DE UN PAQUETE EN LA MEMORIA TAMPON (MP) DEL SISTEMA ESTA COLOCADA EN CADA FILA DE ESPERA O DOBLE FILA DE ESPERA ASOCIADA A CADA MULTIPLEX TEMPORAL SALIENTE DESTINADO A TRASMITIR EL PAQUETE. COMPRENDE UNA MEMORIA DE CAMPO DE PUNTOS (MAP) CUYAS PALABRAS (ZI) COMPRENDEN CADA UNA TANTOS BITS COMO LOS MULTIPLEX TEMPORALES SALIENTES. LAS DIRECCIONES DE LA MEMORIA (MAP) CORRESPONDEN A LAS DE LA MEMORIA TAMPON (MP). CADA BIT DE UNA PALABRA (ZI) ES UN "1" CUANDO EL PAQUETE MEMORIZADO EN LA MISMA DIRECCION QUE LA PALABRA Y DESTINADO AL MULTIPLEX TEMPORAL SALIENTE QUE CORRESPONDE AL BIT CON UNA PRIORIDAD SEMANTICA DE ALTO NIVEL Y QUE NO HA SIDO AUN TRASMITIDO POR EL MULTIPLEX SALIENTE QUE LE CONCIERNE. CADA DIRECCION DE MEMORIZACION DE EL PAQUETE ESTA ELEGIDO ENTRELAS DIRECCIONES LIBRES DE LA MEMORIA (MAP) DIRIGIENDO LAS PALABRAS (ZI) EN TODOS LOS BITS SITUADOS EN "0". CADA DIRECCION LIBRE DE LA MEMORIA (MAP) ESTA MEMORIZADA EN UNA FILA DE DIRECCIONES LIBRES (ADL) CUYA SALIDA PROPORCIONA AL RITMO DE LLEGADA DE LOS PAQUETES SUS DIRECCIONES DE MEMORIZACION EN LA MEMORIA TAMPON (MP).
ES198888460011T 1987-07-16 1988-07-12 Sistema de conmutacion de informaciones con prioridades. Expired - Lifetime ES2030524T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8710254A FR2618280B1 (fr) 1987-07-16 1987-07-16 Systeme de commutation d'informations a priorites.

Publications (1)

Publication Number Publication Date
ES2030524T3 true ES2030524T3 (es) 1992-11-01

Family

ID=9353335

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198888460011T Expired - Lifetime ES2030524T3 (es) 1987-07-16 1988-07-12 Sistema de conmutacion de informaciones con prioridades.

Country Status (7)

Country Link
US (1) US4864560A (es)
EP (1) EP0300941B1 (es)
JP (1) JP2848400B2 (es)
CA (1) CA1294024C (es)
DE (1) DE3868752D1 (es)
ES (1) ES2030524T3 (es)
FR (1) FR2618280B1 (es)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365519A (en) 1991-03-05 1994-11-15 Hitachi, Ltd. ATM switch1ng system connectable to I/O links having different transmission rates
JP2880271B2 (ja) * 1990-08-17 1999-04-05 株式会社日立製作所 帯域制御方法および回路
US6330240B1 (en) 1987-04-24 2001-12-11 Hitachi, Ltd. ATM cell switching system
USRE36751E (en) * 1987-07-15 2000-06-27 Hitachi, Ltd. ATM switching system connectable to I/O links having different transmission rates
JPH01221042A (ja) * 1988-02-29 1989-09-04 Toshiba Corp パケット交換機の輻輳制御方法
US5008880A (en) * 1988-03-14 1991-04-16 Sharp Kabushiki Kaisha Data transmission apparatus
US5233603A (en) * 1988-04-21 1993-08-03 Nec Corporation Packet switch suitable for integrated circuit implementation
JPH02117243A (ja) * 1988-10-27 1990-05-01 Toshiba Corp パケット通信装置
JPH0758963B2 (ja) * 1989-01-27 1995-06-21 日本電気株式会社 セル交換装置
US5153877A (en) * 1989-04-21 1992-10-06 Kabushiki Kaisha Toshiba Packet network with communication resource allocation and call set up control of higher quality of service
JP2907886B2 (ja) * 1989-09-14 1999-06-21 株式会社日立製作所 スイッチングシステム
JPH03252241A (ja) * 1990-03-01 1991-11-11 Toshiba Corp パケット交換網における呼接続制御法
ATE127643T1 (de) * 1990-03-14 1995-09-15 Alcatel Nv Atm-artiges vermittlungselement mit mehreren betriebsarten und dieses enthaltendes vermittlungsnetzwerk.
NL9000780A (nl) * 1990-04-03 1991-11-01 Nederland Ptt Werkwijze en inrichting voor het doorschakelen van dataeenheden.
US5297137A (en) * 1991-01-30 1994-03-22 International Business Machines Corporation Process for routing data packets around a multi-node communications network
US5361255A (en) * 1991-04-29 1994-11-01 Dsc Communications Corporation Method and apparatus for a high speed asynchronous transfer mode switch
CA2068056C (en) * 1991-05-07 1998-06-16 Kazuo Sakagawa Switching node in label multiplexing type switching network
US5850385A (en) * 1991-09-24 1998-12-15 Kabushiki Kaisha Toshiba Cell loss rate sensitive routing and call admission control method
US5361372A (en) * 1991-12-27 1994-11-01 Digital Equipment Corporation Memory management for data transmission networks
US5418779A (en) * 1994-03-16 1995-05-23 The Trustee Of Columbia University Of New York High-speed switched network architecture
US7058067B1 (en) 1995-03-13 2006-06-06 Cisco Technology, Inc. Distributed interactive multimedia system architecture
US5838683A (en) 1995-03-13 1998-11-17 Selsius Systems Inc. Distributed interactive multimedia system architecture
KR100299119B1 (ko) * 1997-09-30 2001-09-03 윤종용 플래쉬롬제어장치를구비한개인용컴퓨터시스템및그제어방법
US7296100B1 (en) 2003-10-06 2007-11-13 Redpine Signals, Inc. Packet buffer management apparatus and method
US7747734B2 (en) * 2006-03-29 2010-06-29 International Business Machines Corporation Apparatus, system, and method for error assessment over a communication link
US8930872B2 (en) * 2012-02-17 2015-01-06 Netronome Systems, Incorporated Staggered island structure in an island-based network flow processor
US8902902B2 (en) 2012-07-18 2014-12-02 Netronome Systems, Incorporated Recursive lookup with a hardware trie structure that has no sequential logic elements

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3979733A (en) * 1975-05-09 1976-09-07 Bell Telephone Laboratories, Incorporated Digital data communications system packet switch
FR2475330A1 (fr) * 1980-01-31 1981-08-07 Thomson Csf Mat Tel Dispositif d'aiguillage de donnees numeriques
JPS57125439A (en) * 1981-01-28 1982-08-04 Fujitsu Ltd Buffering system
FR2538976A1 (fr) * 1982-12-29 1984-07-06 Servel Michel Systeme de commutation de paquets synchrones de longueur fixe
US4707693A (en) * 1984-06-13 1987-11-17 Hewlett-Packard Company Through-traffic priority protocol in a communications system
US4621359A (en) * 1984-10-18 1986-11-04 Hughes Aircraft Company Load balancing for packet switching nodes

Also Published As

Publication number Publication date
EP0300941B1 (fr) 1992-03-04
FR2618280B1 (fr) 1989-10-20
CA1294024C (en) 1992-01-07
FR2618280A1 (fr) 1989-01-20
DE3868752D1 (de) 1992-04-09
JPH021663A (ja) 1990-01-05
US4864560A (en) 1989-09-05
EP0300941A1 (fr) 1989-01-25
JP2848400B2 (ja) 1999-01-20

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