JPS6448124A - Data transfer device - Google Patents
Data transfer deviceInfo
- Publication number
- JPS6448124A JPS6448124A JP62205407A JP20540787A JPS6448124A JP S6448124 A JPS6448124 A JP S6448124A JP 62205407 A JP62205407 A JP 62205407A JP 20540787 A JP20540787 A JP 20540787A JP S6448124 A JPS6448124 A JP S6448124A
- Authority
- JP
- Japan
- Prior art keywords
- speed
- data
- low
- interfaces
- transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Communication Control (AREA)
Abstract
PURPOSE:To efficiently transfer data between interfaces different in data transfer speed by providing a data storage buffer whose memory space is divided and is assigned to plural access ports. CONSTITUTION:In case of data transfer from plural low-speed interfaces A-N to a high-speed interface, each low-speed adapter 2 accesses one assigned access port 12 of a data storage buffer 1 independently of the other low-speed adapters and writes data in one of memory spaces A-N which is assigned to this access port. A high-speed adapter 3 accesses plural access ports 12 of the buffer 11 in a prescribed order and reads out data of memory spaces A-N in order and transfers this data to the high-speed interface. Data transfer from the high- speed interface to low-speed interfaces is performed in accordance with reverse procedures. Thus, it is unnecessary that plural low-speed interfaces are synchronized with one another, and data is efficiently transferred between interfaces different in transfer speed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62205407A JPS6448124A (en) | 1987-08-19 | 1987-08-19 | Data transfer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62205407A JPS6448124A (en) | 1987-08-19 | 1987-08-19 | Data transfer device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6448124A true JPS6448124A (en) | 1989-02-22 |
Family
ID=16506328
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62205407A Pending JPS6448124A (en) | 1987-08-19 | 1987-08-19 | Data transfer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6448124A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05191468A (en) * | 1992-01-10 | 1993-07-30 | Ashikaga Denshi Kogyo Kk | Data converting device |
US7086709B2 (en) * | 1997-07-15 | 2006-08-08 | Silverbrook Research Pty Ltd | Print engine controller for high volume pagewidth printing |
JP2008097882A (en) * | 2006-10-06 | 2008-04-24 | Sumitomo Electric Fine Polymer Inc | Gasket, sealed secondary battery, and electrolytic capacitor |
CN100405343C (en) * | 2006-06-21 | 2008-07-23 | 北京中星微电子有限公司 | Asynchronous data buffer storage |
-
1987
- 1987-08-19 JP JP62205407A patent/JPS6448124A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05191468A (en) * | 1992-01-10 | 1993-07-30 | Ashikaga Denshi Kogyo Kk | Data converting device |
US7086709B2 (en) * | 1997-07-15 | 2006-08-08 | Silverbrook Research Pty Ltd | Print engine controller for high volume pagewidth printing |
CN100405343C (en) * | 2006-06-21 | 2008-07-23 | 北京中星微电子有限公司 | Asynchronous data buffer storage |
JP2008097882A (en) * | 2006-10-06 | 2008-04-24 | Sumitomo Electric Fine Polymer Inc | Gasket, sealed secondary battery, and electrolytic capacitor |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SE8405456D0 (en) | VERY FAST MEMORY AND MEMORY MANAGEMENT SYSTEM | |
CA2079623A1 (en) | Method and apparatus for providing two parties transparent access to a single-port memory storage device | |
AU4379389A (en) | High speed bus with virtual memory data transfer capability | |
DE69020569D1 (en) | MODULAR INPUT / OUTPUT SYSTEM FOR SUPER COMPUTERS. | |
AU6583090A (en) | Multiplexed serial register architecture for vram | |
EP0259050A3 (en) | Multi-channel memory access circuit | |
JPS6421563A (en) | Information exchanger for multiple processor | |
CA2060820A1 (en) | Direct memory access for data transfer within an i/o device | |
CA2119228A1 (en) | Arrangement for expanding the device capacity of a bus | |
JPS6448124A (en) | Data transfer device | |
CA2234635A1 (en) | Method and device for exchanging data | |
EP0164972A3 (en) | Shared memory multiprocessor system | |
EP0192578A3 (en) | A multiple bus system including a microprocessor having separate instruction and data interfaces and caches | |
EP0269370A3 (en) | Memory access controller | |
EP0568678B1 (en) | Device for transmission of data | |
JPS5563422A (en) | Data transfer system | |
JPS6448163A (en) | Multiprocessor system | |
KR900007098B1 (en) | Art-bus component for sequence control system | |
JPS62154056A (en) | Interface for data communication | |
JPS6217879Y2 (en) | ||
JPS6263351A (en) | Disk cache device | |
JPS55147720A (en) | Multimemory bus | |
JPH02148124A (en) | Magnetic disk controller | |
JPS6415843A (en) | High-speed external memory | |
JPS55140937A (en) | Data processing system |