JPH02148124A - Magnetic disk controller - Google Patents

Abstract

PURPOSE:To obtain a magnetic disk controller which is capable of high-speed transfer and has the bit unit price reduced by arranging plural general purpose magnetic disk devices in parallel to use them. CONSTITUTION:Memory control circuits 2a to 5a access magnetic disk devices 10 to 13 through magnetic disk interface circuits 6 to 9 based on a inputted addresses. Pertinent data of the magnetic disk devices are saved in dual port RAMs 2 to 5. With respect to data transfer from dual ports RAMs 2 to 5 to a memory 16, interleave is applied through a system data bus 17 by memory control circuits 2a to 5a to transfer data at a high speed. Thus, data is transferred at a high speed, and the bit unit price is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic disk control device, and particularly to high-speed data transfer.

[Prior art and problems to be solved by the invention] A conventional magnetic disk control device transfers a large amount of data to and from a magnetic disk device, and if this is desired to be done in a short period of time, the magnetic disk device itself is Although magnetic disk devices with high transfer speeds are used, such magnetic disk devices are expensive and have special interfaces, so they cannot be easily adopted.

There are also magnetic disk devices for parallel transfer (for example, magnetic disk devices for high-speed transfer that have multiple data input/output channels on the same cylinder), but they are special.
It was extremely expensive.

An object of the present invention is to obtain a magnetic disk control device that enables high-speed transfer and lowers the bit unit cost by arranging and using a plurality of general-purpose magnetic disk devices in parallel.

[Means for Solving the Problems] A magnetic disk control device according to the present invention includes a plurality of magnetic disk control circuits provided corresponding to a plurality of magnetic disk devices, a system bus, and a plurality of magnetic disk control circuits. A plurality of storage means each provided between the system bus and the magnetic disk device to save data from the system bus and a plurality of storage means, and a plurality of storage means for interleaving and transferring data exchanged between the system bus and the plurality of storage means. It has a memory control circuit.

[Operation] In the present invention, data is exchanged between the system bus and the plurality of storage means with interleaving. Furthermore, data exchange between the plurality of storage means and the plurality of magnetic disk devices is processed in parallel by the plurality of independent magnetic disk control circuits and the plurality of magnetic disk devices.

[Embodiment] FIG. 1 is a block diagram showing the configuration of a magnetic disk control device according to an embodiment of the present invention. In the figure, (1)
is a CPU, and (2) to (5) are dual port RAMs of 1 Mbyte each. (2a) to (5a) are memory control circuits that control data writing and reading of the dual port RAMs (2) to (5), respectively.

(6) to (9) are magnetic disk interface circuits including a magnetic disk control circuit, and (10) to (13) are magnetic disk devices. (14) is an address decoder, and (15) is a magnetic disk interface control circuit (hereinafter referred to as control circuit).

(16) is a memory as a main storage device, (17) is a system data bus, and (18) is a system address bus.

The dual port RAMs (2) to (5) have ports on the system data bus (17) side and on the magnetic disk interface circuits (8) to (9), respectively. and,
From the system data bus (17) side, an address decoder (14) and memory control circuits (2a) to (5a) form an interleave configuration for dual port RAMs (2) to (5). Further, the magnetic disk interface circuits (6) to (9) are connected to the magnetic disk device (1).
In this case, the serial data from memory (16) is converted to 32 bits, and the 32 bit data from memory (16) is converted to serial data. The magnetic disk devices (lO) to (13) correspond one-to-one to the magnetic disk interface circuits (6) to (9), and are low cost and
It is of small capacity.

The control circuit (15) receives commands from the CPU (1) and sends them to each magnetic disk interface circuit (8).
- (9) and provides the converted commands, and also integrates the statuses from each magnetic disk interface circuit (6) - (9) and notifies the CPU (1).

Next, the operation of the magnetic disk control device configured as described above when a read command and a write command are received from the CPU (1) will be explained.

(1) In case of read command; Read command from CPU (1) (magnetic disk device logical address oooooooo to l 00000
When there is a read (II), the control circuit (15) converts and provides commands and the like for each magnetic disk interface circuit (6) to (9). In addition, an address decoder (14
) converts the address from the system address bus (18) into an address for the dual-port RAMs (2) to (5) and supplies it to each memory control circuit (2a) to (5a). Each memory control circuit (2a)-(5a) controls each magnetic disk interface circuit (6)-(6) based on the input address.
(9) to access the magnetic disk devices (10) to (13). Then, the corresponding data of the magnetic disk device (2) is stored in the dual port RAM (2) to (5).
will be saved. Dual port RAM (2)
The data transfer from ~(5) to the memory (lG) is performed at high speed by interleaving via the system data bus (17) by the memory control circuits (2a) to (5a), and the transferred data is written into the memory (16).

When the control circuit (5) recognizes that all the magnetic disk interface circuits (6) to (9) have finished executing the read command, it notifies the CPU (1) as a status.

(2) In the case of a write command; Write command from CPU (1) (magnetic disk device logical address 0000000ff to 1000001
1 write), the control circuit (15) converts and provides commands and the like for each of the magnetic disk interface circuits (6) to (9). Further, the address decoder (14) converts the address from the system address bus (18) into an address for dual port RAM (2) to (5) and provides it to each memory control circuit (2a) to (5a). . Each memory control circuit (2a) to (5a) causes the dual port RAMs (2) to (5) to save the necessary amount of data from the system data bus (17) based on the input address. Data transfer from this memory (16) to the dual port RAMs (2) to (5) is carried out by the system data bus (17) by memory control circuits (2a) to (5a).
) is interleaved and transferred at high speed.

The data saved in dual port RAM (2) to (5) is transferred to each magnetic disk interface circuit (6).
~ (9) via magnetic disk device (lO) ~ (13)
will be written to the corresponding address.

When the control circuit (15) recognizes that all the magnetic disk interface circuits (6) to (9) have finished executing the write command, it notifies the CPU (1) as a status.

[Effects of the Invention] As described above, according to the present invention, data is exchanged between the system bus and the plurality of storage means by interleaving, so that the throughput of the system bus is improved. In addition, data exchange between multiple storage means and multiple magnetic disk devices is processed in parallel by multiple independent magnetic disk control circuits and multiple magnetic disk devices, so the bit width is widened. Serial transfer now appears to be parallel transfer, and the transfer speed increases in proportion to the number of data processing mechanisms arranged in parallel.
Also, the capacity in terms of number of units is increasing.

For this reason, high-speed transfer is possible even when using a general-purpose magnetic disk device, and the cost per bit can therefore be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a magnetic disk control device according to an embodiment of the present invention. In the figure, (1) is a CPU, (2) to (5) are dual port RAM1 (8) to (9) are magnetic disk interface circuits, (10) to (13) are magnetic disk devices, and (14) is an address. decoder, (15) is a control circuit,
(16) is memory, (17) is system data bus, (
18) is a system address bus. Agent Patent Attorney Souji Sasaki Figure 8 Syspmu Atresno

Claims (1)

[Scope of Claims] A plurality of magnetic disk control circuits provided corresponding to a plurality of magnetic disk devices, and a plurality of magnetic disk control circuits each provided between a system bus and a plurality of magnetic disk control circuits, each of which receives data from the system bus and magnetic disks. A magnetic device characterized by having a plurality of storage means for saving data from a disk device, and a plurality of memory control circuits for interleaving and transferring data exchanged between a system bus and the plurality of storage means. Disk controller.