AR002791A1 - Dispositivo de circuito integrado con a lo menos dos elementos constructivos aislados entre si y procedimiento para su elaboracion. - Google Patents
Dispositivo de circuito integrado con a lo menos dos elementos constructivos aislados entre si y procedimiento para su elaboracion.Info
- Publication number
- AR002791A1 AR002791A1 ARP960103508A AR10350896A AR002791A1 AR 002791 A1 AR002791 A1 AR 002791A1 AR P960103508 A ARP960103508 A AR P960103508A AR 10350896 A AR10350896 A AR 10350896A AR 002791 A1 AR002791 A1 AR 002791A1
- Authority
- AR
- Argentina
- Prior art keywords
- integrated circuit
- circuit device
- elaboration
- yes
- procedure
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Un dispositivo de circuito integrado con al menos dos elementos constructivos comprende, en un substrato, una estructura aislante (4,5) entrelos elementos constructivos que cubre al menos un flanco de un surco (3) y es más ancha en elp iso del surco que en el cuello del mismo. Los elementosconstructivos están dispuestos en distintos planos, en la superficie del substrato y en el piso de los surcos. La estructura aislante causa unaaislación perpendicular entre loselementos c onstructivos.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19525072A DE19525072C2 (de) | 1995-07-10 | 1995-07-10 | Integrierte Schaltungsanordnung, bei der ein erstes Bauelement an einer Hauptfläche eines Halbleitersubstrats und ein zweites Bauelement am Grabenboden angeordnet sind, und Verfahren zu deren Herstellung |
Publications (1)
Publication Number | Publication Date |
---|---|
AR002791A1 true AR002791A1 (es) | 1998-04-29 |
Family
ID=7766444
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ARP960103508A AR002791A1 (es) | 1995-07-10 | 1996-07-10 | Dispositivo de circuito integrado con a lo menos dos elementos constructivos aislados entre si y procedimiento para su elaboracion. |
Country Status (9)
Country | Link |
---|---|
US (1) | US5990536A (es) |
EP (1) | EP0838089B1 (es) |
JP (1) | JPH11509043A (es) |
KR (1) | KR100418849B1 (es) |
CN (1) | CN1093983C (es) |
AR (1) | AR002791A1 (es) |
DE (2) | DE19525072C2 (es) |
IN (1) | IN189112B (es) |
WO (1) | WO1997003463A1 (es) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6218720B1 (en) * | 1998-10-21 | 2001-04-17 | Advanced Micro Devices, Inc. | Semiconductor topography employing a nitrogenated shallow trench isolation structure |
US7071043B2 (en) | 2002-08-15 | 2006-07-04 | Micron Technology, Inc. | Methods of forming a field effect transistor having source/drain material over insulative material |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58134445A (ja) * | 1982-02-05 | 1983-08-10 | Seiko Epson Corp | 半導体装置の製造方法 |
JPS58169934A (ja) * | 1982-03-30 | 1983-10-06 | Fujitsu Ltd | 半導体集積回路装置 |
JPS61135151A (ja) * | 1984-12-05 | 1986-06-23 | Mitsubishi Electric Corp | 半導体記憶装置 |
US5176789A (en) * | 1985-09-21 | 1993-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Method for depositing material on depressions |
JPS6378573A (ja) * | 1986-09-22 | 1988-04-08 | Hitachi Ltd | 半導体装置 |
US4835584A (en) * | 1986-11-27 | 1989-05-30 | American Telephone And Telegraph Company, At&T Bell Laboratories | Trench transistor |
DE3809218C2 (de) * | 1987-03-20 | 1994-09-01 | Mitsubishi Electric Corp | Halbleitereinrichtung mit einem Graben und Verfahren zum Herstellen einer solchen Halbleitereinrichtung |
JPH0620108B2 (ja) * | 1987-03-23 | 1994-03-16 | 三菱電機株式会社 | 半導体装置の製造方法 |
US4977436A (en) * | 1988-07-25 | 1990-12-11 | Motorola, Inc. | High density DRAM |
JPH04151850A (ja) * | 1990-10-15 | 1992-05-25 | Nec Corp | 溝絶縁分離型半導体集積回路の製造方法 |
FR2672731A1 (fr) * | 1991-02-07 | 1992-08-14 | France Telecom | Procede d'oxydation localisee enterree d'un substrat de silicium et circuit integre correspondant. |
US5122848A (en) * | 1991-04-08 | 1992-06-16 | Micron Technology, Inc. | Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance |
EP0540262A2 (en) * | 1991-10-31 | 1993-05-05 | STMicroelectronics, Inc. | Trench isolation region |
JPH0637275A (ja) * | 1992-07-13 | 1994-02-10 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
US5512517A (en) * | 1995-04-25 | 1996-04-30 | International Business Machines Corporation | Self-aligned gate sidewall spacer in a corrugated FET and method of making same |
-
1995
- 1995-07-10 DE DE19525072A patent/DE19525072C2/de not_active Expired - Fee Related
-
1996
- 1996-05-30 IN IN985CA1996 patent/IN189112B/en unknown
- 1996-06-24 DE DE59607729T patent/DE59607729D1/de not_active Expired - Lifetime
- 1996-06-24 JP JP9505399A patent/JPH11509043A/ja not_active Ceased
- 1996-06-24 CN CN96195393A patent/CN1093983C/zh not_active Expired - Fee Related
- 1996-06-24 WO PCT/DE1996/001109 patent/WO1997003463A1/de active IP Right Grant
- 1996-06-24 KR KR1019970708234A patent/KR100418849B1/ko not_active IP Right Cessation
- 1996-06-24 EP EP96918603A patent/EP0838089B1/de not_active Expired - Lifetime
- 1996-06-24 US US08/981,674 patent/US5990536A/en not_active Expired - Lifetime
- 1996-07-10 AR ARP960103508A patent/AR002791A1/es unknown
Also Published As
Publication number | Publication date |
---|---|
US5990536A (en) | 1999-11-23 |
KR100418849B1 (ko) | 2004-04-21 |
EP0838089A1 (de) | 1998-04-29 |
CN1093983C (zh) | 2002-11-06 |
IN189112B (es) | 2002-12-21 |
DE59607729D1 (de) | 2001-10-25 |
CN1190490A (zh) | 1998-08-12 |
DE19525072A1 (de) | 1997-01-16 |
EP0838089B1 (de) | 2001-09-19 |
JPH11509043A (ja) | 1999-08-03 |
WO1997003463A1 (de) | 1997-01-30 |
KR19990014889A (ko) | 1999-02-25 |
DE19525072C2 (de) | 2002-06-27 |
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AR002791A1 (es) | Dispositivo de circuito integrado con a lo menos dos elementos constructivos aislados entre si y procedimiento para su elaboracion. |