DE69714134D1 - Rissunterbrecher auf Chips mit integrierter Schaltung - Google Patents
Rissunterbrecher auf Chips mit integrierter SchaltungInfo
- Publication number
- DE69714134D1 DE69714134D1 DE69714134T DE69714134T DE69714134D1 DE 69714134 D1 DE69714134 D1 DE 69714134D1 DE 69714134 T DE69714134 T DE 69714134T DE 69714134 T DE69714134 T DE 69714134T DE 69714134 D1 DE69714134 D1 DE 69714134D1
- Authority
- DE
- Germany
- Prior art keywords
- breaker
- crack
- integrated circuit
- circuit chips
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01055—Cesium [Cs]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Dicing (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/642,983 US5776826A (en) | 1996-05-06 | 1996-05-06 | Crack stop formation for high-productivity processes |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69714134D1 true DE69714134D1 (de) | 2002-08-29 |
DE69714134T2 DE69714134T2 (de) | 2003-02-13 |
Family
ID=24578864
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69714134T Expired - Lifetime DE69714134T2 (de) | 1996-05-06 | 1997-05-02 | Rissunterbrecher auf Chips mit integrierter Schaltung |
Country Status (4)
Country | Link |
---|---|
US (1) | US5776826A (de) |
EP (1) | EP0806795B1 (de) |
JP (1) | JP3204158B2 (de) |
DE (1) | DE69714134T2 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5834829A (en) * | 1996-09-05 | 1998-11-10 | International Business Machines Corporation | Energy relieving crack stop |
US5789302A (en) * | 1997-03-24 | 1998-08-04 | Siemens Aktiengesellschaft | Crack stops |
US6486526B1 (en) * | 1999-01-04 | 2002-11-26 | International Business Machines Corporation | Crack stop between neighboring fuses for protection from fuse blow damage |
DE19961790C1 (de) | 1999-12-21 | 2001-05-10 | Infineon Technologies Ag | Anordnung zur Abtrennung eines Halbleiterbausteines aus einem Halbleiterwafer |
US6295721B1 (en) | 1999-12-28 | 2001-10-02 | Taiwan Semiconductor Manufacturing Company | Metal fuse in copper dual damascene |
KR100359158B1 (ko) * | 1999-12-30 | 2002-10-31 | 주식회사 하이닉스반도체 | 반도체소자의 퓨즈 형성방법 |
US6495918B1 (en) * | 2000-09-05 | 2002-12-17 | Infineon Technologies Ag | Chip crack stop design for semiconductor chips |
US20050230005A1 (en) * | 2003-06-25 | 2005-10-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Test pad for reducing die sawing damage |
US20040262762A1 (en) * | 2003-06-25 | 2004-12-30 | Ming-Shuoh Liang | Method of providing via in a multilayer semiconductor device |
US20050026397A1 (en) * | 2003-07-28 | 2005-02-03 | International Business Machines Corporation | Crack stop for low k dielectrics |
US7276440B2 (en) * | 2003-12-12 | 2007-10-02 | Chartered Semiconductor Manufacturing Ltd. | Method of fabrication of a die oxide ring |
US8137791B2 (en) * | 2007-12-12 | 2012-03-20 | International Business Machines Corporation | Fuse and pad stress relief |
US9331019B2 (en) * | 2012-11-29 | 2016-05-03 | Infineon Technologies Ag | Device comprising a ductile layer and method of making the same |
US9305887B2 (en) | 2013-06-05 | 2016-04-05 | United Microelectronics Corp. | Seal ring structure with a v-shaped dielectric layer conformally overlapping a conductive layer |
JP6406138B2 (ja) | 2014-07-18 | 2018-10-17 | 株式会社デンソー | 半導体装置およびその製造方法 |
KR102334377B1 (ko) | 2015-02-17 | 2021-12-02 | 삼성전자 주식회사 | 실링 영역 및 디커플링 커패시터 영역을 포함하는 반도체 소자 |
TWI637462B (zh) * | 2017-11-15 | 2018-10-01 | 奕力科技股份有限公司 | 晶圓結構 |
CN113078109B (zh) * | 2021-03-26 | 2022-11-25 | 长鑫存储技术有限公司 | 半导体结构的制作方法及半导体结构 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2575795B2 (ja) * | 1988-04-28 | 1997-01-29 | 富士通株式会社 | 半導体装置の製造方法 |
US5096855A (en) * | 1988-05-23 | 1992-03-17 | U.S. Philips Corporation | Method of dicing semiconductor wafers which produces shards less than 10 microns in size |
US5414297A (en) * | 1989-04-13 | 1995-05-09 | Seiko Epson Corporation | Semiconductor device chip with interlayer insulating film covering the scribe lines |
US5206181A (en) * | 1991-06-03 | 1993-04-27 | Motorola, Inc. | Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing |
JP2776457B2 (ja) * | 1992-12-29 | 1998-07-16 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 半導体デバイスのクラックストップ形成方法及び半導体デバイス |
US5420455A (en) * | 1994-03-31 | 1995-05-30 | International Business Machines Corp. | Array fuse damage protection devices and fabrication method |
-
1996
- 1996-05-06 US US08/642,983 patent/US5776826A/en not_active Expired - Lifetime
-
1997
- 1997-04-24 JP JP10701497A patent/JP3204158B2/ja not_active Expired - Fee Related
- 1997-05-02 EP EP97303018A patent/EP0806795B1/de not_active Expired - Lifetime
- 1997-05-02 DE DE69714134T patent/DE69714134T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0806795A3 (de) | 1997-11-26 |
JPH1041255A (ja) | 1998-02-13 |
JP3204158B2 (ja) | 2001-09-04 |
DE69714134T2 (de) | 2003-02-13 |
EP0806795B1 (de) | 2002-07-24 |
US5776826A (en) | 1998-07-07 |
EP0806795A2 (de) | 1997-11-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: QIMONDA AG, 81739 MUENCHEN, DE Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US |