CN106940428A - Chip verification method, apparatus and system - Google Patents
Chip verification method, apparatus and system Download PDFInfo
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- CN106940428A CN106940428A CN201610004019.2A CN201610004019A CN106940428A CN 106940428 A CN106940428 A CN 106940428A CN 201610004019 A CN201610004019 A CN 201610004019A CN 106940428 A CN106940428 A CN 106940428A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
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Abstract
The invention provides a kind of chip verification method, apparatus and system.Wherein, this method includes：Verification platform is generated, wherein, verification platform includes：Model layer and interface layer, model layer include discharge model and register model, and interface layer includes data bus interface agency and cpu bus interface agency；By verification platform, chip to be measured is verified.By the present invention, solving UVM checking framework shortage level causes the problem of durability of platform is low, improves the durability of checking framework, improves verification efficiency.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of chip verification method, apparatus and system.
Background technology
Logic checking is a committed step during digit chip Front-end Design, verification platform analog chip actual motion
Environment, and pass through the correctness of test case checking chip function.As digital integrated electronic circuit is in scale and complexity
Rapid growth, and a large amount of similar chip of function release quickly demand, to verification platform and method of testing the time and into
Higher requirement is proposed in sheet.
Traditional verification platform is the checking of signal level, and by directly writing test and excitation, chip to be measured is verified.
Traditional verification platform, lacks the abstract division of labor to platform feature, ununified standard of compiling and application interface are caused
Verification platform durability is poor, and testing efficiency is low.
At present, using verification methodology it is one of trend of chip checking, unified verification methodology (Universal
Verification Methodology, referred to as UVM) it is Typical Representative therein.UVM system architecture diagrams such as Fig. 1
It is shown.Topmost Multiplexing Unit is bus agent (Agent) in UVM frameworks, verifies personnel by writing serial device
(sequencer) sequence (Sequence) in generates the bag (transaction) of transaction-level, and passes through driver (Driver)
Be converted to interface pumping signal and act on EBI, while monitor (Monitor) collects bus signals, convert back
The bag of transaction-level, and send to scoring board (scoreboard) progress automation comparison.
UVM provides a set of basic checking framework, realizes basic multiplexing and automatic Verification.But for current
Mass data is forwarded in the place for also having deficiency on the fast verification demand of type chip, UVM frameworks, first UVM
Agent definition is more wide in range, lacks the concept of level, the development of current high-speed bus so that bus structures are inherently
More complicated, itself just has many levels, and simultaneously for the modeling of flow bus, there is also many levels.More and more
Interface type can produce numerous combinations with complicated discharge model, be realized if these functions are all placed in Agent,
Need multi-level serial device to coordinate to realize, Agent can become extremely complex, also be unfavorable for the multiplexing of platform, while also can
Influence the operating efficiency of simulation tool software.Register checking there is also it is same the problem of.Secondly, for verification platform,
Writing and testing for test case, is also not enough only using only UVM frameworks.
Checking framework shortage level for UVM causes the problem of durability of platform is low, not yet proposes at present effective
Solution.
The content of the invention
The invention provides a kind of chip verification method, apparatus and system, lacked with the checking framework at least solving UVM
Level causes the problem of durability of platform is low.
According to an aspect of the invention, there is provided a kind of chip verification method, including：Verification platform is generated, wherein,
The verification platform includes：Model layer and interface layer, the model layer include discharge model and register model, described to connect
Mouth layer includes data bus interface agency and cpu bus interface agency；By the verification platform, to the core to be measured
Piece is verified.
Alternatively, generating the verification platform includes：Receiving platform configuration file, the platform configuration file is carried
State the platform structure parameter of the model parameter, the interface parameters of the interface layer and the verification platform of model layer；From platform
Component corresponding with the platform structure parameter is chosen in Component Gallery, the basic framework of the verification platform is generated；According to institute
Model parameter is stated, the discharge model and the register model is generated；According to the interface parameters, the data are generated
EBI is acted on behalf of and cpu bus interface agency.
Alternatively, carrying out checking to the chip to be measured includes：The test configurations for verifying chip to be measured are received, wherein,
Platform configuration, interface testing configuration, flow rate test configuration and register testing configuration are carried in the test configurations；From
Chosen in protos test suite PROTOS and configure phase with interface testing configuration, flow rate test configuration and the register testing respectively
The test case answered；According to the platform configuration, the test case is adjusted；Test case after combustion adjustment,
Generation checking report.
Alternatively, carrying out checking to the chip to be measured includes：By the discharge model, needed for generating chip to be measured
The transaction-level message of forwarding surface flow；By the register model, the chain of command deposit needed for the chip to be measured is generated
The transaction-level message of device；Acted on behalf of by the data bus interface, the transaction-level message received from the discharge model is turned
The bus signals level excitation for being sent to the chip to be measured is changed to, the bus signals level received from the chip to be measured is encouraged
Be converted to the transaction-level message for being sent to reference model or scoring board；Acted on behalf of by the cpu bus interface, will be from institute
The transaction-level message for stating register model reception is converted to the bus signals level excitation for being sent to the chip to be measured, will be from institute
The bus signals level excitation for stating chip reception to be measured is converted to the transaction-level message for being sent to reference model or scoring board.
According to another aspect of the present invention, a kind of chip checking device is additionally provided, including：Generation module, for giving birth to
Into verification platform, wherein, the verification platform includes：Model layer and interface layer, the model layer include discharge model and
Register model, the interface layer includes data bus interface agency and cpu bus interface agency；Authentication module, is used
In by the verification platform, the chip to be measured is verified.
Alternatively, the generation module includes：First receiving unit, for receiving platform configuration file, the platform is matched somebody with somebody
Put the platform knot that file carries the model parameter, the interface parameters of the interface layer and the verification platform of the model layer
Structure parameter；First chooses unit, raw for choosing component corresponding with the platform structure parameter from platform assembly storehouse
Into the basic framework of the verification platform；First generation unit, for according to the model parameter, generating the flow mould
Type and the register model；Second generation unit, for according to the interface parameters, generating the data bus interface
Agency and cpu bus interface agency.
Alternatively, the authentication module includes：Second receiving unit, the test for being used to verify chip to be measured for receiving is matched somebody with somebody
Put, wherein, platform configuration, interface testing configuration, flow rate test configuration and register are carried in the test configurations and is surveyed
Trial is put；Second chooses unit, is surveyed respectively with interface testing configuration, the flow for being chosen from protos test suite PROTOS
Trial is put configures corresponding test case with the register testing；Adjustment unit, it is right for according to the platform configuration
The test case is adjusted；Authentication unit, for the test case after combustion adjustment, generation checking report.
Alternatively, the authentication module includes：3rd generation unit, for by the discharge model, generating core to be measured
The transaction-level message of forwarding surface flow needed for piece；4th generation unit, for by the register model, generating institute
State the transaction-level message of the chain of command register needed for chip to be measured；First interface unit, for passing through the data/address bus
Interface proxy, the transaction-level message received from the discharge model is converted to the bus signals for being sent to the chip to be measured
Level excitation, the bus signals level excitation received from the chip to be measured is converted to the thing for being sent to reference model or scoring board
Business level message；Second interface unit, for being acted on behalf of by the cpu bus interface, will connect from the register model
The transaction-level message of receipts is converted to the bus signals level excitation for being sent to the chip to be measured, will be received from the chip to be measured
Bus signals level excitation be converted to the transaction-level message that is sent to reference model or scoring board.
According to an aspect of the invention, there is provided a kind of chip checking system, including：Above-mentioned chip checking device,
Platform assembly storehouse, protos test suite PROTOS storehouse, script bank, wherein, the platform assembly storehouse builds verification platform base for providing
The component of this framework；The protos test suite PROTOS storehouse, for providing test case；The script bank, for providing the chip
Verify the script that the automatic operating of device needs.
By the present invention, using generation verification platform, wherein, verification platform includes：Model layer and interface layer, model layer
Including discharge model and register model, interface layer includes data bus interface agency and cpu bus interface agency；It is logical
Verification platform is crossed, the mode verified to chip to be measured, solving UVM checking framework shortage level causes to put down
The problem of durability of platform is low, improves the durability of checking framework, improves verification efficiency.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, the present invention
Schematic description and description be used for explain the present invention, do not constitute inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is the framework schematic diagram according to the chip checking system of correlation technique；
Fig. 2 is the flow chart of chip verification method according to embodiments of the present invention；
Fig. 3 is the structured flowchart of chip checking device according to embodiments of the present invention；
Fig. 4 is the alternative construction block diagram one of chip checking device according to embodiments of the present invention；
Fig. 5 is the alternative construction block diagram two of chip checking device according to embodiments of the present invention；
Fig. 6 is the alternative construction block diagram three of chip checking device according to embodiments of the present invention；
Fig. 7 is the structured flowchart of chip checking system according to embodiments of the present invention；
Fig. 8 is the framework schematic diagram according to the chip checking system of alternative embodiment of the present invention；
Fig. 9 is the structural representation of the test case according to alternative embodiment of the present invention；
Figure 10 is the flow chart of the chip verification method according to alternative embodiment of the present invention；
Figure 11 is the structural representation of the chip checking system according to alternative embodiment of the present invention.
Embodiment
Describe the present invention in detail below with reference to accompanying drawing and in conjunction with the embodiments.It should be noted that in the feelings not conflicted
Under condition, the feature in embodiment and embodiment in the application can be mutually combined.
It should be noted that term " first ", " second " in description and claims of this specification and above-mentioned accompanying drawing
Etc. being for distinguishing similar object, without for describing specific order or precedence.
A kind of chip verification method is provided in the present embodiment, and Fig. 2 is chip verification method according to embodiments of the present invention
Flow chart, as shown in Fig. 2 the flow comprises the following steps：
Step S202, generates verification platform, wherein, verification platform includes：Model layer and interface layer, model layer include
Discharge model and register model, interface layer include data bus interface agency and cpu bus interface agency；
Step S204, by verification platform, is verified to chip to be measured.
By above-mentioned steps, the verification platform of stratification is generated, and chip to be measured is entered using the verification platform of stratification
That checking of row, solving UVM checking framework shortage level causes the problem of durability of platform is low, improves and tests
The durability of framework is demonstrate,proved, verification efficiency is improved.
Alternatively, generation verification platform includes：Receiving platform configuration file, platform configuration file carries the mould of model layer
The platform structure parameter of shape parameter, the interface parameters of interface layer and verification platform；Chosen and platform knot from platform assembly storehouse
The corresponding component of structure parameter, generates the basic framework of verification platform；According to model parameter, generation discharge model and register
Model；According to interface parameters, generation data bus interface agency and cpu bus interface agency.Through the above way,
The quick of verification platform can be realized with the preset component for being used to generate the basic framework of verification platform in platform assembly storehouse
Build.
Alternatively, when being verified to chip to be measured, it can write and verification platform is sent to after test configurations, verification platform
Receive the test configurations for verifying chip to be measured, wherein, carried in test configurations platform configuration, interface testing configuration,
Flow rate test is configured and register testing configuration；Verification platform is chosen from protos test suite PROTOS to be configured with interface testing, flows respectively
Measure test configurations and register testing configures corresponding test case；Verification platform enters according to platform configuration to test case
Row adjustment；Test case after verification platform combustion adjustment, generation checking report.
Alternatively, when being verified to chip to be measured, in verification platform, discharge model generates turn needed for chip to be measured
The transaction-level message of fermentation flow；The transaction-level message of chain of command register needed for register model generation chip to be measured；
Data bus interface agency is converted to the transaction-level message received from discharge model the bus signals for being sent to chip to be measured
Level excitation, the bus signals level excitation received from chip to be measured is converted to the transaction-level for being sent to reference model or scoring board
Message；Cpu bus interface agency, which is converted to the transaction-level message received from register model, is sent to the total of chip to be measured
The level excitation of line signal, the bus signals level received from chip to be measured is encouraged to be converted to is sent to reference model or scoring board
Transaction-level message.
Through the above description of the embodiments, those skilled in the art can be understood that according to above-described embodiment
Method the mode of required general hardware platform can be added to realize by software, naturally it is also possible to by hardware, but a lot
In the case of the former be more preferably embodiment.Understood based on such, technical scheme is substantially in other words to existing
The part for having technology to contribute can be embodied in the form of software product, and the computer software product is stored in one
In storage medium (such as ROM/RAM, magnetic disc, CD), including some instructions are make it that a station terminal equipment (can
To be mobile phone, computer, server, or network equipment etc.) perform method described in each embodiment of the invention.
A kind of chip checking device is additionally provided in the present embodiment, and the device is used to realize above-described embodiment and be preferable to carry out
Mode, had carried out repeating no more for explanation.As used below, term " module " can realize predetermined function
Software and/or hardware combination.Although the device described by following examples is preferably realized with software, firmly
Part, or the realization of the combination of software and hardware is also that may and be contemplated.
Fig. 3 is the structured flowchart of chip checking device according to embodiments of the present invention, as shown in figure 3, the device includes：
Generation module 32 and authentication module 34, wherein,
Generation module 32, for generating verification platform, wherein, verification platform includes：Model layer and interface layer, model layer
Including discharge model and register model, interface layer includes data bus interface agency and cpu bus interface agency；Test
Module 34 is demonstrate,proved, coupled to generation module 32, for by verification platform, being verified to chip to be measured.
Fig. 4 is the alternative construction block diagram one of chip checking device according to embodiments of the present invention, as shown in figure 4, alternatively,
Generation module 32 includes：First receiving unit 322, for receiving platform configuration file, platform configuration file carries mould
The model parameter of type layer, the platform structure parameter of the interface parameters of interface layer and verification platform；First chooses unit 324,
Coupled to the first receiving unit 322, for choosing component corresponding with platform structure parameter, generation from platform assembly storehouse
The basic framework of verification platform；First generation unit 326, coupled to the first receiving unit 322, for being joined according to model
Number, generation discharge model and register model；Second generation unit 328, coupled to the first receiving unit 322, is used for
According to interface parameters, generation data bus interface agency and cpu bus interface agency.
Fig. 5 is the alternative construction block diagram two of chip checking device according to embodiments of the present invention, as shown in figure 5, alternatively,
Authentication module 34 includes：Second receiving unit 340, for receiving the test configurations for being used for verifying chip to be measured, wherein,
Platform configuration, interface testing configuration, flow rate test configuration and register testing configuration are carried in test configurations；Second choosing
Take unit 341, coupled to the second receiving unit 340, for chosen from protos test suite PROTOS respectively with interface testing configuration,
Flow rate test is configured and register testing configures corresponding test case；Adjustment unit 342, unit is chosen coupled to second
341, for according to platform configuration, being adjusted to test case；Authentication unit 343, coupled to adjustment unit 342,
For the test case after combustion adjustment, generation checking report.
Fig. 6 is the alternative construction block diagram three of chip checking device according to embodiments of the present invention, as shown in fig. 6, alternatively,
Authentication module 34 includes：3rd generation unit 344, for by discharge model, generating the forwarding surface needed for chip to be measured
The transaction-level message of flow；4th generation unit 345, for by register model, generating the control needed for chip to be measured
The transaction-level message of face register processed；First interface unit 346, coupled to the 3rd generation unit 344, for passing through number
Acted on behalf of according to EBI, the transaction-level message received from discharge model is converted to the bus signals level for being sent to chip to be measured
Excitation, the bus signals level excitation received from chip to be measured is converted to the transaction-level report for being sent to reference model or scoring board
Text；Second interface unit 347,, will be from for being acted on behalf of by cpu bus interface coupled to the 4th generation unit 345
The transaction-level message that register model is received is converted to the bus signals level excitation for being sent to chip to be measured, will be from chip to be measured
The bus signals level excitation of reception is converted to the transaction-level message for being sent to reference model or scoring board.
It should be noted that above-mentioned modules can be by software or hardware to realize, for the latter, Ke Yitong
Cross in the following manner realization, but not limited to this：Above-mentioned module is respectively positioned in same processor；Or, above-mentioned module distinguishes position
In multiple processors.
Embodiments of the invention additionally provide a kind of chip checking system, and Fig. 7 is chip checking according to embodiments of the present invention
The structured flowchart of system, as shown in fig. 7, the system includes：Above-mentioned chip checking device 72, platform assembly storehouse 74,
Protos test suite PROTOS storehouse 76, script bank 78, wherein, platform assembly storehouse 74, coupled to chip checking device 72, for providing
Build the component of verification platform basic framework；Protos test suite PROTOS storehouse 76, coupled to chip checking device 72, for providing survey
Example on probation；Script bank 78, coupled to chip checking device 72, the automatic operating for providing chip checking device is needed
The script wanted.
Embodiments of the invention additionally provide a kind of software, and the software is used to perform in above-described embodiment and preferred embodiment
The technical scheme of description.
Embodiments of the invention additionally provide a kind of storage medium.In the present embodiment, above-mentioned storage medium can be set
To store the program code for being used for performing following steps：
Step S202, generates verification platform, wherein, verification platform includes：Model layer and interface layer, model layer include
Discharge model and register model, interface layer include data bus interface agency and cpu bus interface agency；
Step S204, by verification platform, is verified to chip to be measured.
Alternatively, in the present embodiment, above-mentioned storage medium can include but is not limited to：USB flash disk, read-only storage
(Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as
For RAM), mobile hard disk, magnetic disc or CD etc. are various can be with the medium of store program codes.
Alternatively, the specific example in the present embodiment may be referred to showing described in above-described embodiment and optional embodiment
Example, the present embodiment will not be repeated here.
In order that the description of the embodiment of the present invention is clearer, it is described and illustrates with reference to alternative embodiment.
In the RTL Front End Authentications of digit chip, there are many deficiencies in traditional verification method, use UVM authentications
The science of law, there is also deficiency in terms of stratification, durability and automation.Therefore the embodiment of the present invention is directed to one
The new verification platform framework of kind and method of testing, to solve these problems present in existing checking framework.
Alternative embodiment of the present invention provides a kind of chip checking framework, method of testing and system, before digit chip
Hold Method at Register Transfer Level (Register Transfer Level, referred to as RTL) logic checking.
For the verification platform structure providing a kind of stratification, durability is stronger and the test case structure of standardization, together
When script is combined on the basis of the checking framework, complete automatic Verification flow is built, so as to lift overall test
Efficiency is demonstrate,proved, the chip checking framework that alternative embodiment of the present invention is provided uses following scheme：
As shown in figure 8, verification platform is divided into two levels of model layer and interface layer：
Model layer includes discharge model, register model, wherein：
Discharge model is modeled to forwarding surface flow needed for whole chip to be measured, produces the things level message of data traffic,
The message is unrelated with specific data bus interface.
Register model is modeled to chain of command register needed for chip to be measured, produces the things level message of register, should
Message is unrelated with specific cpu bus interface.
Interface layer includes data bus interface agency and cpu bus interface agency：
Above-mentioned interface proxy realizes specific data bus protocol (including different data/address bus and cpu bus), will
Things level message is converted to bus signals level excitation, and controlling bus, and bus interface signals are converted back into things level message,
It is sent to reference model or scoring board.Interface proxy is only to specific type of bus protocol related, and with being carried in bus
Type of message is unrelated.
With reference to above-mentioned layered verification framework, the invention provides a kind of test case organization plan, as shown in figure 9, should
The structure of test case includes：
Interface is configured, the configuration for describing the interface testing use-case in platform corresponding to interface proxy；
Platform configuration, the active configuration parameter for describing each component in platform；
Message is configured, the active configuration for describing discharge model；
Register configuration, the read-write for describing register model is configured.
Alternative embodiment of the present invention additionally provides a kind of method of testing of chip front end RTL logics, as shown in Figure 10, bag
Include the following steps：
Step S1001：Write platform configuration file, including platform structure configuration, discharge model configuration, register model
Configuration, configuration file can use extensible markup language (eXtensible Markup Language, referred to as xml)
Form is stored；
Step S1002：Verification platform is generated, first, transfer environment builds script (envBuilder), and reading platform is matched somebody with somebody
The platform structure configuration in file is put, corresponding interface module and other components are chosen from the Component Gallery of software systems, it is raw
Into verification platform basic framework.
Secondly, the register model in allocating register model generation script (spec2reg), reading platform configuration file is matched somebody with somebody
Put, generate register model code；
Again；The discharge model for calling discharge model to generate in script (spec2packet), reading platform configuration file is matched somebody with somebody
Put, generate discharge model code；
Step S1003：Write the reference model and scoring board in verification platform；According to chip to be measured, in testing for having generated
Demonstrate,prove supplement reference model and scoring board block code in platform framework；
Step S1004：Use-case configuration file, including platform configuration are write, interface testing configuration, flow rate test is configured,
Register testing is configured
Step S1005：Test case is generated, calls use-case to generate script (testGen), selection is raw from protos test suite PROTOS
Into use-case：
First, configured according to interface testing, the corresponding interface test case is chosen from protos test suite PROTOS；
Secondly, according to flow rate test configuration, corresponding discharge test case is chosen from protos test suite PROTOS；
Again, configured according to register testing, corresponding registers test case is chosen from protos test suite PROTOS；
Finally, according to the difference of platform configuration, above-mentioned standard use-case is modified, can be normal in verification platform
Operation.
Step S1006：New test case is write, calls use-case to generate script (testGen), new use-case is write in selection,
New test case framework is generated, as shown in Figure 3.In the use-case framework, to platform configuration, interface configuration, message is matched somebody with somebody
Put, register configuration is write respectively.
Step S1007：Testing results use-case is verified, calls operation with returning script (run＆regression), choosing
The test case for selecting needs is run, while coverage rate relevant information is collected, generation checking report；
With reference to above-mentioned verification platform framework, test case structure, method of testing, the present invention is optional to additionally provide a set of test
Platform software system is demonstrate,proved, as shown in figure 11, including：Platform assembly storehouse, protos test suite PROTOS storehouse, and script bank.
Platform assembly storehouse, including：
Infrastructure component, for depositing the basic module that verification platform is built, such as configuration module, scoring board etc.；
Data interface assembly, required data/address bus proxy module is built for depositing verification platform；
Cpu i/f component, required cpu bus proxy module is built for depositing verification platform；
Message component, required module is built for depositing discharge model in verification platform；
Register component, required module is built for depositing register model in verification platform；
Reference model component, required module is built with reference model in storage verification platform；
Macroelement, builds for depositing verification platform and the macrodoces of middle needs is write with test case；
Virtual interface component, the virtual interface of middle needs is built for depositing verification platform.
Protos test suite PROTOS storehouse, including：
Message use-case, for depositing typical message flow model and model configuration information；
Register use-case, for depositing typical register model and model configuration information；
Interface protocol use-case, for depositing the use-case tested in itself for interface protocol.
Script bank, including：
Environmental structure script (envBuilder), according to platform configuration file, generates basic framework and the checking of verification platform
The software environment of platform operation；
Register model generation script (spec2reg), according to register configuration file, generates register model；
Discharge model generation script (spec2packet), according to traffic profile, generates discharge model；
Use-case generation script (testGen), according to use-case configuration file, extracts use-case, generation is tested from protos test suite PROTOS storehouse
Test case needed for card；
Operation is with returning script (run＆regression), the control run for test case, while collecting coverage rate phase
Close information, generation checking report.
In summary, the such scheme provided by alternative embodiment of the present invention, is divided into model layer by verification platform and connects
Mouth layer, it is high-level flowmeter factor and register modeling is independent with bottom physical interface so that verification platform is multiplexed
Property is greatly improved.Simultaneously based on the architecture provides a kind of method of testing and software systems, specification testing process and checking
The function definition of module, saves the overlapping development time of verification platform, and realizes the automation of chip checking flow,
Greatly improve the efficiency of chip checking.
Obviously, those skilled in the art should be understood that above-mentioned each module of the invention or each step can be with general
Computing device realizes that they can be concentrated on single computing device, or is distributed in multiple computing devices and is constituted
Network on, alternatively, the program code that they can be can perform with computing device be realized, it is thus possible to by they
Storage is performed by computing device in the storage device, and in some cases, can be to be held different from order herein
They, are either fabricated to each integrated circuit modules or will be many in them by the shown or described step of row respectively
Individual module or step are fabricated to single integrated circuit module to realize.So, the present invention is not restricted to any specific hardware
Combined with software.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the technology of this area
For personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made is any
Modification, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (9)
1. a kind of chip verification method, it is characterised in that including：
Verification platform is generated, wherein, the verification platform includes：Model layer and interface layer, the model layer include
Discharge model and register model, the interface layer include data bus interface agency and cpu bus interface agency；
By the verification platform, the chip to be measured is verified.
2. according to the method described in claim 1, it is characterised in that the generation verification platform includes：
Receiving platform configuration file, the platform configuration file carries the model parameter of the model layer, described connect
The interface parameters and the platform structure parameter of the verification platform of mouth layer；
Component corresponding with the platform structure parameter is chosen from platform assembly storehouse, the base of the verification platform is generated
This framework；
According to the model parameter, the discharge model and the register model are generated；
According to the interface parameters, the data bus interface agency and cpu bus interface agency are generated.
3. according to the method described in claim 1, it is characterised in that carrying out checking to the chip to be measured includes：
Receive the test configurations for verifying chip to be measured, wherein, carried in the test configurations platform configuration,
Interface testing configuration, flow rate test configuration and register testing configuration；
Choose and configured and the register with interface testing configuration, the flow rate test respectively from protos test suite PROTOS
The corresponding test case of test configurations；
According to the platform configuration, the test case is adjusted；
Test case after combustion adjustment, generation checking report.
4. according to the method described in claim 1, it is characterised in that carrying out checking to the chip to be measured includes：
Pass through the discharge model, the transaction-level message of the forwarding surface flow needed for generation chip to be measured；
Pass through the register model, the transaction-level message of the chain of command register needed for the generation chip to be measured；
Acted on behalf of by the data bus interface, the transaction-level message received from the discharge model is converted into transmission
To the bus signals level excitation of the chip to be measured, the bus signals level excitation received from the chip to be measured is changed
To be sent to the transaction-level message of reference model or scoring board；
Acted on behalf of by the cpu bus interface, the transaction-level message received from the register model is converted to
The bus signals level excitation of the chip to be measured is sent to, the bus signals level received from the chip to be measured is encouraged
Be converted to the transaction-level message for being sent to reference model or scoring board.
5. a kind of chip checking device, it is characterised in that including：
Generation module, for generating verification platform, wherein, the verification platform includes：Model layer and interface layer,
The model layer includes discharge model and register model, and the interface layer includes data bus interface and acted on behalf of and CPU
EBI is acted on behalf of；
Authentication module, for by the verification platform, being verified to the chip to be measured.
6. device according to claim 5, it is characterised in that the generation module includes：
First receiving unit, for receiving platform configuration file, the platform configuration file carries the model layer
Model parameter, the platform structure parameter of the interface parameters of the interface layer and the verification platform；
First chooses unit, raw for choosing component corresponding with the platform structure parameter from platform assembly storehouse
Into the basic framework of the verification platform；
First generation unit, for according to the model parameter, generating the discharge model and the register model；
Second generation unit, is acted on behalf of and described for according to the interface parameters, generating the data bus interface
Cpu bus interface is acted on behalf of.
7. device according to claim 5, it is characterised in that the authentication module includes：
Second receiving unit, for receiving the test configurations for being used for verifying chip to be measured, wherein, the test configurations
In carry platform configuration, interface testing configuration, flow rate test configuration and register testing configuration；
Second chooses unit, is surveyed respectively with interface testing configuration, the flow for being chosen from protos test suite PROTOS
Trial is put configures corresponding test case with the register testing；
Adjustment unit, for according to the platform configuration, being adjusted to the test case；
Authentication unit, for the test case after combustion adjustment, generation checking report.
8. device according to claim 5, it is characterised in that the authentication module includes：
3rd generation unit, for passing through the discharge model, the thing of the forwarding surface flow needed for generation chip to be measured
Business level message；
4th generation unit, for by the register model, the chain of command needed for generating the chip to be measured to be posted
The transaction-level message of storage；
First interface unit, for being acted on behalf of by the data bus interface, the thing that will be received from the discharge model
Business level message is converted to the bus signals level excitation for being sent to the chip to be measured, by what is received from the chip to be measured
Bus signals level excitation is converted to the transaction-level message for being sent to reference model or scoring board；
Second interface unit, for being acted on behalf of by the cpu bus interface, will be received from the register model
Transaction-level message be converted to be sent to the chip to be measured bus signals level excitation, will be connect from the chip to be measured
The bus signals level excitation of receipts is converted to the transaction-level message for being sent to reference model or scoring board.
9. a kind of chip checking system, it is characterised in that including：Chip as any one of claim 5 to 8 is tested
Card device, platform assembly storehouse, protos test suite PROTOS storehouse, script bank, wherein,
The platform assembly storehouse, the component of verification platform basic framework is built for providing；
The protos test suite PROTOS storehouse, for providing test case；
The script bank, for providing the script that the automatic operating of the chip checking device needs.
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| CN201610004019.2A CN106940428B (en) | 2016-01-04 | 2016-01-04 | Chip verification method, device and system |
| PCT/CN2016/081331 WO2016197768A1 (en) | 2016-01-04 | 2016-05-06 | Chip verification method, device, and system |
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|---|---|---|---|
| CN201610004019.2A CN106940428B (en) | 2016-01-04 | 2016-01-04 | Chip verification method, device and system |
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