CN109684672B - System-level verification system and method for SOC (System on chip) - Google Patents
System-level verification system and method for SOC (System on chip) Download PDFInfo
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Abstract
The invention discloses a system-level verification system and a method of an SOC chip, wherein the system comprises a simulation platform and the SOC chip; the chip comprises a CPU, a debugging interface, a module to be verified and an excitation sending interface; the simulation platform comprises: the control CPU model is connected with the module to be verified through a debugging interface according to an interface protocol; receiving an indication signal of starting verification and controlling a CPU to enter a debugging mode, receiving an indication signal of finishing verification and controlling the CPU to exit the debugging mode, wherein the CPU acts according to an instruction of controlling a CPU model in the debugging mode; the excitation sending model is connected with the module to be verified through the excitation sending interface according to an interface protocol, and is used for generating excitation data, sending the excitation data to the module to be verified and collecting or receiving response data of the module to be verified; and the result analysis model is used for analyzing and judging the response data of the verification module, outputting a verification result and outputting an indication signal of verification end according to the verification result. The scheme solves the problem of low verification efficiency caused by complex and complicated code maintenance, simplifies code maintenance and improves verification efficiency.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a System On Chip (SOC) Chip System level verification System and a method.
Background
With the development of the integrated circuit industry, the presented SOC chip is more and more complex, the requirement for verification is higher and higher overall, and the verification working time occupies about 80% of the whole cycle in the development cycle of chip design, so the research on how to improve the verification working efficiency under such a large background is significant.
At present, for SOC verification, a C-language-based driving program needs to be written, a driving instruction program is compiled through a proper compiler, and finally the driving instruction program is written into a memory in a simulation platform for a CPU to take out an instruction and execute, meanwhile, the verification simulation platform needs to start control excitation sending, the pre-compiled program cannot interact with the simulation platform, and the idea of randomness verification cannot be well applied to simulation.
Referring to fig. 1, in the conventional SOC verification method, a C code (C language driver) is compiled in advance in a C language environment to drive a CPU to perform behavior control, and a simulation is implemented in cooperation with an excitation generation and transmission component in a simulation environment; the behavior of a CPU in the SOC is controlled according to a pre-compiled C language driver, so that the configuration of related functions of the chip is realized, a simulation platform excitation sending component applies related excitation signals to the SOC design to realize SOC system verification, and development, compilation and simulation environments of the driver are two completely separated systems. When simulation is carried out, a verifier cannot flexibly schedule a CPU, the behavior of the CPU is completely controlled by a precompiled driver, friendly interaction cannot be formed with a simulation environment, the verifier needs to modify the driver of a C code and the component of Systemverilog language of the simulation environment in a modification verification scene, and the work load is undoubtedly increased for the verifier with more and more complex verification tasks by maintaining two sets of verification codes, so that the work efficiency is not high.
Disclosure of Invention
The invention provides a system-level verification method and system of an SOC chip, which are used for overcoming the defects of low verification efficiency and the like caused by insufficient flexibility of CPU control in the simulation test process in the prior art, improving the flexibility of CPU control in the simulation test process, simplifying code maintenance and improving the verification efficiency.
In order to achieve the above object, the present invention provides a system-on-a-chip (SOC) verification system, which includes a simulation platform and an SOC chip;
the SOC chip comprises a CPU, a debugging interface connected with the CPU, a module to be verified and an excitation sending interface connected with the module to be verified;
the simulation platform comprises:
the control CPU model is connected with the module to be verified through the debugging interface according to an interface protocol; receiving an indication signal of starting verification when the verification is started and controlling a CPU to enter a debugging mode, receiving an indication signal of finishing the verification when the verification is finished and controlling the CPU to exit the debugging mode, wherein the CPU acts according to an instruction of controlling a CPU model in the debugging mode;
the excitation sending model is connected with the module to be verified through the excitation sending interface according to an interface protocol, and is used for generating excitation data, sending the excitation data to the module to be verified, and collecting or receiving response data of the module to be verified;
and the result analysis model is used for analyzing and judging the response data of the verification module, outputting a verification result and outputting an indication signal of verification end according to the verification result.
In order to achieve the above object, the present invention further provides an SOC chip system level verification simulation platform, which includes the simulation platform in the SOC chip system level verification system.
In order to achieve the above object, the present invention further provides a system-level verification method for an SOC chip, wherein the SOC chip includes a CPU, a debug interface connected to the CPU, a module to be verified, and an excitation sending interface connected to the module to be verified; the method comprises the following steps:
compiling and compiling a software program in a simulation platform;
the simulation platform generates an indication signal for starting verification, outputs the indication signal through the debugging interface and controls the CPU of the SOC chip to enter a debugging mode;
controlling a CPU to configure related functions of a module to be verified according to a working mode required by a verification scene;
generating and transmitting random stimulus data to a stimulus transmission interface according to the configuration of the function;
receiving or collecting response data of a module to be verified and judging whether the response data is overtime or not;
finishing verification and reporting errors when the response data is overtime, and checking whether the response data is correct when the response data is not overtime;
finishing verification and reporting errors when the response data are wrong, and judging whether other excitation data exist or not when the response data are correct;
and ending the verification when no other excitation data exists, and returning to the step of controlling the CPU to configure the related functions of the module to be verified according to the working mode required by the verification scene when other excitation data exists.
The SOC chip system level verification system and the method provided by the invention have the advantages that an SOC chip CPU driver platform is integrated in a simulation platform and unified in the same compiling language environment, a unified verification platform is adopted, the verification environment is completely used for controlling CPU behaviors and driving excitation, the work of maintaining codes is simplified, meanwhile, a random verification method can be fully utilized to participate in the driving control of a CPU, the interaction with the simulation platform can be well carried out, the verification is more flexible and efficient, the maintenance and the expansion are convenient, so that a verifier can concentrate on the development of scenes and the coverage of functions, the rapid convergence of the verification work is accelerated, and the overall working efficiency of the verifier can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating a simulation of an SOC chip implemented in the prior art;
fig. 2 is a schematic diagram of a frame of an SOC chip system-level verification system according to an embodiment of the present invention;
FIG. 3 is a block diagram of a system-on-chip system-in-a-chip verification system according to a second embodiment of the present invention
Fig. 4 is a flowchart illustrating an SOC chip system-level verification method according to an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
It should be noted that all directional indicators (such as up, down, left, right, front, back \8230;) in the embodiments of the present invention are only used to explain the relative positional relationship between the components, the motion situation, etc. in a specific posture (as shown in the attached drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly, and for example, "secured" may be a fixed connection, a removable connection, or an integral part; the connection can be mechanical connection, electrical connection, physical connection or wireless communication connection; they may be directly connected or indirectly connected through intervening media, or they may be interconnected within two elements or in a relationship where two elements interact with each other unless otherwise specifically limited. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In addition, the technical solutions in the embodiments of the present invention may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination of technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a system-level verification system of an SOC chip.
Example one
Referring to fig. 2, the present invention provides a system-on-chip verification system of SOC, which includes an SOC chip 1 and a simulation platform 2;
the SOC chip 1 comprises a CPU11, a debugging interface 14 connected with the CPU11, a module 12 to be verified, and an excitation sending interface 15 connected with the other design logics 13 and the module 12 to be verified;
the simulation platform 2 comprises a control CPU model 21, an excitation sending model 22 and a result analysis model 23; wherein:
the control CPU model 21 is connected with the module to be verified 12 through the debugging interface 14 according to an interface protocol; receiving an indication signal of starting verification when the verification is started and controlling the CPU11 to enter a debugging mode, receiving an indication signal of finishing the verification when the verification is finished and controlling the CPU11 to exit the debugging mode, wherein the CPU11 acts according to an instruction of controlling the CPU model 21 in the debugging mode;
preferably, the control CPU model is built based on a UVM verification methodology; and controlling the CPU to configure the related functions of the module to be verified according to the working mode required by the verification scene, and scheduling the peripheral equipment (other design logic 13).
The excitation sending model 22 is connected with the module to be verified 12 through the excitation sending interface 15 according to an interface protocol, and is used for generating excitation data, sending the excitation data to the module to be verified 12, and collecting or receiving response data of the module to be verified 12;
preferably, the excitation sending model is built based on a UVM verification methodology, generates excitation data according to a working mode, and sends the excitation data to the excitation sending interface 15.
And the result analysis model 23 is used for analyzing and judging the response data of the verification module 12, outputting a verification result and outputting an indication signal of verification end according to the verification result.
Based on UVM verification methodology establishment, the automatic function (automatic comparison and automatic simulation ending) of the verification environment is mainly realized. And the result analysis model outputs an indication signal of verification end when at least one of response data feedback time of the module to be verified is overtime or no response, response data is wrong and excitation data is sent completely.
The action of each internal component of the module 12 to be verified is controlled by the CPU, the whole module to be verified can be flexibly controlled in a simulation environment and is matched with excitation to achieve the aim of verifying certain functions, an effective method is explored to improve verification efficiency in a chip development period, a debug interface of a CPU can be used for more flexibly and effectively controlling the CPU in the simulation environment, the excitation of the simulation environment is combined, the specific randomness principle of a systemverilog language is fully utilized, the whole work efficiency of verification can be improved, the maintenance of codes can be simplified, and further the verification efficiency is improved.
Preferably, the simulation platform 1 is connected to the excitation sending interface 15 and the debugging interface 14 on the SOC chip 1 through a plurality of interfaces (interfaces defined in the system design language, connecting the simulation platform and the design to be tested), executable model codes for controlling the CPU model 21 and the excitation sending model 22 are written by using the UVM methodology, and the excitation sending interface 15 includes but is not limited to I2C, SPI, UART and other interfaces; debug interface 14 includes, but is not limited to, a jtag, serial wire, etc. interface. The debugging interface 14 and the excitation sending interface 15 are bridges for connecting the simulation platform 2 and the SOC chip 1 to be tested, and the implementation mode is that an interface method in the systemverilog is adopted.
Preferably, a circulation mechanism is arranged inside the control CPU model 21 and the excitation sending model 22, and any function in the module to be verified 12 is repeatedly verified by generating multiple times of random excitation data in the excitation sending model 22 according to the configuration in the control CPU model 21 in the verification process.
Aiming at the problems that the development of the SOC chip is more and more complex, the verification complexity is further improved, effective methods and schemes are explored to improve the verification efficiency, more flexible simulation environment development and more efficient verification scene coverage can be provided for verification personnel, and the method is a modern integrated circuit testing technology combining CPU control, simulation platform control and verification methods.
The invention is a novel verification method mainly composed of a design to be tested (DUT, namely a module to be verified 12), a debugging interface 14 and a verification environment generated by conventional excitation, and combines a simulation EDA tool to freely control various behaviors of a CPU11 at each simulated node, manages the behavior of the design to be tested by using a very convenient control CPU under a specific functional scene, and inputs the behavior into the design to be tested by combining an excitation sequence of the verification environment, thereby fully verifying whether the design to be tested accords with the requirement of the design specification under the specific scene. Meanwhile, as the control of the CPU is realized in a verification environment, the chip verification can be more robust by combining the characteristic of randomness verification, and the interactivity of CPU control and excitation transmission can be realized.
Example two
Referring to fig. 3, to implement the application of the present invention to the I2C interface:
the verification environment mainly comprises:
1. the excitation generating and sending component (excitation sending model 22) is mainly connected to the corresponding pin of the SOC design to be tested (SOC chip 1) through I2C _ interface according to the I2C interface protocol, and can sample the response or return data of the design to be tested through the component.
2. The control CPU component (control CPU model 21) is mainly connected to the corresponding supervisor of the SOC design to be tested through jtag _ interface according to the jtag interface protocol, the CPU enters a debugging mode by accessing the register of the CPU, the CPU enters a halt state in the debugging mode, and the behavior of the CPU is completely taken over by the jtag.
3. The other components (result analysis model 23) mainly perform automatic comparison and judgment on the simulation in the verification environment, and can control the end of the whole simulation.
The SOC design to be tested mainly comprises: CPU, I2C controller, other logic; the CPU is mainly used for scheduling various complex work in the chip, the I2C controller analyzes and responds to corresponding commands when being configured to be in a working mode of the slave device, and initiates access commands to the slave device externally connected with the chip when being configured to be in a working mode of the master device. Other logic refers to components such as buses and memory that are present in the chip.
The control CPU part mainly flexibly controls the CPU to be designed in the simulation platform, can flexibly control the execution action of the CPU in the simulation environment, and is the greatest advantage of the invention compared with the current simulation technology. The excitation generating and sending component is mainly used for applying excitation to the design to be tested in the simulation platform, observing whether the work and response of the design to be tested are normal or not, and controlling the CPU behavior by controlling the CPU component at any time in the excitation applying process. Controlling the interaction mechanism between the CPU component and the stimulus generation and transmission component: in the simulation platform, a control CPU part and an excitation generation and transmission part can interact with each other, random data generated by excitation random can be controlled by certain configuration of the control CPU part, and certain behavior control can be performed on the part of the control CPU by certain values generated by the excitation random; the CPU can be controlled by the simulation environment at any time in the excitation sending process, so that the processing of some chip abnormal conditions can be verified more flexibly.
EXAMPLE III
The embodiment of the invention also provides an SOC system-level verification simulation platform, which comprises the simulation platform in the SOC system-level verification system of any embodiment.
Example four
Referring to fig. 4, an embodiment of the present invention provides a system-on-chip verification method for an SOC chip corresponding to the embodiment, including the following steps:
s1, starting simulation operation, and compiling a software program in a simulation platform; compiling codes by using a simulation tool (VCS, IRUN) commonly used by a chip, and compiling a simulation platform and an SOC design to be tested; running the compiled code, and starting simulation by using simulation work;
s2, controlling the CPU to enter a debugging mode, generating an indication signal for starting verification by the simulation platform, outputting the indication signal through a debugging interface, and controlling the CPU of the SOC chip to enter the debugging mode;
the CPU loads instructions to run in a default power-on state, and because the CPU is not controlled by compiled instructions, the CPU is controlled to enter a debugging mode by using a control CPU component in the simulation environment through a debugging interface, so that the CPU can generate corresponding actions according to behaviors given by the simulation environment. The method is realized by utilizing a control CPU component in a simulation environment;
s3, controlling the CPU to configure related functions of the design to be tested according to the verification scene: controlling a CPU to configure related functions of a module to be verified according to a working mode required by a verification scene;
the working mode scheduling of the design to be tested needs a CPU to control and schedule, the design to be tested needs to enter a working mode required by a verification scene during simulation, and whether the function meets the design index is verified by matching with excitation. The method is realized by utilizing a control CPU component in a simulation environment;
s4, excitation generation and transmission: generating and transmitting random excitation data to the excitation transmitting interface according to the configuration of the function; in order to verify a certain function repeatedly, the CPU can be controlled to configure the certain function of the module to be verified for multiple times, and the excitation data is used for generating multiple excitation data for verifying the same function;
in the simulation environment, excited data are generated according to random with constraint, and the data are sent to an interface to be tested through an excitation sending interface in a driver (driver) according to the time sequence requirement of the corresponding interface. Controlled by a stimulus generation and transmission component in the verification environment.
Other stimuli send: in simulation, multiple random excitations are often needed for a certain function to more fully verify the function, so that a circulation mechanism is needed. This is achieved by using excitation generation and transmission components in a simulation environment.
S5, overtime of the design to be tested: receiving or collecting response data of a module to be verified and judging whether the response data is overtime or not;
and setting an overtime mechanism in the verification environment, wherein the design is not expected or does not respond to the design to be tested due to other reasons, and the simulation runs overtime and reports errors. The design under test of the SOC chip is monitored by other components in the verification environment.
S6, finishing verification and reporting errors when the response data is overtime, and checking whether the response data is correct when the response data is not overtime;
s7, finishing simulation and reporting errors: finishing verification and reporting errors when the response data are wrong, and judging whether other excitation data exist or not when the response data are correct;
when obvious errors occur in the simulation, the corresponding errors are reported at the moment, and the simulation is finished to carry out subsequent error checking work. Implemented with other components in the simulation environment.
S8, finishing simulation: the verification is ended when there is no other stimulus data, and S3 is returned when there is other stimulus data.
And after all the excitation transmission is simulated, normally ending the simulation. Implemented with other components in the simulation environment.
The novel SOC verification method provided by the invention can carry out SOC simulation work without compiling C codes by software, is of great significance for improving code maintenance and development of verification personnel, and simultaneously improves the overall verification efficiency.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A system-level verification system of an SOC chip is characterized by comprising a simulation platform and the SOC chip;
the SOC chip comprises a CPU, a debugging interface connected with the CPU, a module to be verified and an excitation sending interface connected with the module to be verified;
the simulation platform comprises:
the control CPU model is connected with the module to be verified through the debugging interface according to an interface protocol; receiving an indication signal of starting verification when the verification is started and controlling a CPU to enter a debugging mode, receiving an indication signal of finishing the verification when the verification is finished and controlling the CPU to exit the debugging mode, wherein the CPU acts according to an instruction of controlling a CPU model in the debugging mode;
the excitation sending model is connected with the module to be verified through the excitation sending interface according to an interface protocol, and is used for generating excitation data, sending the excitation data to the module to be verified and collecting or receiving response data of the module to be verified;
and the result analysis model is used for analyzing and judging the response data of the verification module, outputting a verification result and outputting an indication signal of verification end according to the verification result.
2. The SOC chip system-on-a-chip verification system of claim 1, wherein the control CPU model is built based on UVM verification methodology; and controlling the CPU to configure the related functions of the module to be verified according to the working mode required by the verification scene, and scheduling the peripheral equipment.
3. The SOC chip system-on-a-chip verification system of claim 2, wherein the excitation sending model is built based on a UVM verification methodology, generates excitation data according to a working mode and sends the excitation data to the excitation sending interface.
4. The SOC chip system-on-chip verification system according to claim 3, wherein a loop mechanism is arranged inside the control CPU model and the stimulus transmission model, and any function in the module to be verified repeatedly verifies the function by generating multiple times of random stimulus data in the stimulus transmission model according to the configuration in the control CPU model during verification.
5. The SOC chip system-on-chip verification system according to claim 1, wherein the result analysis model outputs a verification end indication signal when at least one of response data feedback time of the module to be verified is overtime or no response occurs, response data is incorrect, and excitation data is sent out.
6. The SOC chip system-on-chip verification system of claim 5, wherein the result analysis model initiates an error checking procedure to query for the type of the response data error and output an error checking result after sending an indication signal of end of verification due to the response data error of the module to be verified.
7. The SOC chip system-on-a-chip verification system according to any one of claims 1 to 6, wherein the debug interface and the stimulus interface both adopt the interface method in the systemverilog to realize the connection between the simulation platform and the module to be verified.
8. An SOC chip system-level verification simulation platform, comprising the simulation platform in the SOC chip system-level verification system of any one of claims 1 to 7.
9. A system-level verification method of an SOC chip is characterized in that the SOC chip comprises a CPU, a debugging interface connected with the CPU, a module to be verified and an excitation sending interface connected with the module to be verified; the method comprises the following steps:
step 1, compiling a simulation platform and an SOC design to be tested by using a chip simulation tool;
step 2, starting the whole simulation program according to the setting of the simulation platform, outputting the simulation program through a debugging interface, and controlling a CPU (central processing unit) of the SOC chip to enter a debugging mode;
step 3, controlling the CPU to configure the related functions of the module to be verified according to the working mode required by the verification scene;
step 4, generating and sending random excitation data to an excitation sending interface according to the configuration of the function;
step 5, receiving or collecting response data of the module to be verified and judging whether the response data is overtime or not;
step 6, finishing verification and reporting errors when the response data is overtime, and checking whether the response data is correct when the response data is not overtime;
step 7, finishing verification and reporting errors when the response data are wrong, and judging whether other excitation data exist when the response data are correct;
and 8, finishing the verification when no other stimulus data exists, and returning to the step 3 when other stimulus data exists.
10. The SOC chip system-in-verification method as claimed in claim 9, wherein in the generating and transmitting random stimulus data to the stimulus transmission interface according to the configuration of the function, the stimulus data includes a plurality of stimulus data verifying the same function.
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