CN110688811B

CN110688811B - Random weight controllable method for accelerating design verification of SOC module

Info

Publication number: CN110688811B
Application number: CN201910864165.6A
Authority: CN
Inventors: 石易明; 刘大铕; 李风志; 戴绍新; 姚香君; 李文军
Original assignee: Shandong Sinochip Semiconductors Co Ltd
Current assignee: Shandong Sinochip Semiconductors Co Ltd
Priority date: 2019-09-12
Filing date: 2019-09-12
Publication date: 2023-05-02
Anticipated expiration: 2039-09-12
Also published as: CN110688811A

Abstract

The invention discloses a method for accelerating design verification of an SOC module with controllable random weight, which comprises the steps of adding an OR operation module between a digital logic module and a FIFO, wherein one input end of the OR operation module is connected with the output end of the FIFO, the other input end of the OR operation module is connected with a random 0/1 generation module, or the output end of the OR operation module is connected with the digital logic module, and during simulation verification, a full signal output by the FIFO and a numerical value generated by the 0/1 generation module are subjected to OR operation, then the OR operation result is transmitted to the digital logic module, and the digital logic module generates a push signal pressed into the FIFO correspondingly according to the input OR operation result. The method can collide the corner errors in the digital logic by using short simulation, thereby accelerating the process of module design verification; and the random part can control the random weight more accurately, so that the simulation effect has better controllability.

Description

Random weight controllable method for accelerating design verification of SOC module

Technical Field

The invention relates to a method for accelerating design verification of an SOC module with controllable random weight, and belongs to the technical field of digital circuit function simulation verification.

Background

The development of the digital front end of the current SOC (system on a chip) basically realizes modularized development flow, and common modules such as an interface controller module, an algorithm hardware acceleration module, a protocol conversion bridging module and the like basically use FIFO in the design of a digital circuit stage.

As a first-in first-out circuit unit, there are usually an input "push" signal (abbreviated as push) and an output "full" indication signal (abbreviated as full) at the data entry end of the FIFO, and various timings and combinational logic in the design of the module are usually directly or indirectly associated with the logic of the two signals; especially, when the application scene of the module is numerous, the logic for generating the push signal may be complex, so that logic errors are also generated in the design verification process. The traditional method generally comprises the steps of constructing a random regression verification platform outside a module, and indirectly transmitting bandwidth differences between two ends outside the module to a FIFO (first in first out) in the module through random variables such as clock frequency related to transmission bandwidths at two ends outside the module in the platform, so that the bandwidth of an input end of the FIFO is larger, the situation that the depth is filled gradually occurs after a period of time, and at the moment, a full signal can be changed in height and can collide with potential logic errors in the current module along with a large number of regression simulations; this process is time consuming and the "full" signal transitions from the external signal conduction through the random module to the internally manufactured FIFO output are less random.

Disclosure of Invention

The invention aims to provide a method for accelerating the design verification of an SOC module with controllable random weight, which can collide corner errors in digital logic by using short simulation so as to accelerate the process of the design verification of the module; and the random part can control the random weight more accurately, so that the simulation effect has better controllability.

In order to solve the technical problems, the invention adopts the following technical scheme: a method for accelerating design verification of an SOC module with controllable random weight comprises the following steps: s01), an OR operation module is added between the digital logic module and the FIFO, one input end of the OR operation module is connected with the output end of the FIFO, the other input end of the OR operation module is connected with a random 0/1 generation module, or the output end of the OR operation module is connected with the digital logic module, the FIFO, the OR operation module and the 0/1 generation module are all positioned in the SOC module to be designed, the digital logic module and the FIFO are integrated into a circuit, or the operation module and the 0/1 generation module are not integrated into a circuit; s02), during simulation verification, the full signal output by the FIFO and the numerical value generated by the 0/1 generating module are subjected to OR operation, then the OR operation result is transmitted to the digital logic module, the digital logic module generates a corresponding push signal pressed into the FIFO according to the input OR operation result, and when the relation between the push signal and the OR operation result is that the OR operation result is high, the push signal cannot be high.

Further, whether the OR operation module and the 0/1 generation module are started or not is confirmed by adopting a macro definition mode, when the macro is defined, the OR operation module and the 0/1 generation module are started, the digital logic module collects the FIFO output and the result after random 0/1 OR operation, when the macro is not defined, the OR operation module and the 0/1 generation module are not started, and the digital logic module directly collects the FIFO output.

Further, only at the time of simulation verification, macros are defined.

Further, the OR operation module and the 0/1 generation module are simulation structures compiled by a systemverilog language.

Further, the 0/1 generating module generates weight of 0 or 1 to be controllable, and the method for controlling the weight of 0 or 1 comprises the following steps: s11), setting a dynamic array, wherein the size of the dynamic array is set to be the simulated beat number, and then enabling all elements of the dynamic array to be equal to 0; s12), determining the weight of 1 at random, and then calculating the effective beat number of 1 at random according to a formula 1, wherein the formula 1 is as follows: a 1-random effective beat = simulated beat a 1-random weight; s13), starting from the first element of the dynamic array, sequentially filling 1 into the following elements; s14), judging whether the filling times are equal to 1 effective beats at random, if not, repeating the step S13 to continue filling, and if so, calling the functions of the systemverilog array to disturb all elements; s15), judging whether the last element of the array is equal to 1, if not, continuing to use the function of the system verilog array to disturb all elements, and if so, inputting the generated random number into the or operation module.

Further, the 0/1 generating module generates weight of 0 or 1 to be controllable, and the method for controlling the weight of 0 or 1 comprises the following steps: s21), setting a dynamic array, wherein the size of the dynamic array is set to be the simulated beat number, and then enabling all elements of the dynamic array to be equal to 0; s22), determining the weight of 1 at random, and then calculating the valid number of beats with 1 at random according to a formula 1, wherein the formula 1 is as follows: valid=simulated beat number randomly 1 the weight randomly 1; s23), randomly outputting a position index pn of an element equal to 1 in the dynamic array; s24), filling 1 into array elements of the corresponding position pointed by the position index pn; s25), judging whether the number of times of filling 1 is equal to the effective beat number of 1 at random, if not, continuing to fill 1 at random new element positions until valid elements in the array are equal to 1, and if so, inputting the generated random number into the OR operation module.

Further, in step S23, the array element position index that is not repeated at each random is ensured by using the keyword random of systemverilog.

The invention has the beneficial effects that: the invention replaces the full signal actually output by the FIFO with the full signal actually output by the FIFO and the result after the random value logic or operation, realizes the condition that the full signal actually sampled has alternating height to the greatest extent, so that the corner error in the digital logic is collided by short simulation, thereby accelerating the process of module design verification; and the random part can control the random weight more accurately, so that the simulation effect has better controllability.

In the traditional module design simulation process, only one logic condition of a certain circuit can be run out by one simulation, for example, the depth of the FIFO is a fixed value; in the aspect of sampling full signals by the digital logic module, the invention is equivalent to changing the fixed depth FIFO in the module into the FIFO with the depth changing randomly and dynamically, thereby being capable of running out logic conditions of multiple traditional simulations in one simulation, debugging logic details in design more quickly and improving the efficiency of design verification.

Drawings

FIG. 1 is a schematic diagram of a present SOC module design verification;

FIG. 2 is a schematic diagram of design verification of an SOC module according to the present invention;

FIG. 3 is a schematic waveform diagram after randomization;

FIG. 4 is a flowchart of example 1 for randomly generating 0 or 1;

fig. 5 is a flowchart for randomly generating 0 or 1 in example 2.

Detailed Description

The invention will be further described with reference to the drawings and the specific examples.

Example 1

In the design process of an SOC module, FIFOs are usually used as common circuit units for each module to call, as shown in fig. 1, the outermost box represents the SOC module, the rectangular bar on the right side in the box represents the FIFOs, and one end of each FIFO is used as a first-in first-out buffer circuit unit, and the other end of each FIFO is used for entering data and outputting data. FIG. 1 is a simplified diagram of a push-in and full signal at one end (rectangular left end) of incoming data, the data and push-in signal together being input into the FIFO, the full signal being an output signal reflecting in real time whether the entire depth of the FIFO has been filled, the FIFO becoming gradually full if the FIFO outputs slow or no data but the input end continues to push in data; the relevant signals of the output data at the right end of the rectangle are omitted.

The left box represents the digital logic that generates the push-in push and samples the full signal in real time, samples the full signal if full, the push signal cannot be high, and when the push is high when the full signal is not high is based on the data input condition of the whole SOC module (outer box).

In the design verification process of the SOC module, the main purpose is to fully simulate the interaction of the FIFO and other logic (left square block in the schematic diagram 1) in the module in different input and output scenes, wherein one important point is that the full signal sampled by the left square block is enabled to have the condition of alternating high and low to the greatest extent; if the sampled full signal is not always high or rarely high, the design logic problem of the part indicated by the left box in the limit situation cannot be impacted, and is generally considered to be insufficient verification simulation;

the traditional method is that the data input/output bandwidth outside the module (outer layer box) is adjusted, and the data is indirectly conducted through logic between the FIFO and the module, so that a scene that the FIFO entry end (left end in the figure) rapidly pushes data and the FIFO output end (right end) is very slow or basically does not output data is manufactured, and the full signal is enabled to have the condition of high-low alternation; this is time consuming, especially when the FIFO depth is large, and even if the FIFO ingress and egress rates differ significantly, it takes a long simulation time to get full high, and although a large number of simulations can collide with most of the logic scenarios with a long enough time, the efficiency is too low.

Aiming at the situation, the embodiment discloses a method for accelerating the design verification of an SOC module with controllable random weight, which comprises the following steps: s01), as shown in FIG. 2, an OR operation module is added between the digital logic module and the FIFO, one input end of the OR operation module is connected with the output end of the FIFO, the other input end of the OR operation module is connected with a random 0/1 generation module, the output end of the OR operation module is connected with the digital logic module, the FIFO, the OR operation module and the 0/1 generation module are all positioned in the SOC module to be designed, the digital logic module and the FIFO are integrated into a circuit, or the operation module and the 0/1 generation module are not integrated into a circuit; s02), during simulation verification, the full signal output by the FIFO and the numerical value generated by the 0/1 generating module are subjected to OR operation, then the OR operation result is transmitted to the digital logic module, the digital logic module generates a corresponding push signal pressed into the FIFO according to the input OR operation result, and when the relation between the push signal and the OR operation result is that the OR operation result is high, the push signal cannot be high.

The logical OR is characterized in that when any one of the two quantities is 1, the result output by the logical OR is 1, and only when the two quantities are 0, the result output by the logical OR is 0; that is, when the full signal output by the FIFO is 1, i.e., the FIFO is full, the result of the logical or is 1, regardless of the random value newly added; thus, when the FIFO is truly full, the full signal sampled by the digital logic of the left square frame, namely the output of the OR gate, is guaranteed to be full, and the original functions of the part are guaranteed not to be influenced by the newly added logic; conversely, when the full signal output by the FIFO is 0, i.e. the FIFO is not full, the left box, which is the part of the digital logic samples, is the output of the or gate; this achieves that full sampled must be high when the FIFO is truly full, and that it is possible that full is high when the FIFO is not full, i.e. increases the chance that full is high.

Fig. 1 is a schematic diagram of a general design of a FIFO in a module, all parts being synthesizable into circuits. An important difference in the modified part of fig. 2 is that the newly added part, in particular the random number part, is an uncombined structure. That is, the main innovation point of the invention is to embed an uncombinable simulation structure in the synthesizable circuit module, wherein the synthesizable circuit module refers to a digital logic module and a FIFO, and the simulation structure controlled by macro definition and uncombined into a circuit refers to an OR operation module and a 0/1 generation module, wherein the 0/1 generation module is uncombinable.

Or the operation module and the 0/1 generation module are only used for functional simulation, in order to facilitate the use in simulation, a macro definition mode is adopted to confirm whether the operation module and the 0/1 generation module are started, the macro is defined only in simulation verification, the operation module and the 0/1 generation module are started, the digital logic module collects the results after the FIFO output and the random 0/1 OR operation, when the macro is not defined, the operation module and the 0/1 generation module are not started, and the digital logic module directly collects the FIFO output.

The simulation structure of the OR operation module is implemented by using the system verilog language in this embodiment, namely, the process of performing OR operation on the FIFO output and the random 0/1, which is specifically the following procedure:

`ifdef TEST_TURBO

.bp_mst_wr_cmd_full (mst_wr_cmd_full | bp_mst_wr_cmd_rand ),

`else

.bp_mst_wr_cmd_full (mst_wr_cmd_full ),

`endif

.bp_mst_wr_cmd_push (bp_mst_wr_cmd_push ),

in the above procedure, bp_mst_wr_cmd_full represents the signal sampled by the digital logic module in fig. 1 and 2, mst_wr_cmd_full represents the "full" signal output by the FIFO, and bp_mst_wr_cmd_full_rand represents the random 0,1 signal; the lower row of else represents the case where the two sides of fig. 1 are directly connected, and the upper row of else represents fig. 2, i.e. the result after the digital logic module samples "full signal output from FIFO and random 0,1 value.

When test_turbo in the above procedure is defined, the connection case of fig. 2 is implemented (for simulation only), and when it is not defined, the connection case of fig. 1 is implemented (all of which can be integrated into a circuit).

The simulation structure of the random 0/1 generation module of the system verilog language is used in the embodiment, and the following procedure is specifically adopted:

`ifdef TEST_TURBO

initial

begin

forever

begin

@(posedge bp_clk) bp_mst_wr_cmd_full_rand=$urandom_range(0,1);

end

`endif

the code is a part which can not be synthesized into a circuit, is embedded in a module and is controlled by the same macro definition in an OR operation program; the above procedure gives a simple example of generating random 0,1, the randomness of which can be controlled more finely, e.g. controlling the respective weights of random 0 and 1, etc.;

the specific effect after randomization is shown in fig. 3.

In fig. 3, bp_mst_wr_cmd_full represents the signal actually sampled by the left block in fig. 1 and 2, mst_wr_cmd_full represents the "full" signal actually output by the FIFO, bp_mst_wr_cmd_full_rand represents the random 0,1 signal, and the last one is the push signal of the last row in fig. 3;

as can be seen from fig. 3, the "full" signal actually output by the FIFO (the second signal in the figure) is high for only one beat, but after performing or operation with random 0,1 (the third signal in fig. 3), the first signal in fig. 3 (representing the signal actually sampled by the left box in fig. 1 and 2) is generated, and it can be seen that the high-low jump of this signal is significantly more than that of the second signal in fig. 3, according to the rule that the FIFO "actually samples full signal, if full, the push signal cannot be high", the lowest push signal in fig. 3 is divided into a plurality of single beats by more obvious jumps, and the logic waveform when "full" is multiple times can be simulated;

therefore, the situation that the signals actually sampled by the left square boxes in the figures 1 and 2 are alternated in height to the greatest extent is realized, so that the design logic problem of the part indicated by the left square boxes in the limit situation is collided, the full verification simulation is realized, and the corner logic problem in the module design is modified.

As shown in fig. 4, the 0/1 generating module generates a weight of 0 or 1 to be controllable, and the method for controlling the weight of 0 or 1 comprises the following steps: s11), setting a dynamic array, wherein the size of the dynamic array is set to be the simulated beat number, and then enabling all elements of the dynamic array to be equal to 0; s12), determining the weight of 1 at random, and then calculating the effective beat number of 1 at random according to a formula 1, wherein the formula 1 is as follows: a 1-random effective beat = simulated beat a 1-random weight; s13), starting from the first element of the dynamic array, sequentially filling 1 into the following elements; s14), judging whether the filling times are equal to 1 effective beats at random, if not, repeating the step S13 to continue filling, and if so, calling the functions of the systemVerilog array to disturb all elements; s15), judging whether the last element of the array is equal to 1, if not, continuing to use the function of the systemVerilog array to disturb all elements, and if so, inputting the generated random number into the or operation module.

Example 2

As shown in fig. 5, the 0/1 generating module generates a weight of 0 or 1 to be controllable, and the method for controlling the weight of 0 or 1 comprises the following steps: s21), setting a dynamic array, wherein the size of the dynamic array is set to be the simulated beat number, and then enabling all elements of the dynamic array to be equal to 0; s22), determining the weight of 1 at random, and then calculating the valid number of beats with 1 at random according to a formula 1, wherein the formula 1 is as follows: valid=simulated beat number randomly 1 the weight randomly 1; s23), randomly outputting the position index pn of the element which is equal to 1 in the dynamic array, and ensuring the position index of the array element which is not repeated in each random by using the keyword random of the systemVerilog; s24), filling 1 into array elements of the corresponding position pointed by the position index pn; s25), judging whether the number of times of filling 1 is equal to the effective beat number of 1 at random, if not, continuing to fill 1 at random new element positions until valid elements in the array are equal to 1, and if so, inputting the generated random number into the OR operation module.

Otherwise, the same as in example 1 will not be described here.

The foregoing description is only of the basic principles and preferred embodiments of the present invention, and modifications and alternatives thereto will occur to those skilled in the art to which the present invention pertains, as defined by the appended claims.

Claims

1. A method for accelerating design verification of an SOC module with controllable random weight is characterized by comprising the following steps of: the method comprises the following steps: s01), an OR operation module is added between the digital logic module and the FIFO, one input end of the OR operation module is connected with the output end of the FIFO, the other input end of the OR operation module is connected with a random 0/1 generation module, the 0/1 generation module is provided with a dynamic array and enables elements in the dynamic array to be 0 or 1 randomly, the generated random numbers are input into the OR operation module, the output end of the OR operation module is connected with the digital logic module, the FIFO, the OR operation module and the 0/1 generation module are all positioned in the SOC module to be designed, the digital logic module and the FIFO are integrated into a circuit, or the operation module and the 0/1 generation module are not integrated into the circuit; s02), during simulation verification, the full signal output by the FIFO and the numerical value generated by the 0/1 generating module are subjected to OR operation, then the OR operation result is transmitted to the digital logic module, the digital logic module generates a corresponding push signal pressed into the FIFO according to the input OR operation result, and when the relation between the push signal and the OR operation result is that the OR operation result is high, the push signal cannot be high;

the 0/1 generating module generates weight of 0 or 1 to be controllable, and the method for controlling the weight of 0 or 1 comprises the following steps: s01), setting a dynamic array, wherein the size of the dynamic array is set to be the simulated beat number, and then enabling all elements of the dynamic array to be equal to 0; s02), determining the weight of 1 at random, and then calculating the effective beat number of 1 at random according to a formula 1, wherein the formula 1 is as follows: a 1-random effective beat = simulated beat a 1-random weight; s03), setting the corresponding elements of the dynamic array to be 1 in a mode of filling 1 in sequence or filling 1 in array elements of corresponding positions pointed by the position indexes pn; s04) when filling 1 in sequence, judging whether the filling times are equal to 1 effective beats at random, if not, repeating the step S03 to continue filling, and if so, calling the functions of the systemverilog array to disturb all elements; judging whether the last element of the array is equal to 1, if not, continuing to use the function of the system verilog array to disturb all elements, and if so, inputting the generated random number into the or operation module; when filling 1 according to array elements of the corresponding position pointed by the position index pn, judging whether the number of times of filling 1 is equal to 1 effective beat number, if not, continuing to fill 1 with new random element positions until valid elements in the array are equal to 1, and if so, inputting the generated random number into the or operation module.

2. The method for accelerating design verification of an SOC module with controllable random weights as claimed in claim 1, wherein: and confirming whether the OR operation module and the 0/1 generation module are started or not by adopting a macro definition mode, when the macro is defined, starting the OR operation module and the 0/1 generation module, acquiring a result after the FIFO output and the random 0/1 OR operation by the digital logic module, and when the macro is not defined, not starting the OR operation module and the 0/1 generation module, and directly acquiring the FIFO output by the digital logic module.

3. The method for accelerating design verification of an SOC module with controllable random weights as claimed in claim 2, wherein: only at the time of simulation verification, macros are defined.

4. The method for accelerating design verification of an SOC module with controllable random weights as claimed in claim 1, wherein: the OR operation module and the 0/1 generation module are simulation structures compiled by the systemverilog language.

5. The method for accelerating design verification of an SOC module with controllable random weights as claimed in claim 1, wherein: in step S23, the key random of systemverilog is used to ensure a non-duplicate array element position index at each random.