WO2011023847A1 - Method for integrated circuit design verification in a verification environment - Google Patents
Method for integrated circuit design verification in a verification environment Download PDFInfo
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- WO2011023847A1 WO2011023847A1 PCT/FI2010/050250 FI2010050250W WO2011023847A1 WO 2011023847 A1 WO2011023847 A1 WO 2011023847A1 FI 2010050250 W FI2010050250 W FI 2010050250W WO 2011023847 A1 WO2011023847 A1 WO 2011023847A1
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Abstract
A method comprises obtaining a reference model (170) and a register transfer level model (172) to a design verification test bench (152). Critical decision branches of the reference model (170) or the register transfer level model (172) are determined. For the critical decision branches are determined the reverse execution paths for reaching the branches. The variable values for entering the critical decision branches are determined. From the variable values are determined input vector values required for obtaining the variable values. Test cases are determined based on the input vector values determined. The test cases are written to a memory within a test bench apparatus. The test cases are executed using the reference model (170) and the register transfer level model (172).
Description
TITLE OF THE INVENTION
METHOD FOR INTEGRATED CIRCUIT DESIGN VERIFICATION IN A VERIFICATION ENVIRONMENT BACKGROUND OF THE INVENTION
Field of the invention:
The invention relates to Integrated Circuits (IC) design and development. Particularly, the invention relates to a method for integrated circuit design verification in a verification environment.
Description of the Related Art:
Integrated Circuits (IC) are manufactured on the surface of a semiconductor substrate material. The manufacturing is based on imaging, deposition and etching steps where patterns from predesigned photo masks are projected on a light-sensitive chemical resist on the surface to produce an exposure pattern. Thereupon, chemical processes are applied to engrave the exposure pattern into the substrate underneath the photo resist. A semiconductor wafer may undergo dozens of photolithographic cycles. The photo masks are produced by printing graphical models of different layers of the circuit. The graphical models in turn may be produced from a logical model of the circuit. In order to avoid producing faulty circuits, it is necessary to be able to test the logical model of the circuit to be manufactured. The logical model may in turn be generated from a Register Transfer Level (RTL) model or the logical model may directly be an RTL model. The RTL model may also be produced from or accompanied by an even higher-level reference model, which describes the function of the circuit on an algorithmic level.
In addition to fixed design circuits there are Field-Programmable Gate Arrays (FPGA) , which allow the programming of gates on a universal purpose IC af-
ter the IC has been manufactured. An FPGA contains gates that may be configured to emulate any fixed IC.
For the programming of FPGAs and the producing of RTL or reference models, a number of Hardware Description Languages (HDL) has been developed. Examples of such HDLs comprise the Very High Speed Integrated Circuits Hardware Description Language VHSIC HDL (VHDL), SystemC and SystemVerilog. The models are in turn tested using test beds that run sequences of predefined test cases. A model being tested is often referred to as a Design Under Test (DUT) . The test cases are inputted to the models by the test bed, which also collects output responses from the models. The test bed may be defined at least partially using a test language, that is, a hardware verification language such as OpenVera, SystemC and SystemVerilog. The VHDL may also be used to define a test bed for testing a model. The test case related input data may be defined in or generated from a description language.
The problem in existing testing systems is that a user must table test algorithmic or RTL models to determine relevant test cases and the input data for each test case. It is important to achieve a wide coverage of condition branches in the models through the selection of right test cases. It is very difficult to determine relevant test cases, since the testing of all possible combinations of input logic vector values may be impossible due to the time required. The generation of purely random test cases or test with actual application data may actually never cover improbable decision branches.
Therefore, it would be beneficial to be able to automatically determine test cases necessary for correct functioning of a DUT. Similarly, it would be beneficial to avoid testing irrelevant, superfluous or duplicate test cases.
SUMN[ARY OF THE INVENTION:
The invention relates to a method, comprising: obtaining at least one of the reference model and the register transfer level model; determining at least one critical decision branch; determining at least one reverse execution path for entering the at least one critical decision branch; determining at least one variable value required for entering the at least one critical decision branch; determining at least one input vector value required for obtaining the at least one variable value; determining at least one test case based on the at least one input vector value determined; writing the at least one test case to at least one memory within an apparatus; and exe- cuting the at least one test case using the reference model and the register transfer level model.
The invention relates to a method, comprising: obtaining at least one of the reference model and the register transfer level model; determining a tar- get value for a target variable; determining at least one starting point for reverse execution path determination; determining at least one reverse execution path for entering the at least one starting point; determining at least one second variable value for at least one second variable required for obtaining the target value for the target variable; determining at least one input vector value required for obtaining at least one of the target value for the target variable and the at least one second variable value; determin- ing at least one test case based on the at least one input vector value determined; writing the at least one test case to at least one memory within an apparatus; and executing the at least one test case using the reference model and the register transfer level model.
The invention relates also to an apparatus, comprising: at least one memory configured to store a
design under test comprising at least one of a reference model and a register transfer level model; and at least one processor configured to determine at least one critical decision branch, to determine at least one reverse execution path for entering the at least one critical decision branch, to determine at least one variable value required for entering the at least one critical decision branch, to determine at least one input vector value required for obtaining the at least one variable value, to determine at least one test case based on the at least one input vector value determined, to write the at least one test case to the memory and to execute the at least one test case using the reference model and the register transfer level model .
The invention relates also to an apparatus, comprising: a memory configured to store a design under test comprising at least one of a reference model and a register transfer level model; and at least one processor configured to determine a target value for a target variable, to determine at least one starting point for reverse execution path determination, to determine at least one reverse execution path for entering the at least one starting point, to determine at least one second variable value for at least one second variable required for obtaining the target value for the target variable, to determine at least one input vector value required for obtaining at least one of the target value for the target variable and the at least one second variable value, to determine at least one test case based on the at least one input vector value determined, to write the at least one test case to at least one memory within an apparatus and to execute the at least one test case using the reference model and the register transfer level model.
The invention relates also to an apparatus, comprising: means for obtaining at least one of the
reference model and the register transfer level model; means for determining at least one critical decision branch; means for determining at least one reverse execution path for entering the at least one critical decision branch; means for determining at least one variable value required for entering the at least one critical decision branch; means for determining at least one input vector value required for obtaining the at least one variable value; means for determining at least one test case based on the at least one input vector value determined; means for writing the at least one test case to at least one memory within an apparatus; and means for executing the at least one test case using the reference model and the register transfer level model.
The invention relates also to an apparatus, comprising: means for obtaining at least one of the reference model and the register transfer level model; means for determining a target value for a target variable; means for determining at least one starting point for reverse execution path determination; means for determining at least one reverse execution path for entering the at least one starting point; means for determining at least one second variable value for at least one second variable required for obtaining the target value for the target variable; means for determining at least one input vector value required for obtaining at least one of the target value for the target variable and the at least one second variable value; means for determining at least one test case based on the at least one input vector value determined; means for writing the at least one test case to at least one memory within an apparatus; and means for executing the at least one test case using the refer- ence model and the register transfer level model.
The invention relates also to a computer program comprising code adapted to perform the following steps when executed on a data-processing system: obtaining at least one of the reference model and the register transfer level model; determining at least one critical decision branch; determining at least one reverse execution path for entering the at least one critical decision branch; determining at least one variable value required for entering the at least one critical decision branch; determining at least one input vector value required for obtaining the at least one variable value; determining at least one test case based on the at least one input vector value determined; writing the at least one test case to at least one memory within an apparatus; and executing the at least one test case using the reference model and the register transfer level model.
The invention relates also to a computer program comprising code adapted to perform the following steps when executed on a data-processing system: obtaining at least one of the reference model and the register transfer level model; determining a target value for a target variable; determining at least one starting point for reverse execution path determina- tion; determining at least one reverse execution path for entering the at least one starting point; determining at least one second variable value for at least one second variable required for obtaining the target value for the target variable; determining at least one input vector value required for obtaining at least one of the target value for the target variable and the at least one second variable value; determining at least one test case based on the at least one input vector value determined; writing the at least one test case to at least one memory within an apparatus; and executing the at least one test case using the reference model and the register transfer level model.
The invention relates also to a computer program product comprising: obtaining at least one of the reference model and the register transfer level model; determining at least one critical decision branch; de- termining at least one reverse execution path for entering the at least one critical decision branch; determining at least one variable value required for entering the at least one critical decision branch; determining at least one input vector value required for obtaining the at least one variable value; determining at least one test case based on the at least one input vector value determined; writing the at least one test case to at least one memory within an apparatus; and executing the at least one test case using the refer- ence model and the register transfer level model.
The invention relates also to a computer program product comprising: obtaining at least one of the reference model and the register transfer level model; determining a target value for a target variable; de- termining at least one starting point for reverse execution path determination; determining at least one reverse execution path for entering the at least one starting point; determining at least one second variable value for at least one second variable required for obtaining the target value for the target variable; determining at least one input vector value required for obtaining at least one of the target value for the target variable and the at least one second variable value; determining at least one test case based on the at least one input vector value determined; writing the at least one test case to at least one memory within an apparatus; and executing the at least one test case using the reference model and the register transfer level model.
In one embodiment of the invention, an input vector, that is, an input vector value instance to be provided to a model may be defined as a test transac-
tion or a number of test transactions. The input vector values may be generated based on random number constraints defined for the vector.
In one embodiment of the invention, an input vector represents an input pin or a set of interrelated input pins that are in an external interface of a model. The input pin or the set of interrelated input pins may be provided to at least one chip defined as part of the model. An input vector may have any number of bits. An input vector value is an instance of values assigned to the input vector bits that are valid during a given time interval. The time interval may be, for example, a given number of clock cycles.
In one embodiment of the invention, a cover- age analysis entity in a verification test bench is further configured to set as criteria for a critical decision branch at least one of most frequently occurring linearly independent branch, least frequently occurring linearly independent branch, a branch executed with probability lower than a predefined threshold probability, a branch related to a low or high value of a variable, and a branch on the highest level of nesting or occurring above or below a predefined level of nesting. By a high value or low value may be meant a maximum value and a minimum value, respectively.
In one embodiment of the invention, a coverage analysis entity in a verification test bench is configured to select at least two variables, to rate the at least two variables based on predefined rating criteria, to determine a maximum number of test cases and to select at least one test case based on the rating. The coverage analysis entity may also rate the target variable and the at least one second variable.
In one embodiment of the invention, a cover- age analysis entity in a verification test bench is configured to set as rating criteria at least one of a level of parallelism for the variable, cyclomatic com-
plexity of a module encapsulating the variable, frequency of use of the variable and frequency of use of the variable in branch decision clauses.
In one embodiment of the invention, a cover- age analysis entity in a verification test bench is configured to selecting a mutual order of significance of the rating criteria.
In one embodiment of the invention, at least one of the reference model and the register transfer level model in a verification test bench is configured to producing output data of the executing of the at least one test case. A result comparison entity in the verification test bench is configured to compare output data from the reference model to output data in the register transfer level and to determine a discrepancy as a result of the comparison.
In one embodiment of the invention, a coverage analysis entity in a verification test bench is configured to determine at least one ambiguous bit in a variable used in an operation in a decision clause associated with the at least one critical decision branch, to determine at least one ambiguous bit in an input vector based on the at least one ambiguous bit the variable and to eliminate at least one redundant test case from the at least one test case determined.
In one embodiment of the invention, the test cases are determined in a verification test bench by a sequence generation entity.
In one embodiment of the invention, at least one of the reference model and the register transfer level model are defined in a hardware verification language .
In one embodiment of the invention, a protocol checking entity is configured to determine the success of the testing using at least one predetermined expected output.
In one embodiment of the invention, the apparatus comprises a permanent storage, which may be comprised in a secondary memory, for example, as a disk partition, directory or a file. The permanent storage may be at least part of the storage space of a computer readable medium such as a flash memory, a magnetic or an optic disk.
In one embodiment of the invention, the computer program is stored on a computer readable medium. The computer readable medium may be a removable memory card, magnetic disk, optical disk or magnetic tape.
In one embodiment of the invention, the at least one processor is configured to execute the coverage analysis entity, the sequence generation entity and the protocol checking entity.
The embodiments of the invention described hereinbefore may be used in any combination with each other. Several of the embodiments may be combined together to form a further embodiment of the invention. A method, an apparatus or a computer program to which the invention is related may comprise at least one of the embodiments of the invention described hereinbefore .
The benefits of the invention is related to improved testing of designs, which further provides improved quality of ICs or FPGA. With the invention there may be fewer bugs in the designs. Also the time required in the generating of test cases may be reduced. With the invention, it may be possible to find bugs that would otherwise not be found.
BRIEF DESCRIPTION OF THE DRAWINGS:
The accompanying drawings, which are included to provide a further understanding of the invention and constitute a part of this specification, illustrate embodiments of the invention and together with
the description help to explain the principles of the invention. In the drawings:
Fig. 1 is a block diagram illustrating design verification environment in one embodiment of the in- vention;
Fig. 2 is a flow chart illustrating a design verification method in one embodiment of the invention;
Fig. 3 is a flow chart illustrating a vari- able rating method in one embodiment of the invention;
Fig. 4 is a variable ambiguity determination method in one embodiment of the invention;
Fig. 5 is a block diagram illustrating reverse execution path determination, variable value de- termination and input value determination in one embodiment of the invention; and
Fig. 6 is a flow chart illustrating a design verification method starting from variable corner cases in one embodiment of the invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS:
Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
Figure 1 is a block diagram illustrating design verification environment in one embodiment of the invention. In Figure 1 there is illustrated an apparatus 150, which comprises at least one processor, a primary memory and a secondary memory. The primary memory is, for example, a Random Access Memory (RAM) . The secondary memory may be, for example, a magnetic disk, an optic disk, a magneto-optic disk or a flash- memory. The internal functions of apparatus 150 are illustrated with a box 151. At least one memory in ap- paratus 150 is configured to store a verification test bench 152. Verification test bench 152 comprises a coverage analysis entity 154, a sequence generation
entity 156, a result comparison entity 166 and a protocol checking entity 168. Verification test bench 152 produces input data files 158 and 160. Input data files 158 and 160 are used to provide input data to a DUT, which comprises a reference model and an RTL model. From the execution of the DUT produces output data files 162 and 164. At least one memory in apparatus 150 is configured to store a reference model 170 and a Register Transfer Level (RTL) model 172. Models 170 and 172 are referred to as the DUT. Verification test bench 152 may be, for example, an executable file to which modules such as Dynamically Linked Libraries (DLL) representing models 170 and 172 are linked statically or dynamically. Models 170 and 172 may also be executed using an interpreter (not shown) in association with verification test bench 152. Verification test bench 152 may be implemented, for example, using a high-level programming language such as C, C++, C#, SystemC or OpenVera. Model 170 may be implemented, for example, using SystemC, C++ or VHDL. Model 172 may be implemented, for example, using VHDL or SystemVerilog. Input data files 158 and 160 may be defined, for example, using a specific test case definition language such as the e-language or they may be unstructured text files. The output data files 162 and 164 may, for example, conform to a proprietary format or be unstructured text files.
The starting point for the design verification method is that source code files for models 170 and 172 are produced for the use of verification test bench 152. Coverage analysis entity 154, in other words, a coverage analyzer determines critical decision branches in reference model 170 or RTL model 172. From the critical decision branches coverage analysis entity 154 determines critical input vector values required for reaching the critical decision branches in models 170 and 172. Coverage analysis entity 154 may
also determine the timing required for reaching the critical decision branches, that is, the clock cycles for providing the critical input vector values for models 170 and 172. The coverage analysis is illus- trated in Figure 1 with arrows IOOA and 10OB. The arrows illustrate the fact that verification test bench 152 reads input files 170 and 172 to determine the critical input vector values.
In one embodiment of the invention, the critical decision branches are the corner cases. By a corner case is meant a test case where at least one variable defined within the model has its low or high value within its domain, that is, a minimum or maximum value. The at least one variable defined within the model may be though of as spanning a multidimensional space where each scalar variable represents a dimension .
After or during the coverage analysis, sequence generation entity 156 writes to input data files 158 and 160 input vector values, which may correspond to each critical decision branch. There may be only a single input data file such as input data file 158, which is read by both models. The input vector values may be represented as a sequence of carriage return or line feed terminated lines or records, where each record comprises a start clock value, the values for the other input vector values during the time from the start clock value to a clock value in the next line or record. A user of verification test bench 152 may also define additional test cases with additional input vector values, in addition to the critical input vector values. The writing of data to input data files 158 and 160 by sequence generation entity 156 is illustrated with arrows 102A and 102B. In one embodiment of the invention, there is only one input data file, which is provided to both models 170 and 172.
After the generation of input data files 158 and 160, verification test bench 152 executes reference models 170 and 172. During the execution, verification test bench 152 provides input vector values from input data files 158 and 160 to models 170 and 172, as illustrated with arrows 103A and 103B. Further, during the execution models 170 and 172 generate data to output data files 162 and 164, as illustrated with arrows 104A and 104B, respectively. The output data may be represented as a sequence of carriage return or line feed terminated lines or records, where each record a start clock value, the values for the output vector values during the time from the start clock value to a clock value in the next line or re- cord. The execution of test cases may be implemented, for example, by compiling of models 170 and 172 into object files by verification test bench 152. Each test case execution may comprise the calling of a method, a procedure or a subroutine with input vector values corresponding to a single record or line in one of the input data files 158 and 160. The execution of a test case may provide an output record or line to one of the output data files 162 and 164. For example, the method, procedure or subroutine executed may return output vector values, which are used by verification test bench 152 to write a single record or line to one of the output data files 162 and 164. Models 170 and 172 provide output vector values for output data files 162 and 164, respectively.
During or after the execution of models 170 and 172, result comparison entity 166 compares the output records from output data files 162 and 164, as illustrated with arrows 105A and 105B. For each mismatch, an error message may be outputted to standard output or a log file. A protocol check entity 168 may observe the compliance of output data records or lines in one of output data files 162 and 164 to check that
output vector values comply with a protocol. The protocol checking may comprise the checking of output vector values with at least one protocol rule. A protocol rule may be obtained by protocol checking entity 168 from a rule file (not shown) using parsing.
In one embodiment of the invention, input data required in at least one of the input data files 158 and 160 is produced by sequence generation entity 156 using a rating of variables from the design de- fined in at least one of the models 170 and 172. The rating of variables comprises the ordering of variables to an increasing order of importance. Based on the ordering of variables, input vector values are ordered to an increasing order of importance. Based on the order of importance of input vector values, test cases are produced in sequence generation entity 156. In one embodiment of the invention, the rating of a variable is based on at least one of a cyclomatic complexity of a module encapsulating the variable, the inverse of a probability of a decision clause comprising the variable becoming assigned the Boolean value true, frequency of use, frequency of use in decision clauses and a level of parallelism of the variable. The level of parallelism of a variable is based on the number of linearly independent paths in one of models 170 and 172 in which the variable occurs.
Apparatus 150 comprises a processor, a primary memory and a secondary memory. There may be more than one processor. A processor may comprise multiple cores. Apparatus 150 may also comprise a network interface such as, for example, an Ethernet card. Primary memory may be a Random Access Memory (RAM) . Secondary memory is a non-volatile memory such as, for example, a magnetic or optical disk. When the proces- sor executes functionalities associated with the invention, the memory comprises entities such as, for example, coverage analysis entity 154, sequence gen-
eration entity 156, result comparison entity 166 and protocol checking entity 168. The entities within apparatus 150 in Figure 1 may be implemented in a variety of ways. They may be implemented as processes exe- cuted under the native operating system of the network node. The entities may be implemented as separate processes or threads or so that a number of different entities are implemented by means of one process or thread. A process or a thread may be the instance of a program block comprising a number of routines, that is, for example, procedures and functions. The entities may be implemented as separate computer programs or as a single computer program comprising several routines or functions implementing the entities. The program blocks are stored on at least one computer readable medium such as, for example, a memory circuit, memory card, magnetic or optic disk. Some entities may be implemented as program modules linked to another entity. The entities in Figure 1 may also be stored in separate memories and executed by separate processors, which communicate, for example, via a message bus or an internal network within the network node. An example of such a message bus is the Peripheral Component Interconnect (PCI) bus.
Figure 2 is a flow chart illustrating a design verification method in one embodiment of the invention .
At step 200 a reference model of a design is obtained. In one embodiment of the invention, the ref- erence model is a model of the design in a high-level programming language, which defines the behavior of the design in terms of decisions based on input vector values directly or indirectly. In one embodiment of the invention, the reference model is defined in asso- ciation with a verification test bench.
At step 202 a register transfer level model of the design is obtained. In one embodiment of the
invention, the register transfer level model is defined in association with a verification test bench.
At step 204 at least one critical decision branch is determined in at least one of the reference model and the register transfer level model. In one embodiment of the invention, the critical decision branches are the ones comprised in most frequently occurring linearly independent branches in at least one of the reference and the register transfer level model. In one embodiment of the invention, the critical decision branches are the ones comprised in least frequently occurring linearly independent branches in at least one of the reference and the register transfer level model. In one embodiment of the invention, the critical decision branches are the ones that are executed with probabilities lower than a predefined threshold probability. In one embodiment of the invention, the critical decision branches are the ones related to a low or high value of a variable within at least one of the reference model and register transfer level model. In one embodiment of the invention, the critical decision branches are determined as the ones on the highest level of nesting in the model or the ones occurring above or below a predefined level of nesting in the model. By the level of nesting of a decision branch may be meant the number of decision branches that must be traversed in order to reach the decision branch. The predefined level of nesting may be determined from the analysis of either the refer- ence or the register transfer level model of the design to be verified.
At step 206 at least one reverse execution path for entering the at least one critical decision branch in at least one of the register transfer level and the reference model is determined. In one embodiment of the invention, all reverse execution paths for entering the critical decision branch are determined.
At step 208 at least one variable value required for entering the at least one critical decision branch is determined based on the at least one reverse execution path. In one embodiment of the invention, all variable values required for entering the at least one critical decision branch are determined.
At step 210 at least one input vector value is determined based on the at least one variable value required for entering the at least one critical deci- sion branch. In one embodiment of the invention, all input vector values required for entering the at least one critical decision branch are determined based on the at least one variable value required for entering the at least one critical decision branch and the at least one reverse execution path required for entering the critical decision branch.
At step 212 the timing required for obtaining the at least one variable value is determined. In one embodiment of the invention the timing comprises a clock input vector so that step 212 may be considered as part of step 210.
At step 214 at least one test case is generated based on the at least input vector value and the timing determined. The at least one test case is writ- ten to a memory within an apparatus.
At step 216 the at least one test case is executed by reading the memory. The at least one test case is executed using the reference model and the register transfer level model. Thereupon, the method is finished.
Figure 3 is a flow chart illustrating a variable rating method in one embodiment of the invention.
At step 300 a cyclomatic complexity is computed for at least one module in at least one of the reference model and the register transfer level model. The cyclomatic complexity M is computed using the formula M = E - N + 2P, wherein E is the number of edges
in a graph representing the module, N is the number of nodes in the graph and P is the number of connected components in the graph. For a single subroutine or method P is always equal to 1. In case there are sev- eral alternative methods in a single object class or otherwise alternative disconnected paths through a module, P represents the number of such paths.
At step 302 at least one variable present in a decision clause is determined in the at least one of the reference model and the register transfer level model .
At step 304 it is determined which factors the rating involves. The factors involved in the rating comprise at least one of a level of parallelism for the variable, cyclomatic complexity of a module encapsulating the variable, frequency of use of the variable and frequency of use of the variable in branch decision clauses. By the level of parallelism is means the number of parallel execution paths through the at least one of the reference model and the register transfer level model that refer to the variable. Other factors involved in the rating may comprise the parameters given in the declaration of the variable such as type and bit length, relation to data inputs, relation to control inputs and relation to configuration inputs.
At step 306 the mutual significance of the factors involved in the rating is determined. The factors may be assigned to any mutual order of signifi- cance .
At step 308 the variables are ordered according to the rating.
At step 310 at least one input vector is determined that affects the at least one variable.
At step 312 at least two test cases are generated according to the rating of the variables and the at least one input vector determined. The at least
two test cases generated are written to a memory within an apparatus. Thereupon, the method is finished.
Figure 4 is a variable ambiguity determina- tion method in one embodiment of the invention.
At step 400 at least one decision branch variable is determined. In one embodiment of the invention, at least one decision branch variable required for entering at least one critical decision branch is determined.
At step 402 at least one domain variable involved in the producing of values for the at least one decision branch variable or a previously determined at least one domain variable from many-to-one mapping op- erations, that is, non-bijective mappings are determined.
At step 404 bitmasks are associated with the at least one domain variable determined.
At step 406 ambiguous bits in the associated bitmasks are determined.
At step 408 it is determined if there are more operations. If there are more operations, the method continues at step 402. Otherwise, the method continues at step 410.
At step 410 at least one input vector involved in the producing of a value for the at least one domain variable or a decision branch variable is determined. The value may be produced from a many-to- one mapping operation, a direct assignment or a one- to-one mapping.
At step 412 bitmasks are associated with the at least one input vector are determined.
At step 414 ambiguous bits in input vectors are marked. The ambiguous bits in input vectors are bits that are obtained from ambiguous bits in the at least one domain variable, which is assigned from an input vector, or bits that are ambiguous for the pur-
pose of producing the value for a many-to-one mapping operation. The operation is used to produce a value for the at least one domain variable or the at least one variable.
At step 416 test cases with ambiguous input vector bits are removed or otherwise eliminated from test cases to be produced. Thereupon, the method is finished.
Figure 5 is a block diagram illustrating re- verse execution path determination, variable value determination and input value determination in one embodiment of the invention. In Figure 5 there is illustrated a design module 500 with input vectors II, 12, 13 and 14.
The starting point in Figure 5 is that branch
BR has been determined as critical, for example, based on the criteria put forth in association the discussion of Figure 1.
At step 501 condition clause C3 is determined on a reverse execution path to branch BR. In an operation OP3 decision variables V3 and V4 are applied as an input. The result of OP3 is compared to constant X3. Operation OP3 is non-one-to-one resulting in the ambiguity of bits 6 - 7 in variables V3 and V4. Only bits 0 - 5 in variables V3 and V4 may be traced back to non-ambiguous values, which are a necessary condition for successfully comparing the result of OP3 on V3 and V4 to X3.
At step 502 condition clause C2 is determined on a reverse execution path to branch C3. In an operation OP2 decision variables V3 and V4 are applied as an input. The result of OP2 is compared to constant X2. Operation OP2 is not one-to-one resulting in the ambiguity of bits 4 - 7 in variables V3 and V4. Only bits 0 - 3 in variables V3 and V4 may be traced back to non-ambiguous values, which are a necessary condi-
tion for successfully comparing the result of 0P2 on V3 and V4 to X2.
At step 503 assignment of input vectors V3 :=
13 and V4 : = 14 in branch B2 is determined on a reverse execution path to branch C2. The bits 4 - 7 in input vectors 13 and 14 become ambiguous from the point of view of reaching critical branch BR.
At step 504 condition clause Cl is determined on a reverse execution path to branch B2. In an opera- tion OPl decision variables Vl and V2 are applied as an input. The result of OPl is compared to constant Xl. Operation OP2 is non-one-to-one resulting in the ambiguity of bits 4 - 7 in variables Vl and V2. Only bits 0 - 3 in variables Vl and V2 may be traced back to non-ambiguous values, which are a necessary condition for successfully comparing the result of OPl on Vl and V2 to Xl.
At step 505 assignment of input vectors Vl := Il and V2 : = 12 in branch Bl is determined on a reverse execution path to branch Cl. The bits 4 - 7 in input vectors Il and 12 become ambiguous from the point of view of reaching critical branch BR.
At step 506 it is determined that ambiguous bits in input vectors Il and 12 are bits 0 - 3. Simi- larly, ambiguous bits in input vectors 13 and 14 are bits 0 - 3. Thereupon, the method is finished.
Figure 6 is a flow chart illustrating a design verification method starting from variable corner cases in one embodiment of the invention.
At step 600 a reference model of a design is obtained. In one embodiment of the invention, the reference model is a model of the design in a high-level programming language, which defines the behavior of the design in terms of decisions based on input vector values directly or indirectly. In one embodiment of the invention, the reference model and the register transfer level model is defined in association with a
verification test bench such as illustrated in Figure 1.
At step 602 a register transfer level model of the design is obtained. In one embodiment of the invention, the register transfer level model is defined in association with a verification test bench.
At step 604 is determined a target value for a target variable. In one embodiment of the invention, a target value is, for example, 0, 1, minimum value and maximum value. These are variable corner values. There is at least one target variable for which target values are determined.
At step 606 is determined at least one starting point for reverse execution path determination. In one embodiment of the invention, the starting point is selected before entry to a module, method or subroutine interface in the reference model or the register transfer level model. In one embodiment of the invention, the starting point is at the end of a module, method, subroutine or program code of at least one of the reference model and the register transfer level model. In one embodiment of the invention, the starting point is before a condition clause, which may be on above or below a predefined level of nesting of branching conditions. In one embodiment of the invention, a user is provided by the user interface entity a user interface for selecting a point in a program code of at least one of the reference model and the register transfer level model. In one embodiment of the invention, the starting point is specified using a comment or other marker in the program code of at least one of the reference model and the register transfer level model. In one embodiment of the invention, the starting point is selected automatically by a verification test bench.
At step 608 is determined at least one reverse execution path for entering the at least one starting point.
At step 610 is determined at least one second variable value for at least one second variable required for obtaining the target value for the target variable. By a second variable is meant a variable the value of which affects the value of the target variable, through, for example, a value assignment or a mathematical or bitwise logical operation.
At step 612 is determined at least one input vector value required for obtaining at least one of the target value for the target variable and the at least one second variable value. In one embodiment of the invention, each of the at least one input vector value may be associated with a separate input vector. In one embodiment of the invention, the at least one input vector value may represent a different value for a single input vector at separate time intervals.
At step 614 is determined at least one test case based on the at least one input vector value determined. The at least one test case is written to a memory within an apparatus.
At step 616 the at least one test case is executed by reading the memory. Thereupon, the method is finished. The at least one test case is executed using the reference model and the register transfer level model .
In one embodiment of the invention, the method illustrated in Figure 2 may also comprise at least one step described in association with Figure 6. In one method of the invention the method illustrated in Figure 6 may also comprise at least one step described in association with Figure 3 or Figure 4.
In one embodiment of the invention, a coverage analysis entity as illustrated in Figure 1 per-
forms the steps 604 - 612, whereas steps 614 - 616 are performed by a sequence generation entity.
The exemplary embodiments of the invention can be included within any suitable device, for exam- pie, including any suitable servers, workstations, PCs, laptop computers, PDAs, Internet appliances, handheld devices, cellular telephones, wireless devices, other devices, and the like, capable of performing the processes of the exemplary embodiments, and which can communicate via one or more interface mechanisms, including, for example, Internet access, telecommunications in any suitable form (e.g., voice, modem, and the like) , wireless communications media, one or more wireless communications networks, cellular communications networks, G3 communications networks, Public Switched Telephone Network (PSTNs) , Packet Data Networks (PDNs), the Internet, intranets, a combination thereof, and the like.
It is to be understood that the exemplary em- bodiments are for exemplary purposes, as many variations of the specific hardware used to implement the exemplary embodiments are possible, as will be appreciated by those skilled in the hardware art(s) . For example, the functionality of one or more of the com- ponents of the exemplary embodiments can be implemented via one or more hardware devices.
The exemplary embodiments can store information relating to various processes described herein. This information can be stored in one or more memo- ries, such as a hard disk, optical disk, magneto- optical disk, RAM, and the like. One or more databases can store the information used to implement the exemplary embodiments of the present inventions. The databases can be organized using data structures (e.g., records, tables, arrays, fields, graphs, trees, lists, and the like) included in one or more memories or storage devices listed herein. The processes de-
scribed with respect to the exemplary embodiments can include appropriate data structures for storing data collected and/or generated by the processes of the devices and subsystems of the exemplary embodiments in one or more databases.
All or a portion of the exemplary embodiments can be implemented by the preparation of application- specific integrated circuits or by interconnecting an appropriate network of conventional component cir- cuits, as will be appreciated by those skilled in the electrical art(s).
As stated above, the components of the exemplary embodiments can include computer readable medium or memories according to the teachings of the present inventions and for holding data structures, tables, records, and/or other data described herein. Computer readable medium can include any suitable medium that participates in providing instructions to a processor for execution. Such a medium can take many forms, in- eluding but not limited to, non-volatile media, volatile media, transmission media, and the like. Nonvolatile media can include, for example, optical or magnetic disks, magneto-optical disks, and the like. Volatile media can include dynamic memories, and the like. Transmission media can include coaxial cables, copper wire, fiber optics, and the like. Transmission media also can take the form of acoustic, optical, electromagnetic waves, and the like, such as those generated during radio frequency (RF) communications, infrared (IR) data communications, and the like. Common forms of computer-readable media can include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other suitable magnetic medium, a CD-ROM, CDRW, DVD, any other suitable optical medium, punch cards, paper tape, optical mark sheets, any other suitable physical medium with patterns of holes or other optically recognizable indicia, a RAM, a
PROM, an EPROM, a FLASH-EPROM, any other suitable memory chip or cartridge, a carrier wave or any other suitable medium from which a computer can read.
While the present inventions have been de- scribed in connection with a number of exemplary embodiments, and implementations, the present inventions are not so limited, but rather cover various modifications, and equivalent arrangements, which fall within the purview of prospective claims.
It is obvious to a person skilled in the art that with the advancement of technology, the basic idea of the invention may be implemented in various ways. The invention and its embodiments are thus not limited to the examples described above; instead they may vary within the scope of the claims.
Claims
1. A method, comprising:
obtaining at least one of the reference model and the register transfer level model;
determining at least one critical decision branch; determining at least one reverse execution path for entering the at least one critical decision branch;
determining at least one variable value required for entering the at least one critical decision branch;
determining at least one input vector value required for obtaining the at least one variable value; determining at least one test case based on the at least one input vector value determined;
writing the at least one test case to at least one memory within an apparatus; and
executing the at least one test case using the reference model and the register transfer level model.
2. The method according to claim 1, the method further comprising:
setting as criteria for a critical decision branch at least one of most frequently occurring linearly independent branch, least frequently occurring linearly independent branch, a branch executed with probability lower than a predefined threshold probability, a branch related to a low or high value of a variable, and a branch on the highest level of nesting or occurring above or below a predefined level of nesting.
3. The method according to claim 1, the method further comprising:
selecting at least two variables;
rating the at least two variables based on predefined rating criteria;
determining a maximum number of test cases; and selecting at least one test case based on the rating.
4. The method according to claim 3, the method further comprising:
setting as rating criteria at least one of a level of parallelism for the variable, cyclomatic complexity of a module encapsulating the variable, frequency of use of the variable and frequency of use of the variable in branch decision clauses.
5. The method according to claim 1, the method further comprising:
selecting a mutual order of significance of the rating criteria.
6. The method according to claim 1, the method further comprising:
producing output data of the executing of the at least one test case;
comparing output data from the reference model to output data in the register transfer level; and
determining a discrepancy as a result of the comparison .
7. The method according to claim 1, the method further comprising:
determining at least one ambiguous bit in a variable used in an operation in a decision clause associated with the at least one critical decision branch; determining at least one ambiguous bit in an input vector based on the at least one ambiguous bit the variable; and
eliminating at least one redundant test case from the at least one test case determined.
8. The method according to claim 1, wherein the test cases are determined in a verification test bench .
9. The method according to claim 1, wherein at least one of the reference model and the register transfer level model are defined in a hardware verification language.
10. A method, comprising: obtaining at least one of the reference model and the register transfer level model;
determining a target value for a target variable; determining at least one starting point for re- verse execution path determination;
determining at least one reverse execution path for entering the at least one starting point;
determining at least one second variable value for at least one second variable required for obtaining the target value for the target variable;
determining at least one input vector value required for obtaining at least one of the target value for the target variable and the at least one second variable value;
determining at least one test case based on the at least one input vector value determined;
writing the at least one test case to at least one memory within an apparatus; and
executing the at least one test case using the reference model and the register transfer level model.
11. An apparatus, comprising:
a memory configured to store a design under test comprising at least one of a reference model and a register transfer level model; and
at least one processor configured to determine at least one critical decision branch, to determine at least one reverse execution path for entering the at least one critical decision branch, to determine at least one variable value required for entering the at least one critical decision branch, to determine at least one input vector value required for obtaining the at least one variable value, to determine at least one test case based on the at least one input vector value determined, to write the at least one test case to the memory and to execute the at least one test case using the reference model and the register transfer level model.
12. An apparatus, comprising:
means for obtaining at least one of the reference model and the register transfer level model;
means for determining at least one critical deci- sion branch;
means for determining at least one reverse execution path for entering the at least one critical decision branch;
means for determining at least one variable value required for entering the at least one critical decision branch;
means for determining at least one input vector value required for obtaining the at least one variable value;
means for determining at least one test case based on the at least one input vector value determined; means for writing the at least one test case to at least one memory within an apparatus; and
means for executing the at least one test case us- ing the reference model and the register transfer level model .
13. A apparatus comprising:
a memory configured to store a design under test comprising at least one of a reference model and a register transfer level model; and
at least one processor configured to determine a target value for a target variable, to determine at least one starting point for reverse execution path determination, to determine at least one reverse exe- cution path for entering the at least one starting point, to determine at least one second variable value for at least one second variable required for obtaining the target value for the target variable, to determine at least one input vector value required for obtaining at least one of the target value for the target variable and the at least one second variable value, to determine at least one test case based on the at least one input vector value determined, to write the at least one test case to at least one memory within an apparatus and to execute the at least one test case using the reference model and the regis- ter transfer level model.
14. An apparatus comprising:
means for obtaining at least one of the reference model and the register transfer level model;
means for determining a target value for a target variable;
means for determining at least one starting point for reverse execution path determination;
means for determining at least one reverse execution path for entering the at least one starting point;
means for determining at least one second variable value for at least one second variable required for obtaining the target value for the target variable; means for determining at least one input vector value required for obtaining at least one of the target value for the target variable and the at least one second variable value;
means for determining at least one test case based on the at least one input vector value determined;
means for writing the at least one test case to at least one memory within an apparatus; and
means for executing the at least one test case using the reference model and the register transfer level model .
15. A computer program comprising code adapted to perform the following steps when executed on a data-processing system:
obtaining at least one of the reference model and the register transfer level model;
determining at least one critical decision branch; determining at least one reverse execution path for entering the at least one critical decision branch;
determining at least one variable value required for entering the at least one critical decision branch;
determining at least one input vector value required for obtaining the at least one variable value; determining at least one test case based on the at least one input vector value determined;
writing the at least one test case to at least one memory within an apparatus; and
executing the at least one test case using the reference model and the register transfer level model.
16. The computer program according to claim
15, wherein said computer program is stored on a computer readable medium.
17. The computer program according to claim
16, wherein said computer readable medium is a remov- able memory card, a holographic memory, a magnetic disk or an optical disk.
18. A computer program comprising code adapted to perform the following steps when executed on a data-processing system:
obtaining at least one of the reference model and the register transfer level model;
determining a target value for a target variable; determining at least one starting point for reverse execution path determination;
determining at least one reverse execution path for entering the at least one starting point;
determining at least one second variable value for at least one second variable required for obtaining the target value for the target variable;
determining at least one input vector value required for obtaining at least one of the target value 34 for the target variable and the at least one second variable value;
determining at least one test case based on the at least one input vector value determined;
writing the at least one test case to at least one memory within an apparatus; and
executing the at least one test case using the reference model and the register transfer level model.
19. The computer program according to claim 18, wherein said computer program is stored on a computer readable medium.
20. The computer program according to claim 19, wherein said computer readable medium is a removable memory card, a holographic memory, a magnetic disk or an optical disk.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FI20095885A FI20095885A0 (en) | 2009-08-27 | 2009-08-27 | A method for verifying integrated circuit design in a verification environment |
| FI20095885 | 2009-08-27 |
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| Publication Number | Publication Date |
|---|---|
| WO2011023847A1 true WO2011023847A1 (en) | 2011-03-03 |
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ID=41050709
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/FI2010/050250 WO2011023847A1 (en) | 2009-08-27 | 2010-03-30 | Method for integrated circuit design verification in a verification environment |
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| Country | Link |
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| FI (1) | FI20095885A0 (en) |
| WO (1) | WO2011023847A1 (en) |
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| CN110688811A (en) * | 2019-09-12 | 2020-01-14 | 山东华芯半导体有限公司 | Method for accelerating design verification of SOC (system on chip) module with controllable random weight |
| CN114444419A (en) * | 2022-04-11 | 2022-05-06 | 奇捷科技(深圳)有限公司 | Method and equipment for generating new version circuit of chip and storage medium |
| CN116909935A (en) * | 2023-09-13 | 2023-10-20 | 沐曦集成电路(上海)有限公司 | Chip joint simulation method, device and medium based on single processing module interface |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113297073B (en) * | 2021-05-20 | 2022-07-29 | 山东云海国创云计算装备产业创新中心有限公司 | Verification method, device and equipment of algorithm module in chip and readable storage medium |
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| FI20095885A0 (en) | 2009-08-27 |
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