JP2007024513A - Logic estimation method for logic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic estimation method for a logic circuit which calculates an output value from an input value and an input value from an output value on a functional level to perform the estimation of faulty parts in a logic circuit and perform logic estimation by a design debug. <P>SOLUTION: The logic estimation method for a logic circuit comprises: an input step for inputting the logical value of input/output terminals of the logic circuit and function description design data; a DD conversion step for extracting function description design data corresponding to a designated logic circuit, converting it into a decision graph, and converting the logic circuit into a decision graph by dividing and hierarchizing into a combinational circuit part and a sequential circuit part; an estimation mode selection step for selecting which logic out of an expected value and an inverted logical estimated value will be calculated; a value estimation step for calculating logical values at a plurality of times for each decision graph divided and hierarchized by the selected calculation method and calculating the expected value and the inverted logical estimated value of the logic circuit; and an output step for outputting the expected value or the estimated value of the logic circuit and displaying its decision graph structure. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a logic circuit logic estimation method for calculating an output value from an input value and an input value from an output value at a functional level in order to estimate a fault location of the logic circuit or to perform logic estimation in design debugging. About.

  In the conventional logic circuit failure diagnosis, in order to estimate the failure location of the logic circuit, a logic circuit failure diagnosis program is installed in a computer having a general configuration and is necessary for a desired diagnosis from the input unit of the computer. Fault diagnosis was performed by entering commands.

  FIG. 1 shows a processing flow in a conventional logic circuit fault location estimation method. In the conventional failure diagnosis of a logic circuit, a function or logic simulation of the logic circuit is performed by assuming a failure in the logic circuit using a failure simulator. Then, the simulation result is compared with an expected value provided in advance, and a fault dictionary is created in which the assumed fault location and the test vector that detected the fault are associated with each other (step S101). Next, fail information is acquired from the actual test result of the logic circuit (step S102). When the fail information is acquired, the failure dictionary corresponding to the fail pin and the fail vector of the fail information is searched, respectively, and an assumed failure location is obtained (step S103). Then, prioritization is performed from a plurality of hypothetical failure candidates obtained, and the failure location is estimated (step S104).

  In addition, as a conventional method for identifying a fault location of a logic circuit, for example, an electron beam tester is used to estimate the fault location from the upper hierarchy of the logic circuit, observe internal signals at the hierarchy boundary, and identify the fault location as a lower rank of the logic circuit. There is a method of narrowing down to the hierarchy in order.

  In relation to the above-described technology, the following proposals have been made.

  In the “logic circuit failure location estimation method and logic circuit failure location estimation program” disclosed in Japanese Patent Application Laid-Open No. 2003-185705, a failure in a logic circuit is based on fail information obtained from a test result of the logic circuit. In the failure location estimation method of a logic circuit that estimates a location, a failure output port or a failure estimation output port based on failure information or failure propagation estimation information from description information in which the logic circuit is functionally described in a circuit block unit in a hardware description language A fail estimation circuit block having a circuit, and a decision graph for determining the operation for all conditions by displaying the data flow of the circuit description part of the fail estimation circuit block by the node and connection of the data processing unit, respectively, and creating a fail output port and The node corresponding to the fail estimation output port The failure estimation of each node is performed in the input direction by estimating the output of each node based on the failure vector and the expected value based on the failure vector, estimating the failure propagation path, and the failure propagation source node of this failure propagation path and the input port Based on the correspondence, information on nodes that do not correspond is registered as failure location estimation information, information on the corresponding input ports is registered as the fail propagation estimation information, and these processes are performed until all fail propagation source nodes no longer correspond to input ports. A failure location estimation method for a logic circuit that outputs a list of failure location estimation information has been proposed.

  Further, in “logic circuit failure diagnosis apparatus, failure diagnosis method and program thereof” disclosed in Japanese Patent Application Laid-Open No. 2004-309261, description information in which the structure or operation of a logic circuit is described in units of circuit blocks in a design language. From the state transition table created for each fail estimation circuit block having a fail estimation output port extracted by the fail extraction device, one output from a set of input nodes, operation nodes composed of operators, and a plurality of input values The selection node and output node for selecting values are connected to each of these nodes, and a decision graph is created to determine the operation for each node by displaying the data flow on the display means. Separate data system failures and control system failures As a result, it is possible to control the data system at the functional level by estimating the failure propagation path using the decision graph. Trouble diagnosis device for a logic circuit having the function of estimating the fault location of the system have been proposed. In this proposal and the proposal disclosed in Japanese Patent Application Laid-Open No. 2003-185705, the logic circuit is converted into a decision graph, and the expected value and estimated value of each node corresponding to the test pattern are compared and tracked at the functional level. Estimate the failure location. To calculate the estimated value, the input value is calculated while calculating the value of each node in the input direction starting from the output of the decision graph. Further, when debugging a designed circuit, a trace signal is traced while searching for a signal that causes a change in a certain signal.

  In addition, in the “Sequential Circuit Fault Location Estimation Method” disclosed in Japanese Patent Application Laid-Open No. 08-146093, all expected value information for all vectors of all latches in the semiconductor integrated circuit, and pass / fail information of the tester In the fault location estimation method of the sequential circuit, which uses the connection information of all circuits and divides the semiconductor integrated circuit into a latch and a combinational circuit to estimate the fault, an actual fail output pin or a latch input estimated to be a fail The combinational circuit is extracted from the line in the input direction until reaching the input pin or latch output of the semiconductor integrated circuit, and the output pin or latch of the semiconductor integrated circuit is further extracted from the extracted input of the combinational circuit. The first processing procedure for extracting the combinational circuit in the output direction until reaching the input, and connected to the output unit of the combinational circuit A second processing procedure for creating a data flow by checking whether or not the output of the latch affects any other latch, and a fault propagation value at the input boundary of the combinational circuit, a single fault propagation Confirmation, confirmation confirmation by simulation for selecting a signal line combination capable of simultaneous failure propagation by confirmation of the same signal line in the combination circuit in the previous stage, confirmation of activation of the branch signal, and confirmation of clock enable of the input boundary latch And the fourth processing procedure for extracting the subsequent circuit when the combinational circuit has not confirmed the extraction of the subsequent circuit until the actual output of the semiconductor integrated circuit, and the combinational circuit A fifth processing procedure for determining whether or not the fault propagation simulation using the fault estimation result at the input boundary matches the actual fail output; When it is determined in the fifth processing procedure that they match, a latch state estimation value table is created and each signal line in the combinational circuit is simulated using the obtained latch state estimation value table As a processing procedure for determining a fault propagation estimated value at the input boundary of the combination circuit at least for each fail vector, a sixth processing procedure for determining the presence or absence of a stuck-at fault based on the result and estimating the fault location in the combination circuit A sequential circuit fault estimation method for creating a fault estimation list is proposed.

  In “Sequential Circuit Fault Location Estimation Method” disclosed in Japanese Patent Application Laid-Open No. 08-146093, a combinational circuit that may propagate a fault to a fault output is dynamically extracted, and a logic state and Estimate the path where the fault propagates and go back to the input method to estimate the fault location. Here, the logic state of the combinational circuit is not only the logic value of one signal line, but all nodes in the circuit, that is, signal lines, gates, gate terminals, and input / output terminals are 0/1 / X (Don't Care). ) / Z (high impedance) / U (undefined).

JP 2003-185705 A JP 2004-309261 A Japanese Patent Application Laid-Open No. 08-146093

  In a conventional fault diagnosis method for a logic circuit using a fault simulator, a fault dictionary needs to be created in advance. Since the creation of a failure dictionary requires a lot of failure simulation time, the simulation time becomes enormous as the logic circuit becomes larger, and the failure dictionary file becomes very large. In particular, the failure model used in the failure simulation is generally a single stuck-at failure, so when a multiple failure such as a bridge failure actually occurs, the failure simulation cannot cope. However, if the fault simulation model is extended to multiple faults, it has been difficult to realize it from the viewpoint of the processing time of the fault simulation.

  In addition, the conventional failure diagnosis method for estimating the failure location of the logic circuit using the electron beam tester is an effective means for narrowing down while sequentially observing the failure location from the upper hierarchy to the lower hierarchy of the logic circuit. However, when the logic circuit becomes large and has a multilayer wiring structure, there is a problem that the potential of the lower layer wiring becomes unobservable.

  In addition, the conventional fault diagnosis method for estimating a fault location at the gate level is an effective means for estimating a fault location for each combinational circuit. Decrease in accuracy of the circuit and increase in processing time are problems.

  In conventional design debugging, when tracing a factor that changes a signal, the signal that causes the signal is searched while tracing the circuit diagram. Usually, there are a plurality of signals that cause the signal, and the signal that causes the signal and its value. There is a problem that it takes a lot of time to estimate.

  In addition, the conventional fault diagnosis method for estimating the fault location at the functional level can calculate the input value from the output value. However, if the processing time can be further reduced, it is also effective for a large-scale logic circuit. This is a failure diagnosis method.

  In the following, means for solving the problem will be described using reference numerals with parentheses used in [Best Mode for Carrying Out the Invention]. These symbols are added in order to clarify the correspondence between the description of [Claims] and the description of the best mode for carrying out the invention. ] Should not be used for interpretation of the technical scope of the invention described in the above.

  The logic circuit logic estimation method of the present invention is a logic circuit logic estimation method for calculating an input value and an output value of a logic circuit by logic estimation or inverse logic estimation. Input process for setting at least part of output value and input value and function description design data as input of input / output terminal of logic circuit, and function description design data corresponding to logic circuit set in input process A logic circuit is determined by a circuit extraction step to extract, a conversion step for converting function description design data into a decision graph, and a reconversion step for dividing and hierarchizing the decision graph into combinational circuit portions and sequential circuit portions. It corresponds to the output value based on the output value and input value of the DD conversion process that is converted to DD (Decision Diagram) and the logic circuit set in the input process. Selected in the estimation mode selection step and the estimation mode selection step for selecting which of the logic estimation for calculating the expected value and the inverse logic estimation for calculating the inverse logic estimation corresponding to the input value Based on the calculated calculation, for each decision graph divided and hierarchized by the reconversion process, an estimation process for calculating an expected value or an inverse logic estimation value at a plurality of times and a calculation result calculated by the estimation process are stored and managed. A value estimation step for calculating an expected value and an inverse logic estimate value of the logic circuit, and an output step for outputting the expected value of the logic circuit, the inverse logic estimate value, or the structure of the decision graph. .

  INDUSTRIAL APPLICABILITY According to the present invention, a logic circuit logic estimation method for calculating an output value from an input value and an input value from an output value at a functional level in order to estimate a failure location of the logic circuit or to perform logic estimation in design debugging Can be provided.

  According to the logic circuit logic estimation method of the present invention, a logic circuit is converted into a decision graph obtained by dividing and hierarchizing a sequential circuit block and a combinational circuit block. By calculating the value, it is possible to calculate the output value from the input value or the input value from the output value in a short time even for a logic circuit or sequential circuit described in a hierarchical manner. The expected value calculation for calculating the output value from the input value and the inverse logic estimation for calculating the input value from the output value according to the present application can be used for tracking the failure path in the failure location estimation, thereby estimating the failure location. Time saving is realized. Furthermore, in circuit debugging according to the present application, by setting a value to a certain signal and performing inverse logic estimation from that value, it is possible to calculate the value of an arbitrary signal in the input direction, and to easily trace the cause of the failure. .

  With reference to the accompanying drawings, the best mode for carrying out the logic estimation method of the logic circuit of the present invention will be described below.

  A logic circuit logic estimation method according to the present invention is a logic circuit logic estimation method for calculating an expected value and inverse logic of a logic circuit. (1) An input process and a logic circuit decision graph (DD: Decision Diagram) (2) DD conversion step and selecting which logic of expected value or inverse logic estimated value is calculated (3) Estimation mode selecting step, and expected value and inverse logic of logic circuit are calculated ( 4) A value estimation step and (5) an output step are provided.

(1) In the input process, input / output terminal logic values or function description design data obtained by simulation, testing and analysis of a logic circuit to be subjected to logic estimation are set as input / output values. In the input process, any value such as only an input value, only an output value, a part of output values, an output value and a part of input values, or an input value and a part of output values may be given. Here, the logical value is an expected value or an inverse logical estimated value. The function description design data describes the structure or operation of a logic circuit in a hardware description language such as Verilog-HDL or VHDL, C language, or the like.

(2) In the DD conversion step, the function description design data corresponding to the logic circuit specified in the input step is extracted by the circuit extraction step, the function description design data is converted into a decision graph by the conversion step, and the re-conversion step Thus, the decision graph is divided and hierarchized into a combinational circuit portion and a sequential circuit portion. In the conversion process of the DD conversion process, a state transition table having a plurality of states is created according to the processing sequence of the logic circuit based on the function description design data. If the logic circuits are described hierarchically based on the state transition table, the hierarchical circuit block is set as a module node. An input node that becomes an input, an input / output node that becomes an input at a certain time and an output at another time, an operation node composed of operators, and a selection node that selects one output value from a set of a plurality of input values By connecting the output nodes and the output nodes, a decision graph for displaying data flow and determining operations for all conditions is created. Thereby, a decision graph required for logic estimation can be created. Further, the re-conversion process of the DD conversion process replaces the decision graph indicated by the module node with the module node when the decision graph is hierarchized, and a flat decision graph structure (decision graph not represented hierarchically) ). Here, when the decision graph A is created using a general module node M, two decision graphs can be created. A decision graph A and a decision graph B representing the module node M. Although the logic circuit is represented by a decision graph A, a part of the configuration requirements of the decision graph A is hierarchically represented as a decision graph B. For this reason, in this application, the decision graph which is not expressed hierarchically is implement | achieved by replacing this decision graph B with the said module node.

  Next, the flat decision graph structure is separated into sequential circuit blocks and combinational circuit blocks. In the reconversion process of the DD conversion process, when the decision graph has a flat structure without being hierarchized, the decision graph is separated into a sequential circuit block and a combinational circuit block, and the sequential circuit block is converted into a module node. replace. At this time, the decision graph representing the module node is a decision graph representing the sequential circuit block.

(3) The estimation mode selection step determines whether to calculate an expected value calculation or an inverse logic estimation value calculation based on the input / output values of the logic circuit specified in the input step.

(4) The value estimation step is an estimation step for calculating a logical value at a plurality of times for each decision graph divided and hierarchized by the reconversion step by the calculation method selected in the estimation mode selection step (3). Then, the expected value and the inverse logic estimated value of the logic circuit are calculated by the estimated value managing step for holding and managing the calculation result. Here, the time may mean time (sec, nsec, psec), or may mean a cycle number in which a logic circuit operates. For example, there is a definition of a time at which a signal changes every unit time (cycle) in units of 1 nsec. In simulations and tests, management is performed using patterns (or vectors) as time units. In addition, although there are a plurality of input terminals of the logic circuit, in the input process, “0” or “1” is set in each terminal. For example, “0” and “1” are set as the first in each of the three input terminals. When a value “0” is set, one input pattern “010” is set. Next, when the values “1”, “1”, and “1” are set as the second, one input pattern “111” is set. In the test, tens of thousands of continuous patterns are set as input terminals. In this case, each pattern has the meaning of “time”.

  When the expected value calculation is selected in the estimation mode selection process, the estimation process of the value estimation process uses an input node, an operation node, a selection node, a module node, and an input / output node each time the state transitions using a decision graph And the expected value of the logic circuit is calculated by calculating the value of the output node. In the module node calculation, the expected value of the decision graph is calculated using the decision graph corresponding to the module node, and the expected value is set as the value of the module node. Thereby, the expected value of the logic circuit can be calculated. In the estimation process of the value estimation process, when inverse logic estimation is selected in the estimation mode selection process, using the decision graph, the transition node is traced back starting from the output node of the uppermost decision graph representing the logic circuit. The estimation of the values of the selection node, the operation node, the input / output node, the input node, and the module node is performed in the input direction, and in the estimation of the module node, the decision graph corresponding to the module node is estimated. If the separated decision graph or the hierarchical decision graph is a sequential circuit block, the value of the input node of the decision graph and the values of the input node and output node at the immediately preceding time are estimated, and the decision graph is In the case of a combinational circuit block, estimation of the current time and estimation of the immediately preceding time are performed separately, and the estimation result of both times is merged to estimate the input value of the logic circuit and the input / output value of the immediately preceding time. . Whether the expected value calculation or the inverse logic estimated value calculation is calculated in the value estimation step may be designated directly from the input step.

(5) In the output step, an expected value or an estimated value of the logic circuit is output, and a decision graph structure of the logic circuit is displayed.

  In the logic circuit logic estimation method of the present invention, by setting module nodes, a decision graph necessary for logic estimation can be created even for hierarchically described logic circuits. In addition, the decision graph structure is hierarchized and separated by the sequential circuit block and the combinational circuit block, and the current time and the previous time are estimated separately for the sequential circuit block, thereby reducing the amount of calculation at the time of inverse logic estimation. The processing time can be shortened. Thereby, the expected value and the inverse logic estimated value of the logic circuit can be calculated at the function level.

(Embodiment of the present invention)
FIG. 2 shows a schematic configuration of a logic circuit estimation apparatus for implementing the logic circuit logic estimation method of the present invention.

  A logic circuit logic estimation apparatus 10 for executing the logic circuit logic estimation method according to the present embodiment inputs an instruction for executing logic estimation of a logic circuit to be subjected to logic estimation. A CPU 40, a storage unit 70, an external data acquisition unit 50, and an output unit 30 for outputting a logic estimation result as necessary. The storage unit 70 preliminarily estimates the failure location of the logic circuit to be subjected to logic estimation, or performs logic estimation in design debugging, so that the input value from the input value or the input value from the output value at the functional level. The logic estimation program 70a for calculating is stored. Further, the external data acquisition unit 50 is connected to a test data storage device 100 for a logic circuit that records the destination data of the logic circuit to be subjected to logic estimation. The input unit 20, the CPU 40, the storage unit 70, the external data acquisition unit 50, and the output unit 30 are each connected by a bus line.

(Operational principle of the embodiment)
A logic circuit logic estimation method according to this embodiment will be described with reference to FIG. In the present embodiment, when an instruction to execute logic estimation of a logic circuit to be subjected to logic estimation is input from the input unit 20 of the logic circuit estimation device 10 of the logic circuit, the CPU 40 stores in the storage unit 70. The stored logic estimation program 70a is read and executed. Along with the execution of the logic estimation program 70a, the external data acquisition unit 50 acquires, from the logic circuit test data storage device 100, the destination data of the logic circuit to be subjected to logic estimation. Thereby, CPU40 starts the logic estimation of the logic circuit used as logic estimation object. As shown in FIG. 3, the logic estimation according to the present embodiment includes an input process (step S01), a DD conversion process (step S02) for converting a logic circuit into a decision graph, an expected value and an inverse logic estimate. An estimation mode selection step (step S03) for selecting which one of these is calculated, a value estimation step (step S04) for calculating an expected value and an inverse logic estimation value of the logic circuit, and an output step (step S05). ing. Hereinafter, each process will be described in detail.

  In the input step (step S01), the logic value of the input / output terminal of the logic circuit or the function description design data is set as the input / output value. Also, a logic circuit to be a logic estimation target is designated.

  The DD conversion step (step S02) includes a circuit extraction step for extracting function description design data corresponding to the logic circuit specified in the input step (step S01), a conversion step for converting the function description design data into a decision graph, A re-conversion step of dividing and hierarchizing the decision graph into a combinational circuit portion and a sequential circuit portion;

  In the estimation mode selection step (step S03), it is determined whether to calculate an expected value or an inverse logic estimation value based on the input / output values of the logic circuit specified in the input step (step S01).

  The value estimation step (step S04) is an estimation method for calculating logical values at a plurality of times for each decision graph divided and hierarchized by the re-conversion step by the calculation method selected in the estimation mode selection step (step S03). The expected value and the inverse logic estimated value of the logic circuit are calculated by the process and the estimated value managing process for holding and managing the calculation result.

  In the output step (step S05), the expected value or estimated value of the logic circuit is output, and the decision graph structure of the logic circuit is displayed.

  Next, the DD conversion process (step S02) in the present embodiment will be described with reference to FIGS.

  FIG. 4 is a Verilog-HDL description of the logic circuit: Circuit-A. FIG. 5 is a state transition table of Circuit-B, which is a sequential circuit block of Circuit-A. Circuit-B is a circuit that operates when a change in the signal DYN is detected. If DYN is 0, 1 is output to OUT, and if DYN is 1, 0 is output to OUT.

  First, the state transition table shown in FIG. 5 is created in accordance with the processing order of the Verilog-HDL description (see FIG. 4) which is function description design data. Circuit-A does not include a time transition in the Verilog-HDL description, so there is no need to create a state transition table. On the other hand, Circuit-B creates a state transition table according to the processing order because it includes a time transition in the Verilog-HDL description.

  As the first transition state, the event generation determination process of the always block is assigned to the state ST0. Here, the change in the signal DYN is expressed as @DYN. If there is a change in the value of DYN, temp becomes TRUE, and if there is no change, it becomes FALSE. Next, the process described in the always block is assigned to the state ST1. In the state ST1, a process for assigning the evaluation of the expression on the right side of the non-blocking substitution expression (OUT <= 1, OUT <= 0) to the temporary register: _reg1 is assigned. Next, a process of assigning the value held in the temporary register: _reg1 to the signal: OUT on the left side of the non-blocking assignment formula is assigned to the state ST2. In state ST0, if temp is TRUE, go to state ST1, and if temp is FALSE, go to state ST3. In the state ST1, when the process ends, the process goes to the state ST2. In the state ST2, when the process is completed, the process goes to the state ST3. In state ST3, go to ST0.

  Next, creation of decision graphs for Circuit-A and Circuit-B will be described. Circuit-A uses IN0, IN1, and IN2 as input ports as input nodes, and OT0 as an output port as output nodes. The bit operation AND (&), the bit operation OR (|) and the logical inversion (˜) of the bit operation are set as operation nodes. The signal: W00 is a variable to be substituted on the left side of the substitution formula, and is also an input to the circuit block Circuit-B, and therefore is set as an input / output node. I1 is set as a module node representing the circuit block Circuit-B. By connecting these nodes and displaying the data flow, FIG. 6 which is a decision graph of Circuit-A is created.

  Circuit-B sets DYN, which is an input port, as an input node. State variable _state and state numbers _st0, _st1, _st2, and _st3 are set as input nodes. Also, constants “0”, “1”, and _reg1, which are constants used in the evaluation of the expression on the right side of the conditional expression and the assignment expression, are set as input nodes. An event node “_evnt” for determining a change in signal is set as an input node. Output port OUT and state variable _state are set as output nodes. _Reg1, which is a variable assigned on the left side of the assignment expression, is set as an output node. In order to express the operation of the if-else syntax, an equal sign (=), NOT (!) of a logical operation, AND (∩) of a logical operation, and OR (∪) of a logical operation are set as operation nodes. OUT_a, state_a, and reg1_a corresponding to each of the output nodes OUT, _state, and _reg1 are set as selection nodes. The selection node is indicated by, for example, the ▽ symbol in FIG. The selection node described in the lower right of FIG. 7 outputs data to the output node “_reg1”. The output value is the value of the node “1” (= “1”) extending from above, or the value of the node “0” (= “0”). Of the two lines connected from the left of the selected node ▽, when the value of the node “∩” to which the upper one is connected is 1, the left one of the two lines extending from above is The value of the connected node “1” is selected. Of the two lines connected from the left of the selected node ▽, when the value of the node “∩” to which the lower one is connected is 1, the right of the two lines extending from the upper side The value of node “0” to which one is connected is selected. Thus, the connection connected to the left side of the selected node ▽ indicates the condition.

  As for the link of each node, first, the input node _state which is a state variable and the input nodes _st0, _st1, _st2 and _st3 which are state numbers are respectively linked by an operation node “=”. The output node STATE is linked as the output destination of the selected node state_a. The selection node state_a is linked with the input nodes _st0, _st1, _st2, and _st3, which are state numbers, as output values. Since the next state is ST1 when the condition temp is TRUE in the state ST0, the state result corresponding to the output value _st1 of the selected node state_a is “equal sign“ = ”linked to the input node _st0”. “The equal sign“ = ”” linked to DYN and _evnt is linked to the operation node “∩”, and the selected node state_a is linked as the output destination of the operation node “∩”. The next state is ST2 when the current state is ST1, and the selected node state_a is linked as the output destination of “equal sign“ = ”linked to input node_st1”. Since the next state is ST3 when the current state is ST0 and the condition temp is FALSE and when the current state is ST2, “equal sign“ = ”linked to DYN and _evnt” is changed to the operation node “!”. And the “equal sign“ = ”” linked with the input node_st0 is linked with the operation node “∩”. The operation node “∩” is linked with the operation node “∪” by “equal sign“ = ”linked to the input node_st2”, and the selection node state_a is linked as an output destination of the operation node “∪”. . The next state is ST0 when the current state is ST3, and the selected node state_a is linked as an output destination of “equal sign“ = ”linked to input node_st3”. The selection node reg_a is linked to the output node_reg1 as an output destination. Here, as a result of a state corresponding to “1” which is one of output values, “operation node“ = ”” linked to input node ST1 and “operation node linked to“ 0 ”from input node DYN” = “” Is linked with the operation node “∩”, and the operation node “∩” is linked with the selection node reg1_a. Further, as a result of the state corresponding to the output value “0”, “the operation node“ = ”” which links the input node DYN and “0” is linked by the operation node “!”, And the operation nodes “!” And “input node” are linked. The operation node “=” linked to ST1 is linked by the operation node “∩”, and the operation node “∩” is linked to the selection node reg1_a. The input node_reg1 is linked to the selection node OUT_a as an output value. The selection node OUT_a is linked to the output node OUT as an output destination. Here, as a state result corresponding to the output value _reg1, the equal sign “=” linked to the input node _st2 is linked to the selected node OUT_a. By connecting these nodes and displaying the data flow, FIG. 7 which is a decision graph of Circuit-B is created.

  Next, the reconversion process of the DD conversion process (step S02) in the present embodiment will be described with reference to FIGS. In the decision graph (DD1) shown in FIG. 8, the input nodes are IN0, IN1, IN2, IN3, and IN4, and the calculation result is output to the output node OT0 via the module node MD. FIG. 9 is a decision graph (DD2) of the module node MD. The calculation results of IN0 and IN1 of the decision graph DD1, the calculation result of IN2, the calculation results of IN3 and IN4, and OT0 are T0, T1, and T0 of the decision graph DD2, respectively. Corresponds to T2 and OUT.

  In the re-conversion step of the DD conversion step (step S02), the module node MD of the decision graph DD1 is replaced with the decision graph DD2 to obtain a flat decision graph (DD3) shown in FIG. Further, the decision graph DD3 is separated into a sequential circuit block having a transition state and a combinational circuit block not related to the transition state. The node on the input side of the node DYN of the decision graph DD3 is a combinational circuit. The decision graph is separated at the node DYN, and the decision graph DD4 of the combinational circuit block shown in FIG. 11 and the decision of the sequential circuit block shown in FIG. Separate into graph DD5. Further, the decision graph DD4 can be converted into the decision graph shown in FIG. 13 by using the module node MD1 expressing the decision graph DD5. Moreover, it can convert into the decision graph which expressed the input / output of the module node clearly shown in FIG. Thereby, in the decision graph, the sequential circuit block and the combinational circuit block can be expressed separately.

  Another embodiment of the reconversion process of the DD conversion process (step S02) will be described with reference to FIGS. In another embodiment of the DD reconversion step of the DD conversion step (step S02), when the decision graph is the flat decision graph (DD3) shown in FIG. 10, the decision graph DD3 is changed to the combinational circuit block shown in FIG. The decision graph DD4 and the decision graph DD5 of the sequential circuit block shown in FIG. A flat decision graph is a decision graph that is not represented hierarchically here. The decision graph DD4 can be converted into the decision graph shown in FIG. 13 using the module node MD1 representing the decision graph DD5. Moreover, it can convert into the decision graph which expressed the input / output of the module node clearly shown in FIG. Thereby, in the decision graph, the sequential circuit block and the combinational circuit block can be expressed separately.

  Next, the estimation mode selection step (step S03) in the present embodiment will be described. In the estimation mode selection step (step S03) according to the present embodiment, when all the input values of the logic circuit are already set and some or all of the output values are not set, an output value is calculated as a calculation method. Select the expected value calculation to calculate part or all of. Alternatively, when all output values are already set and a part or all of the input values are not set, an inverse logic calculation for calculating a part or all of the input values is selected as the calculation method. Further, when a part of the input value and a part of the output value are not set, an inverse logic calculation for calculating a part of the input value is selected as the calculation method. However, in the estimation mode selection step (step S03) in the present embodiment, it may be specified in the input step (step S01) which of expected value calculation and inverse logic estimation is calculated.

  Next, the value estimation process (step S04) according to the present embodiment will be described. First, the value estimation step (step S04) according to the present embodiment when expected value calculation is selected in the value estimation mode selection step (step S03) will be described with reference to FIG. 12 and FIG.

  The decision graph of the logic circuit is the decision graph (DD6) described hierarchically as shown in FIG. 14, and the decision graph representing the module node MD1 of the decision graph DD6 is the decision graph (DD5) shown in FIG. As inputs of the logic circuit, IN0 = 0, IN1 = 0, IN2 = 0, IN3 = 0, IN4 = 0 at the previous time, and IN0 = 0, IN1 = 0, IN2 = 0, IN3 = 1 at the current time. Assume that IN4 = 1. First, the value of each node is calculated for the uppermost decision graph DD6 representing the logic circuit. At the immediately preceding time, the values of the operation nodes “&”, “˜”, and “|” are calculated in the output direction in order, and IN0 = 0, IN1 = 0, IN2 = 0, IN3 = 0, IN4 = 0. Node W1 = 0. At the current time, IN0 = 0, IN1 = 0, IN2 = 0, IN3 = 1, IN4 = 1, so node W1 = 1. The input value of the module node MD1 is 0 at the immediately preceding time and 1 at the current time. The input of the module node MD1 corresponds to the input node DYN of the decision graph DD5.

  Next, for the decision graph DD5 expressed by the module node MD1, the value of each node is calculated in the output direction. The input node DYN of the decision graph DD5 is 0 at the immediately preceding time and 1 at the current time. Since the process of the decision graph DD5 starts from the transition state _st0, 0 representing the transition state _st0 is set in the input node _state. The operation node “=” (X10) linked to _evnt and DYN sets 1 when the value of DYN changes, and 0 when it does not change. Here, since DYN changes from 0 to 1, X10 becomes 1. Since the input node_state = 0, X13 = 1, X14 = 0, and X1 = 0. The values of the operation nodes that have not been set are sequentially estimated, and the operation nodes X2 = 1, X3 = 0, X5 = 0, and X6 = 0. Since the operation node X1 = 0, X2 = 1, and X3 = 0, the second input is selected in the selection node X4, and the output node_state becomes 1 meaning the transition state_st1. Since the operation nodes X5 = 0 and X6 = 0, no input is selected in the selection node X7, and the output node OT0 is not set. Since the calculation in the transition state_st0 is completed and the output node_state = 1, the process goes to the transition state_st1 next.

  In the transition state_st1, the input node_state = 1. Since the value of the input node DYN does not change, the current time value is 1. The value of the immediately preceding time is 1, which is the value of the previous transition state. Since there is no change in the value of DYN, the operation node X10 = 0. The values of the operation nodes are X1 = 0, X2 = 0, X3 = 1, X5 = 0, and X6 = 1, similarly to the estimation in the transition state_st0. Since the operation node X1 = 0, X2 = 0, and X3 = 1, the third input is selected in the selection node X4, and the output node_state becomes 2 which means the transition state_st2. Since the operation nodes X5 = 0 and X6 = 1, the second input is selected at the selection node X7, and the output node OT0 = 0. Since the calculation in the transition state_st1 is completed and the output node_state = 2, the process proceeds to the transition state_st2.

  In the transition state_st2, the input node_state = 2. Since the value of the input node DYN does not change, the current time value is 1. The value of the immediately preceding time is 1, which is the value of the previous transition state. Since there is no change in the value of DYN, the operation node X10 = 0. The value of the operation node is X1 = 1, X2 = 0, X3 = 0, X5 = 0, X6 = 0, as in the estimation in the transition state_st1. Since the operation nodes X1 = 1, X2 = 0, and X3 = 0, the first input is selected in the selection node X4, and the output node_state becomes 0 which means the transition state_st0. Since the operation nodes X5 = 0 and X6 = 0, no input is selected in the selection node X7, and the output node OT0 becomes 0 which is the value of the previous transition state. Since the calculation in the transition state_st2 is completed and the output node_state = 0, and the process returns to the first transition state, the process ends. When calculating the expected value at the next time, the value of the last transition state_st2 is set and the process is continued. Thereby, the process of the decision graph DD5 is completed, and then the process returns to the module node MD1 of the decision graph DD6 indicated by the decision graph DD5. In the decision graph DD6, the output node OT0 of the decision graph DD5 corresponds to the output of the module node MD1. Since the current time value of the output node OT0 of the decision graph DD5 is 0, the value of the output node OT0 of the decision graph DD6 is 0.

  As described above, in the value estimation step (step S04) according to the present embodiment, an expected value can be calculated even for a logic circuit described in a hierarchy by setting a module node.

  Next, the value estimation step (step S04) according to the present embodiment when inverse logic estimation is selected in the value estimation mode selection step (step S03) will be described with reference to FIG. 12 and FIG.

  The decision graph of the logic circuit in the value estimation step (step S04) is the decision graph (DD6) described hierarchically as shown in FIG. 14, and the decision graph representing the module node MD1 of the decision graph DD6 is shown in FIG. It is a decision graph (DD5). Assuming that the output of the current time of the logic circuit is OT0 = 1, the input of the current time and the input / output of the immediately preceding time are estimated. First, the value of each node is estimated starting from the output node OT0 of the decision graph DD6 in the uppermost layer while going back in the input direction. Since the current time value of the output node OT0 of the decision graph DD6 is 1, the current time value of the output of the module node MD1 is 1. Next, the decision graph DD5 expressed by the module node MD1 is estimated.

  In the estimation of the decision graph DD5, assuming that the next transition state is _st0, the value of the output node _state is set to “0” which means that the transition state is _st0. Since the current time value of the output of the module node MD1 of the decision graph DD6 is 1, the output node OT0 = 1 of the decision graph DD5 is set. Since the output node_state = 0, the first input _st0 is selected in the selection node X4. Since the first is selected, the operation nodes X1 = 1, X2 = 0, and X3 = 0. Since the operation node X1 = 1, the input node_state = 2. The operation nodes X13 = 0 and X14 = 0. Since the operation node X3 = 0, X8 = 0. Since X8 = 0, X2 = 0, and X13 = 0, X9 = x and X10 = x. Here, x means that both 0 and 1 are good. Since X10 = x, DYN = x, and the value of the previous transition state is also x. Since the operation node X14 = 0, X5 = 0 and X6 = 0. Since X5 = 0 and X6 = 0, no input is selected in the selection node X7, so the value of the output node OT0 in the previous transition state is 1. Since input node_state = 2, the transition state is traced back, and in the transition state traced back, output node_state = 2. Output node_state = 2 and the value of output node OT0 are set to 1. The input node DYN is x. Since the output node_state = 2, the operation node X4 selects the third input _st2. Since the third item is selected, the operation nodes X1 = 0, X2 = 0, and X3 = 1. Since the operation node X3 = 1, X8 and X14 are either “X8 = 1 and X14 = 1”, “X8 = 1 and X14 = 0”, or “X8 = 0 and X14 = 1”. Here, assuming that “X8 = 1 and X14 = 1”, X9 = 1 and X13 = 1. Since X13 = 1, the input node_state = 0 and X14 = 0. Since the value of X14 is inconsistent, it is not “X8 = 1 and X14 = 1”. Assuming that “X8 = 1 and X14 = 0”, X9 = 1, X13 = 1, and X10 = 0. Since X13 = 1, the input node_state = 0. Since the operation node X14 = 0, X5 = 0 and X6 = 0. Since X5 = 0 and X6 = 0, no input is selected in the selection node X7, so the value of the output node OT0 in the previous transition state is 1. X10 = 0 means that there is no change in the value of DYN, and DYN is “current time value = 0 or the value of the previous transition state = 0” or “current time value = 1 or the previous transition. The value of the state = 1 ”. Since input node_state = 0, which means an initial state, the transition state is traced back. As the estimated value of the decision graph DD5, the output node value in the final transition state is the output value at the current time, and the input node value in the initial transition state is the input value at the current time. In addition, the values of the input node and the output node in the transition state immediately before the initial transition state are set as the input value and output value of the immediately preceding time. That is, as the estimated values of the decision graph DD5, “the previous time value of DYN = 0, the current time value of DYN = 0, the immediately previous time value of OT0 = 1, the current time value of OT0 = 1” and “the previous time value of DYN” = 1, current time value of DYN = 1, immediately previous time value of OT0 = 1, current time value of OT0 = 1 ”.

  On the other hand, assuming that “X8 = 0 and X14 = 1”, the input node_state = 1 and X13 = 0. Since X8 = 0, X2 = 0, and X13 = 0, X9 = x and X10 = x. Since X10 = x, DYN = x, and the value of the previous transition state is also x. Next, the selected node X7 is estimated. In X7, “Nothing is selected”, “First input is selected”, or “Second input is selected”. Here, assuming that “nothing is selected”, X6 = 0 and X5 = 0. From X14 = 1, X6 = 0 to X11 = 0, X12 = 1. Further, X12 = 1 and X5 = 0, so that X12 = 0. Since the value of X12 is contradictory, it does not hold when X7 = “Nothing is selected”. Assuming that X7 is “the second input is selected”, the value of the input node “0” is output to OT0, which contradicts OT0 = 1. Therefore, assuming that X7 is “the first input is selected”, X5 = 1 and X6 = 0. Then, X11 = 0 and X12 = 1 are established. Since X12 = 1, DYN = 0. Since the value is selected by the selection node X7, the value of the output node OT0 in the previous transition state is x. Since input node_state = 1, the transition state is traced back, and in the transition state traced back, output node_state = 1.

  In the next transition state, first, output node_state = 1 and the value of output node OT0 are set to x. The input node DYN is 0. Since the output node_state = 1, the second input _st1 is selected at the selection node X4. Since the second input is selected at the selection node X4, X1 = 0, X2 = 1, and X3 = 0. From X3 = 0, X8 = 0 and X14 = 0. From X2 = 1, X10 = 1 and X13 = 1. From X13 = 1, the input node_state = 0. Since X10 = 1 and DYN = 0, the value of the transition state immediately before DYN is 1. From X14 = 0, X5 = 0 and X6 = 0. Since X5 = 0 and X6 = 0, no input is selected in the selection node X7, so the value of the output node OT0 in the previous transition state is x. Since input node_state = 0, which means an initial state, the transition state is traced back. As an estimated value of the decision graph DD5, “DYN immediately preceding time value = 1, DYN current time value = 0, OT0 immediately preceding time value = x, OT0 current time value = 1” is obtained.

  With the above processing, the estimation of the decision graph DD5 is completed. As the estimated values of the decision graph DD5, “the immediately preceding time value of DYN = 0, the current time value of DYN = 0, the immediately preceding time value of OT0 = 1, the current time value of OT0 = 1”, and the immediately preceding time value of DYN = 1. , DYN current time value = 1, OT0 immediately preceding time value = 1, OT0 current time value = 1, “DYN immediately preceding time value = 1, DYN current time value = 0, OT0 immediately preceding time value = x” , OT0 current time value = 1 ”.

  Next, the process returns to the decision graph DD6. As a result of the estimation of the decision graph DD5, the value of the module node MD1 is as follows: “input previous time value = 0, input current time value = 0, output previous time value = 1, output current time value = 1”, “input Immediately before time value = 1, input current time value = 1, output previous time value = 1, output current time value = 1, “input previous time value = 1, input current time value = 0, output The immediately preceding time value = x, the current output time value = 1 ”.

  In the estimation of the node on the input side from the module node MD1, first, the results of both times of the value of the decision graph DD5 which is the sequential circuit block are merged. For example, the estimated value of the circuit block is “input immediately preceding time value = 1, input current time value = 0, output immediately preceding time value = 1, output current time value = 1” and “input immediately preceding time value”. = 0, current input time value = 0, previous output time value = 1, current output time value = 1 ”, whether the previous input time value is 0 or 1 holds. Therefore, it can be merged with “input previous time value = x, input current time value = 0, output previous time value = 1, output current time value = 1”. In this embodiment, since merging is not possible, three types are estimated.

  Next, as input values of the module node MD1, nodes on the input side are estimated for the cases of 0 and 1 listed from the input values of the three estimation results of the decision graph DD5.

  When the input value of the module node MD1 is 0, the input / output node W1 = 0 and the operation node Y1 = 0. From Y1 = 0, Y2 = 0 and Y5 = 0. From Y5 = 0, “IN0 = 0 and IN1 = x” or “IN0 = 1 and IN1 = 0” is obtained, and there is no contradiction in the decision graph DD5. From Y2 = 0, “Y3 = 0 and Y4 = x” or “Y3 = 1 and Y4 = 0”. Assuming that “Y3 = 0 and Y4 = x”, IN2 = 1, IN3 = x, and IN4 = x are obtained, and both are consistent in the decision graph DD5. Assuming that “Y3 = 1 and Y4 = 0”, IN2 = 0. From Y4 = 0, “IN3 = 0 and IN4 = x” or “IN3 = 1 and IN4 = 0” is obtained, and both are consistent in the decision graph DD5. From the above, (IN0, IN1, IN2, IN3, IN4) = (0, x, 1, x, x), (0, x, 0, 0, x), (0, x, 0, 1, 0) , (1, 0, 1, x, x), (1, 0, 0, 0, x), and (1, 0, 0, 1, 0).

  When the input value of the module node MD1 is 1, the input / output node W1 = 1 and the operation node Y1 = 1. From Y1 = 1, (1, x) or (0, 1) can be obtained for (Y2, Y5). Assuming that (Y2, Y5) = (1, x), IN0 = x, IN1 = x, Y3 = 1, Y4 = 1. Y3 = 1 to IN2 = 0. From Y4 = 1, IN3 = 1 and IN4 = 1. Assuming that (Y2, Y5) = (0, 1), IN0 = 1 and IN1 = 1, and (Y3, Y4) becomes (0, x) or (1, 0). Assuming that (Y3, Y4) = (0, x), IN2 = 1, IN3 = x, IN4 = x. Assuming that (Y3, Y4) = (1, 0), IN2 = 0, and (IN3, IN4) becomes (0, x) or (1, 0). From the above, (IN0, IN1, IN2, IN3, IN4) = (x, x, 0, 1, 1), (1, 1, 1, x, x), (1, 1, 0, 0, x) , (1, 1, 0, 1, 0).

  When the value of the module node MD1 is “immediate input time value = 0, input current time value = 0, output previous time value = 1, output current time value = 1”, the input of MD1 as the previous time value The estimation result when the value is 0 is applied, and the estimation result when the input value of MD1 is 0 is applied as the current time value. 36 kinds of results are obtained which are combinations of 6 kinds of the previous time value and 6 kinds of the current time value.

  When the value of the module node MD1 is “input previous time value = 1, input current time value = 1, output previous time value = 1, output current time value = 1”, the input of MD1 as the previous time value The estimation result when the value is 1 is applied, and the estimation result when the input value of MD1 is 1 is applied as the current time value. Sixteen results, which are combinations of four ways of the immediately preceding time value and four ways of the current time value, are obtained.

  When the value of the module node MD1 is “input previous time value = 1, input current time value = 0, output previous time value = x, output current time value = 1”, the input of MD1 as the previous time value The estimation result when the value is 1 is applied, and the estimation result when the input value of MD1 is 0 is applied as the current time value. Twenty-four results, which are combinations of four types of the previous time value and six types of the current time value, are obtained. As described above, in the logic circuit expressed by the decision graph DD6, when the output at the current time is OT0 = 1, 76 combinations of the input value at the current time and the input / output value at the immediately preceding time are obtained. Is obtained.

  In this embodiment, by setting a module node in a decision graph, a decision graph necessary for logic estimation is created even for a logic circuit described in a hierarchy. In particular, the decision graph structure is hierarchized or separated into sequential circuit blocks and combinational circuit blocks. For the sequential circuit block, the current time and the immediately preceding time are estimated separately, thereby reducing the amount of calculation at the time of inverse logic estimation and reducing the processing time.

  As described above, according to the logic circuit logic estimation method of the present invention, a logic circuit is converted into a decision graph divided and hierarchized by sequential circuit blocks and combinational circuit blocks. For each decision graph, by calculating logical values at a plurality of times, even for logic circuits and sequential circuits described hierarchically, from input values to output values or output values in a short time Input values can be calculated. In particular, in designing a logic circuit, when the circuit does not operate as designed, it is necessary to investigate the cause and correct (debug) the design. In debugging, a signal that causes an operation different from the expected one is traced in the input direction while searching for a signal that causes the signal. However, if the circuit is chased in the input direction, the number of signal lines that must be chased increases, and a great deal of time is required to find the causal signal line. The expected value calculation for calculating the output value from the input value and the inverse logic estimation value calculation for calculating the input value from the output value according to the present application are performed at the functional level when designing the logic circuit or debugging as described above. The present invention can be applied to a failure diagnosis apparatus for estimation. Further, it can be applied to a logic simulator at a functional level and a program for realizing the logic simulator on a computer. As a result, a drastic reduction in the estimated time of the fault location in the logic circuit is realized.

It is a flowchart which shows the process sequence of the fault location estimation of the conventional logic circuit. It is a figure which shows schematic structure of the logic estimation apparatus of the logic circuit for enforcing the logic estimation method of the logic circuit of this invention. It is a flowchart which shows the process sequence of the logic estimation method of the logic circuit of this invention. It is an example of Verilog-HDL description of a logic circuit. It is a state transition table concerning an embodiment of the invention. It is the decision graph hierarchized concerning embodiment of this invention. It is the decision graph hierarchized concerning embodiment of this invention. It is the decision graph hierarchized concerning embodiment of this invention. It is the decision graph hierarchized concerning embodiment of this invention. It is a flat decision graph concerning embodiment of this invention. It is the separated decision graph concerning embodiment of this invention. It is the separated decision graph concerning embodiment of this invention. It is the decision graph hierarchized concerning embodiment of this invention. It is the decision graph hierarchized concerning embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Logic estimation apparatus 20 of a logic circuit ... Input part 30 ... Output part 40 ... CPU
50 ... External data acquisition unit 60 ... Bus line 70 ... Storage unit 70a ... Logic estimation program 100 ... Test data storage devices X1-X14, Y1-Y5 ... Node

Claims (10)

A logic circuit logic estimation method for calculating an input value and an output value of a logic circuit by logic estimation or inverse logic estimation,
An input step for setting at least part of the output value and the input value of the logic circuit to be subjected to logic estimation, and function description design data as an input of an input / output terminal of the logic circuit;
A circuit extraction step of extracting the function description design data corresponding to the logic circuit set in the input step; a conversion step of converting the function description design data into a decision graph; and A DD conversion step of converting the logic circuit into a decision diagram (DD) by a re-conversion step of dividing and hierarchizing the circuit portion;
Based on the output value and the input value of the logic circuit set in the input step, the logic estimation for calculating an expected value corresponding to the output value and an inverse logic estimation value corresponding to the input value are calculated. An estimation mode selection step for selecting which of the inverse logic estimations to calculate is calculated;
Based on the calculation selected in the estimation mode selection step, an estimation step for calculating the expected value or the inverse logic estimation value at a plurality of times for each decision graph divided and hierarchized by the reconversion step; A value estimation step of calculating the expected value and the inverse logic estimation value of the logic circuit by an estimated value management step of holding and managing the calculation result calculated by the estimation step;
A logic circuit logic estimation method comprising: an output step of outputting the expected value of the logic circuit, the inverse logic estimation value, or the structure of the decision graph. The logic estimation method for a logic circuit according to claim 1,
The conversion step of the DD conversion step uses the function description design data, creates a state transition table having a plurality of states according to the processing order of the logic circuit,
When the logic circuit is described in a hierarchy in the created state transition table, the hierarchical circuit block of the logic circuit is defined as a module node, the module node, an input node serving as an input, An input / output node that becomes an input at a specific time and becomes an output at a time different from the specific time, an operation node composed of operators, and a selection that selects one of a plurality of input value sets as an output A logic circuit logic estimation method for creating a decision graph indicating data flows corresponding to all operating conditions of the logic circuit by connecting nodes and output nodes respectively. The logic estimation method for a logic circuit according to claim 1 or 2,
In the re-conversion step of the DD conversion step, when the decision graph is hierarchized, the decision graph corresponding to the module node is replaced with the module node, and the decision graph is not hierarchized. A logic estimation method for a logic circuit having a flat decision graph structure and separating the flat decision graph structure into a sequential circuit block and a combinational circuit block. The logic estimation method for a logic circuit according to claim 1 or 2,
The re-conversion step of the DD conversion step separates the decision graph into a sequential circuit block and a combinational circuit block when the decision graph has a flat structure that is not hierarchized. A logic estimation method for a logic circuit, wherein the decision graph corresponding to the module node is changed to a decision graph corresponding to the sequential circuit block by replacing the sequential circuit block with the module node. In the logic estimation method of the logic circuit according to at least one of claims 1 to 4,
In the estimation step of the value estimation step, when the logic estimation for calculating the expected value is selected in the estimation mode selection step, each time the state of the logic circuit transitions based on the decision graph Calculating the expected value of the logic circuit by calculating values of the input node, the operation node, the selection node, the module node, the input / output node, and the output node;
In particular, in the calculation of the value of the module node, an expected value of the decision graph corresponding to the module node is calculated as a module node expected value, and a logic estimation method for a logic circuit using the expected module node value as the module node value . In the logic estimation method of the logic circuit according to at least one of claims 1 to 4,
In the estimation step of the value estimation step, when the inverse logic estimation for calculating the inverse logic estimation value is selected in the estimation mode selection step, the estimation step corresponding to the logic circuit is selected based on the decision graph. Starting from the output node of the decision graph in the upper layer, values of the selection node, the operation node, the input / output node, the input node, and the module node while tracing back the transition state of the logic circuit Calculating the inverse logic estimate of the logic circuit by calculating
In particular, in calculating the value of the module node, a module node decision graph corresponding to the module node is estimated,
When the module node determination graph is the sequential circuit block, the value of the input node of the module node determination graph at a plurality of arbitrary times, the value of the input node and the output node before the unit time of the arbitrary time, Are independently calculated, the calculated results are merged over each of the plurality of specific times, the value of the input node of the merged module node determination graph, the input node before the unit time of the arbitrary time, and A logic circuit logic estimation method for calculating the input value at an arbitrary time of the logic circuit and the input value and the output value before the unit time of the arbitrary time based on the value of the output node. In the logic estimation method of the logic circuit according to at least one of claims 1 to 6,
A logic circuit logic estimation method for setting which of the expected value and the inverse logic estimation value is calculated in the value estimation step by the input step. The logic estimation method for a logic circuit according to at least one of claims 1 to 7,
The function description design data is a logic circuit logic estimation method in which the structure or operation of the logic circuit is described in a hardware description language such as Verilog-HDL or VHDL and C language.   A computer-readable logic circuit logic estimation program for realizing the logic circuit logic estimation method according to any one of claims 1 to 8. A logic estimation device for calculating an input value and an output value of a logic circuit by logic estimation or inverse logic estimation,
An external data acquisition unit for acquiring the input value, the output value, and the function description design data of the input / output terminals of the logic circuit to be subjected to logic estimation;
CPU,
An input step for setting at least a part of the output value and the input value acquired via the external data acquisition unit and the function description design data as an input of the input / output terminal of the logic circuit;
A circuit extraction step of extracting the function description design data corresponding to the logic circuit set in the input step; a conversion step of converting the function description design data into a decision graph; and A DD conversion step of converting the logic circuit into a decision diagram (DD) by a re-conversion step of dividing and hierarchizing the circuit portion;
Based on the output value and the input value of the logic circuit set in the input step, the logic estimation for calculating an expected value corresponding to the output value and an inverse logic estimation value corresponding to the input value are calculated. An estimation mode selection step for selecting which of the inverse logic estimations to calculate is calculated;
Based on the calculation selected in the estimation mode selection step, an estimation step for calculating the expected value or the inverse logic estimation value at a plurality of times for each decision graph divided and hierarchized by the reconversion step; A value estimation step of calculating the expected value and the inverse logic estimation value of the logic circuit by an estimated value management step of holding and managing the calculation result calculated by the estimation step;
A storage unit for preliminarily storing a logic estimation program for executing the expected value of the logic circuit, the inverse logic estimated value, or an output step of outputting the structure of the decision graph; and the expected value of the logic circuit; A logic estimation apparatus comprising: an output unit that outputs the inverse logic estimation value or the structure of the decision graph.

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