CN110688811A

CN110688811A - Method for accelerating design verification of SOC (system on chip) module with controllable random weight

Info

Publication number: CN110688811A
Application number: CN201910864165.6A
Authority: CN
Inventors: 石易明; 刘大铕; 李风志; 戴绍新; 姚香君; 李文军
Original assignee: Shandong Sinochip Semiconductors Co Ltd
Current assignee: Shandong Sinochip Semiconductors Co Ltd
Priority date: 2019-09-12
Filing date: 2019-09-12
Publication date: 2020-01-14
Anticipated expiration: 2039-09-12
Also published as: CN110688811B

Abstract

The invention discloses a method for accelerating design verification of an SOC (system on chip) module with controllable random weight, which is characterized in that an OR (arithmetic) module is added between a digital logic module and an FIFO (first in first out) module, one input end of the OR module is connected with the output end of the FIFO, the other input end of the OR module is connected with a random 0/1 generation module, or the output end of the OR module is connected with the digital logic module, during simulation verification, a full signal output by the FIFO and a numerical value generated by a 0/1 generation module are subjected to OR operation, then the result of the OR operation is transmitted to the digital logic module, and the digital logic module generates a corresponding push signal pressed into the FIFO according to the input result. The method can use short simulation to collide corner errors in the digital logic, thereby accelerating the process of module design verification; and the random part can control the random weight more accurately, so that the simulation effect has better controllability.

Description

Method for accelerating design verification of SOC (system on chip) module with controllable random weight

Technical Field

The invention relates to a method for accelerating design verification of an SOC module with controllable random weight, and belongs to the technical field of digital circuit function simulation verification.

Background

At present, the digital front-end research and development of an SOC (system on chip) basically realizes a modular development process, and common modules such as an interface controller module, an algorithm hardware acceleration module, a protocol conversion bridge module and the like basically use an FIFO in the internal design of a digital circuit stage.

As a first-in first-out circuit unit, there are usually an input "push" signal (push for short) and an output "full" indication signal (full for short) at the data entry end of the FIFO, and various timing sequences and combinational logics in the design of the module are usually directly or indirectly associated with the logics of the two signals; especially, when the application scenario of the module is complicated, the logic for generating the push signal may be complicated, so that logic errors are often generated in the design verification process. In the traditional method, a random regression verification platform is generally built outside a module, and variables such as clock frequency which are random and related to transmission bandwidths at two ends outside the module are indirectly transmitted to FIFO in the module in the platform, so that the bandwidth of an input end of the FIFO is large, the condition that the FIFO is filled deeply gradually occurs after a period of time, and at the moment, full signals can change in height and can collide with potential logic errors in the current module along with a large amount of regression simulation; this process takes too long and the randomness of the "full" signal transitions conducted through the random module external signal to the internally manufactured FIFO output is poor.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a method for accelerating the design verification of an SOC module with controllable random weight, which can collide corner errors in digital logic by short simulation, thereby accelerating the process of the design verification of the module; and the random part can control the random weight more accurately, so that the simulation effect has better controllability.

In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a method for accelerating design verification of an SOC module with controllable random weight comprises the following steps: s01), adding an OR operation module between the digital logic module and the FIFO, or connecting one input end of the operation module with the output end of the FIFO, and connecting the other input end with a random 0/1 generation module, or connecting the output end of the operation module with the digital logic module, wherein the digital logic module, the FIFO, or operation module and the 0/1 generation module are all positioned in the SOC module to be designed, and the digital logic module and the FIFO are integrated into a circuit, or the operation module and the 0/1 generation module are not integrated into a circuit; s02), during simulation verification, the full signal output by the FIFO and the value generated by the 0/1 generation module are subjected to OR operation, then the result of the OR operation is transmitted to the digital logic module, the digital logic module generates a corresponding push signal pressed into the FIFO according to the input OR operation result, and when the relation between the push signal and the OR operation result is that the OR operation result is high, the push signal cannot be high.

Further, whether the or operation module and the 0/1 generation module are enabled or not is confirmed in a macro definition mode, when the macro is defined, the or operation module and the 0/1 generation module are enabled, the digital logic module collects FIFO output and random 0/1 or a result after operation, when the macro is not defined, the or operation module and the 0/1 generation module are not enabled, and the digital logic module directly collects FIFO output.

Further, the macro is defined only at the time of simulation verification.

Further, the or operation module and the 0/1 generation module are simulation structures compiled from the systemverilog language.

Further, the 0/1 generation module generates controllable weights of 0 or 1, and the method for controlling the weights of 0 or 1 comprises the following steps: s11), setting a dynamic array, wherein the size of the dynamic array is set as the simulated beat number, and then all elements of the dynamic array are equal to 0; s12), determining a weight with a random of 1, and then calculating a beat number with a random of 1 according to formula 1, where formula 1 is: random 1 valid beat = simulated beat × random 1 weight; s13), sequentially filling the following elements with 1 from the first element of the dynamic array; s14), judging whether the filling times is equal to the random number of beats which is 1 effective, if not, repeating the step S13 to continue filling, if so, calling the function of the systemverilog array to disorder all elements; s15), judging whether the last element of the array is equal to 1, if not, continuing to use the function of the systemverilog array to scramble all the elements, if yes, inputting the generated random number into the or operation module.

Further, the 0/1 generation module generates controllable weights of 0 or 1, and the method for controlling the weights of 0 or 1 comprises the following steps: s21), setting a dynamic array, wherein the size of the dynamic array is set as the simulated beat number, and then all elements of the dynamic array are equal to 0; s22), determining a weight with a random of 1, and then calculating a beat number valid with a random of 1 according to formula 1, where formula 1 is: valid beat number valid = 1 at random = simulated beat number × weight of 1 at random; s23), randomly generating a position index pn of an element equal to 1 in the dynamic array; s24), filling 1 in the array element of the corresponding position pointed by the position index pn; s25), judging whether the number of times of filling 1 is equal to the number of beats which is effective and random, if not, continuing to fill 1 at the position of the random new element until valid elements in the array are equal to 1, and if so, inputting the generated random number into the OR operation module.

Further, in step S23, a key randc of the system variance log is used to ensure an array element position index that is not repeated in each random.

The invention has the beneficial effects that: the invention replaces the sampled full signal from the full actually output of the FIFO into the full actually output of the FIFO and the result after the random value logic or operation, thereby realizing the situation that the full signal sampled actually has high-low alternation to the maximum extent, and further using short simulation to collide the corner error in the digital logic, thereby accelerating the process of module design verification; and the random part can control the random weight more accurately, so that the simulation effect has better controllability.

In the traditional module design simulation process, only one logic condition of a determined circuit can be obtained by one-time simulation, for example, the depth of FIFO is a fixed value; from the point of view of sampling full signals by a digital logic module, the method is equivalent to the step of replacing a fixed-depth FIFO in the module with an FIFO with the depth changing randomly and dynamically, so that the logic situation of multiple traditional simulations can be run out in one simulation, the logic details in the design can be debugged more quickly, and the efficiency of design verification is improved.

Drawings

FIG. 1 is a schematic diagram of a present SOC module design verification;

FIG. 2 is a schematic diagram of SOC module design verification according to the present invention;

FIG. 3 is a schematic diagram of a waveform after adding a random;

FIG. 4 is a flowchart of randomly generating 0 or 1 in example 1;

fig. 5 is a flowchart of randomly generating 0 or 1 in example 2.

Detailed Description

The invention is further described with reference to the following figures and specific embodiments.

Example 1

In the design process of the SOC module, the FIFO is usually used as a common circuit unit for each module to call, as shown in fig. 1, the outermost box represents the SOC module, the long rectangle on the right side in the box represents the FIFO, which is a first-in first-out buffer circuit unit, and one end of the FIFO enters data and the other end outputs data. FIG. 1 simplifies this by showing push and full signals into one end of the data (left end of the rectangle), which are used as input signals into the FIFO, and a full signal which is used as an output signal to reflect whether the entire depth of the FIFO is full or not in real time, and if the output of the output data end of the FIFO is slow or not but the input end is continuously pushing data, the FIFO will become full gradually; the signal omission associated with the right-hand output data of the rectangle is not shown.

The left box represents digital logic for generating push and full signal sampling, the full signal is sampled in real time, if the push signal is full, the push signal cannot be high, and when the push signal is high when the full signal is not high depends on the data input condition of the whole SOC module (outer box).

In the design verification process of the SOC module, the main purpose is to fully simulate the interaction between the FIFO and other logic inside the module (left box in fig. 1) in different input/output scenarios, wherein an important point is to make full signals sampled by the left box alternate high and low to the greatest extent; the design logic problem of the part illustrated by the left box in the limit case cannot be hit if the sampled full signal is not always high or is rarely high, and is generally considered to be insufficient verification simulation;

the traditional method is that the data input and output bandwidth outside a module (outer layer square box) is adjusted, and the FIFO and the module are indirectly conducted through logic, so that a scene that the FIFO enters the end (left end in the figure) to rapidly push data and the FIFO outputs the end (right end) to slowly or basically not output data is manufactured, and the full signal is in a high-low alternating condition; this takes a long time, especially when the FIFO depth is large, even if the FIFO in and out rate difference is large, it takes a long simulation time to make full high, and even if a large number of simulations can hit most of the logic scenes in a long enough time, it is inefficient.

In view of the above situation, the present embodiment discloses a method for accelerating design verification of an SOC module with controllable random weight, including the following steps: s01), as shown in fig. 2, adding an or operation module between the digital logic module and the FIFO, wherein one input end of the or operation module is connected with the output end of the FIFO, the other input end is connected with a random 0/1 generation module, the output end of the or operation module is connected with the digital logic module, the FIFO or operation module and the 0/1 generation module are all located inside the SOC module to be designed, and the digital logic module and the FIFO are integrated into a circuit, or the operation module and the 0/1 generation module are not integrated into a circuit; s02), during simulation verification, the full signal output by the FIFO and the value generated by the 0/1 generation module are subjected to OR operation, then the result of the OR operation is transmitted to the digital logic module, the digital logic module generates a corresponding push signal pressed into the FIFO according to the input OR operation result, and when the relation between the push signal and the OR operation result is that the OR operation result is high, the push signal cannot be high.

A logical or is characterized in that the logical or post-output result is 1 when either of the two quantities is 1, and 0 only when both quantities are 0; that is, when the full signal output by the FIFO is 1, i.e., the FIFO is indeed full, the logical or result is 1 regardless of the newly added random value; therefore, when the FIFO is truly full, full signals sampled by the digital logic of the part of the left square block, namely the output of the OR gate, are ensured to be full, and the original functions of the part are not influenced by newly added logic; conversely, when the full signal output by the FIFO is 0, that is, the FIFO is not full, the random value is what the full signal of the part of the digital logic sample on the left side box is, that is, what the output of the OR gate is; this achieves that full sampled is always high when the FIFO is really full and that it is possible to sample high when the FIFO is not full, i.e. increasing the chance that full is high.

Fig. 1 is a general design diagram of FIFO in a module, all parts of which are synthesizable. An important difference of the improved part of fig. 2 is that the newly added part, in particular the random number part, is an uncompensable structure. The main innovation point of the invention is to embed the non-synthesizable simulation structure in the synthesizable circuit module, wherein the synthesizable circuit module refers to a digital logic module and a FIFO, and the simulation structure controlled by the macro definition non-synthesizable circuit refers to an OR operation module and an 0/1 generation module, wherein the 0/1 generation module is non-synthesizable.

The OR operation module and the 0 and 1 generation modules are only used for function simulation, whether the OR operation module and the 0/1 generation module are started or not is confirmed in a macro definition mode for use in simulation, the macro is defined only in simulation verification, the OR operation module and the 0/1 generation module are started, the digital logic module collects FIFO output and random 0/1 or a result after operation, and when the macro is not defined, the OR operation module and the 0/1 generation module are not started, and the digital logic module directly collects FIFO output.

In this embodiment, a simulation structure of an or operation module is implemented using a systemverilog language, that is, a process of performing or operation on FIFO output and random 0/1 is specifically a program including:

`ifdef TEST_TURBO

.bp_mst_wr_cmd_full (mst_wr_cmd_full | bp_mst_wr_cmd_rand ),

`else

.bp_mst_wr_cmd_full (mst_wr_cmd_full ),

`endif

.bp_mst_wr_cmd_push (bp_mst_wr_cmd_push ),

in the above procedure, bp _ mst _ wr _ cmd _ full represents the signal sampled by the digital logic module in fig. 1 and fig. 2, mst _ wr _ cmd _ full represents the "full" signal output by the FIFO, bp _ mst _ wr _ cmd _ full _ rand represents the random 0,1 signals; the line below the else represents the case where the two sides of fig. 1 are directly connected, and the line above the else represents the case of fig. 2, i.e. the digital logic block samples "the result of logical or of the full signal and the random 0,1 value output by the FIFO".

When TEST _ TURBO in the above procedure is defined, the connection case of fig. 2 is implemented (for simulation only), and when not defined, the connection case of fig. 1 is implemented (all can be synthesized into a circuit).

The embodiment uses the simulation structure of the systemverilog language random 0/1 generation module, which is specifically a section of the following program:

`ifdef TEST_TURBO

initial

begin

forever

begin

@(posedge bp_clk) bp_mst_wr_cmd_full_rand=$urandom_range(0,1);

end

`endif

the codes are parts which can not be synthesized into circuits, are embedded in the modules and are controlled by the same macro definition in an OR operation program; the above procedure gives an example of a simple generation of random 0,1, and the randomness of this signal can be controlled more finely, such as controlling the respective weights of random 0 and 1;

the specific effect after randomization is shown in fig. 3.

Bp _ mst _ wr _ cmd _ full in fig. 3 represents the actually sampled signals of the left boxes in fig. 1 and fig. 2, mst _ wr _ cmd _ full represents the "full" signal of the actual output of the FIFO, bp _ mst _ wr _ cmd _ full _ rand represents the random 0,1 signal, and the last one is the push signal of the last row in fig. 3;

as can be seen from fig. 3, the "full" signal (the second signal in the figure) actually output by the FIFO is high for only one beat, but after the or operation with random 0,1 (the third signal in fig. 3), the first signal (representing the signal actually sampled by the left-side box in fig. 1 and fig. 2) in fig. 3 is generated, and it can be seen that the high-low transition of this signal is significantly more than that of the second signal in fig. 3, and according to the rule of "actually sampled full signal, if full, the push signal cannot be high", the lowermost push signal in fig. 3 is divided into a plurality of single beats by a greater number of significant transitions of bp _ mst _ wr _ cmd _ full (actually sampled signal), and the logic waveform at a plurality of times of "full" can be simulated;

therefore, the situation that signals actually sampled by the left side boxes in the figures 1 and 2 are alternated in high and low to the maximum extent is realized, so that the design logic problem of the part indicated by the left side box when the limit situation is collided is realized, the full verification simulation is realized, and the corner logic problem in the module design is modified.

As shown in fig. 4, the 0/1 generation module generates controllable weights of 0 or 1, and the method for controlling the weights of 0 or 1 includes the following steps: s11), setting a dynamic array, wherein the size of the dynamic array is set as the simulated beat number, and then all elements of the dynamic array are equal to 0; s12), determining a weight with a random of 1, and then calculating a beat number with a random of 1 according to formula 1, where formula 1 is: random 1 valid beat = simulated beat × random 1 weight; s13), sequentially filling the following elements with 1 from the first element of the dynamic array; s14), judging whether the filling times is equal to the random number of beats which is 1 effective, if not, repeating the step S13 to continue filling, if so, calling the function of the systemVerilog array to disorder all elements; s15), judging whether the last element of the array is equal to 1, if not, continuing to use the function of the systemvverilog array to scramble all the elements, if yes, inputting the generated random number into the or operation module.

Example 2

As shown in fig. 5, the 0/1 generation module generates controllable weights of 0 or 1, and the method for controlling the weights of 0 or 1 includes the following steps: s21), setting a dynamic array, wherein the size of the dynamic array is set as the simulated beat number, and then all elements of the dynamic array are equal to 0; s22), determining a weight with a random of 1, and then calculating a beat number valid with a random of 1 according to formula 1, where formula 1 is: valid beat number valid = 1 at random = simulated beat number × weight of 1 at random; s23), randomly generating the position index pn of the element equal to 1 in the dynamic array, and ensuring the position index of the array element which is not repeated in each random by using the keyword randc of the systemVerilog; s24), filling 1 in the array element of the corresponding position pointed by the position index pn; s25), judging whether the number of times of filling 1 is equal to the number of beats which is effective and random, if not, continuing to fill 1 at the position of the random new element until valid elements in the array are equal to 1, and if so, inputting the generated random number into the OR operation module.

The rest is the same as in example 1, and will not be described again here.

The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.

Claims

1. A method for accelerating design verification of an SOC module with controllable random weight is characterized by comprising the following steps: the method comprises the following steps: s01), adding an OR operation module between the digital logic module and the FIFO, or connecting one input end of the operation module with the output end of the FIFO, and connecting the other input end with a random 0/1 generation module, or connecting the output end of the operation module with the digital logic module, wherein the digital logic module, the FIFO, or operation module and the 0/1 generation module are all positioned in the SOC module to be designed, and the digital logic module and the FIFO are integrated into a circuit, or the operation module and the 0/1 generation module are not integrated into a circuit; s02), during simulation verification, the full signal output by the FIFO and the value generated by the 0/1 generation module are subjected to OR operation, then the result of the OR operation is transmitted to the digital logic module, the digital logic module generates a corresponding push signal pressed into the FIFO according to the input OR operation result, and when the relation between the push signal and the OR operation result is that the OR operation result is high, the push signal cannot be high.

2. The method for accelerated verification of a SOC module design with controllable random weights as claimed in claim 1, wherein: whether the OR operation module and the 0/1 generation module are enabled or not is confirmed in a macro definition mode, when the macro is defined, the OR operation module and the 0/1 generation module are enabled, the digital logic module collects FIFO output and random 0/1 or operated results, when the macro is not defined, the OR operation module and the 0/1 generation module are not enabled, and the digital logic module directly collects FIFO output.

3. The method for accelerated verification of a SOC module design with controllable random weights as claimed in claim 2, wherein: the macro is defined only at the time of simulation verification.

4. The method for accelerated verification of a SOC module design with controllable random weights as claimed in claim 1, wherein: the or operation module and 0/1 generation module are simulation structures compiled from the systemverilog language.

5. The method for accelerated verification of a SOC module design with controllable random weights as claimed in claim 1, wherein: 0/1 the generating module generates controllable weights of 0 or 1, the method for controlling the weights of 0 or 1 includes the following steps: s11), setting a dynamic array, wherein the size of the dynamic array is set as the simulated beat number, and then all elements of the dynamic array are equal to 0; s12), determining a weight with a random of 1, and then calculating a beat number with a random of 1 according to formula 1, where formula 1 is: random 1 valid beat = simulated beat × random 1 weight; s13), sequentially filling the following elements with 1 from the first element of the dynamic array; s14), judging whether the filling times is equal to the random number of beats which is 1 effective, if not, repeating the step S13 to continue filling, if so, calling the function of the systemverilog array to disorder all elements; s15), judging whether the last element of the array is equal to 1, if not, continuing to use the function of the systemverilog array to scramble all the elements, if yes, inputting the generated random number into the or operation module.

6. The method for accelerated verification of a SOC module design with controllable random weights as claimed in claim 1, wherein: 0/1 the generating module generates controllable weights of 0 or 1, the method for controlling the weights of 0 or 1 includes the following steps: s21), setting a dynamic array, wherein the size of the dynamic array is set as the simulated beat number, and then all elements of the dynamic array are equal to 0; s22), determining a weight with a random of 1, and then calculating a beat number valid with a random of 1 according to formula 1, where formula 1 is: valid beat number valid = 1 at random = simulated beat number × weight of 1 at random; s23), randomly generating a position index pn of an element equal to 1 in the dynamic array; s24), filling 1 in the array element of the corresponding position pointed by the position index pn; s25), judging whether the number of times of filling 1 is equal to the number of beats which is effective and random, if not, continuing to fill 1 at the position of the random new element until valid elements in the array are equal to 1, and if so, inputting the generated random number into the OR operation module.

7. The method for accelerated verification of a SOC module design with controllable random weights as claimed in claim 6, wherein: in step S23, a key of the system variance log is used to ensure that the array element position index is not repeated in each random.