JPH05151295A - Device and method for judging test pattern - Google Patents

Abstract

PURPOSE:To prevent the generation of detection leakage in a logical bug existing in a logical circuit part whose function is not inspected by indicating a logical circuit part which is not activated by a set test pattern at the time of inspecting the logical circuit. CONSTITUTION:A logical description analyzing means 11 analyzes logical description 15 and obtains logical operation overall route information 16. A pass activating pattern forming means 12 forms an input signal pattern for activating each route based upon the information 16 as a temporary test pattern 17. A contradiction generation signal retrieving means 13 retrieves a signal generating contradiction in a set point in the pattern 17 and a route not activated due to the contradiction and forms a test pattern 18 and unactivated pass information 19. An unactivated pass relation signal output means 14 mutually colaltes th information 19, 16 and outputs a signal on the route not activated by the formed test pattern 18 as an unactivated pass list 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern judging device and method for evaluating the quality of a test pattern used when verifying a logic circuit.

[0002]

2. Description of the Related Art A test pattern for verifying the logic consistency of a logic circuit analyzes a logic description composed of an artificially created logic expression, etc. It is created by the procedure of obtaining each path and sequentially setting the values of all input signals so that it is possible to observe what kind of result the change in the value of the input signal brings to the output signal for each path. .. Making the change in the value of the input signal observable on the output signal is called activation hereafter, but using the activation pattern (that is, the pattern in which the input signal affects the output signal). By verifying the logic circuit, it is possible to verify the logic bug existing on the path that is the activation target. Also,
If there is an input signal that is referenced at multiple points and the values that should be set for this signal are inconsistent in the process of activating a route, the pattern that activates the route that is the target of activation is activated. Create a test pattern that does not include
I was verifying the logic circuit.

[0003]

In the above-mentioned conventional technique, even if there is a route that is not activated by the test pattern created based on the logic description, it cannot be recognized that such a route exists, and the activation is not performed. There was a situation where we overlooked a logic bug that could exist in the logic circuit part corresponding to the route that was not converted.

Therefore, according to the present invention, at the time of verifying a logic circuit, the logic circuit portion which is not activated by the set test pattern is specified so that a logic bug existing in the logic circuit portion whose function has not been verified is not detected. A test pattern determining apparatus and method capable of preventing the same.

[0005]

A test pattern judging device as a first solving means of the present invention for solving the above-mentioned problem is to analyze a logic function operation in a logic description for logic circuit design to analyze all input signals. To a corresponding output signal, the logic description analysis means for creating the logic behavior all-route information, and the change of the value of the input signal in each path based on the logic behavior all-route information is the change at the output signal stage. The path activation pattern creating means for creating a temporary test pattern of the signal pattern to be set for all input signals and the test pattern set for the input signal by the path activation pattern creating means are sequentially determined. When there is a contradiction in the value to be set for the input signal referenced from multiple logical condition locations, it is activated by the contradiction. Inconsistency occurrence signal search means for creating inactive path information related to the path for which the abandonment of the path is absent, and the inactive path information and the signal value set to the input signal based on the logical operation all path information are inconsistent. It is characterized in that it is constituted by an inactive path related signal output means for outputting as a non-active path list the signal names on the path for which abandonment is made.

A test pattern judging device as a second solving means of the present invention for solving the above-mentioned problems is a logical description analyzing means, a path activation pattern creating means, a contradiction signal searching means, and An inactive state is displayed on the logic description for logic circuit design, where a portion corresponding to a path for which activation is abandoned due to a contradiction exists in the value set in the input signal based on the active path information and the entire logical operation path information. And a non-active path related description display means for outputting a logical description list.

A test pattern judging method as a third means for solving the above problems according to the present invention is an information processing apparatus comprising an external storage device, an information display device, an output device, an input device and a central processing unit. In the test pattern determination method, the logic function operation in the logic description for logic circuit design input to the information processing apparatus is analyzed to create logic operation all-path information which is a path from all input signals to corresponding output signals. And a temporary test pattern of signal patterns to be set for all input signals so that a change in the value of the input signal in each path can be observed as a change in the output signal stage based on the logic description analysis step To sequentially determine the test pattern to be set to the input signal by the path activation pattern creating step and the path activation pattern creating means. Search whether there is a contradiction in the value to be set for the input signal referenced from the number of logical condition locations, and create inactive path information for the route for which activation is abandoned due to the contradiction. The signal name on the path for which activation has been abandoned is unresolved due to the contradiction signal search step and the signal value set to the input signal based on the inactive path information and the logical operation all-routes information being inconsistent. An inactive path related signal output step of outputting as an active path list, and outputting an inactive logic description list in which a portion corresponding to a path for which activation is abandoned is displayed on the logic description for logic circuit design as necessary. It is characterized by including.

A test pattern determination method as a fourth solving means of the present invention for solving the above-mentioned problems is a logical description analyzing step, a path activation pattern creating step, a contradiction signal searching step, and An inactive state is displayed on the logic description for logic circuit design, where a portion corresponding to a path for which activation is abandoned due to a contradiction exists in the value set in the input signal based on the active path information and the entire logical operation path information. And an inactive path related description display step of outputting a logical description list.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration block diagram of a first embodiment of the present invention.

The logic description analyzing means 11 analyzes the logic description 15 which describes the logical operation of the circuit, and analyzes all the logical operation paths from the input signal to the final output signal based on the logic description 15. Created as the route information 16. The path activation pattern creating means 12 picks up each of the paths in the logical operation all-routes information 16 one by one, and sequentially sets the values of all the input signals so that changes in the input signals of the routes can be observed on the output signals. Then, the values of all the input signals necessary to activate each path are created as the temporary test pattern 17. The contradiction occurrence signal search means 13 makes all inputs for each path to be activated in the temporary test pattern 17, whether or not there is a contradiction in the value of the input signal required for activating the path. The signal is inspected, and the test pattern 18 that does not include the pattern that activates the route is created, and at the same time, the information of the route that is not activated by the test pattern 18 is created as the inactive path information 19. Then, the inactive path-related signal output means 14 collates the inactive path information 19 with the logical operation all-routes information 16, recognizes all the input signals existing on the paths that are not activated by the test pattern 18, and detects the inactive paths. The list 110 is output.

Next, the processing procedure for the main parts common to the first and second embodiments will be described below with reference to the flowchart of FIG. The step 21 analyzes the logic description 15 and finds all paths from each input signal to the output signal in the logic description 15. This is to detect a logical bug on each path by creating a pattern in which a change in the value of each input signal can be observed through each path to observe the change in the output signal. In the next step 22, a test pattern in which the value of the input signal that activates each path is set is created. Here, the value of each input signal is set by sequentially following the operation in the logical description so that the change of the input signal of the path taken as the activation target can be observed on the output signal. At this time, if one input signal affects a plurality of locations, the values that should be set for such an input signal may differ. But here, by tracing each logical operation,
Create a pattern in which all values that should be set for a signal are stored as is.

In step 23, it is judged whether or not the process for creating the test pattern, which is obtained by activating the route, is performed for all the routes on the logic description 15, and the activation pattern is created for all the routes. If not completed, go to step 22,
If the test pattern creation is completed, the process moves to step 24. In step 24, in order to activate each path, there are a plurality of values taken by the input signal values obtained by tracing the respective logic operations, and a search for a signal in which these several values are inconsistent is performed for each path. Do about. Step 25 judges whether or not there is an input signal whose values set for activating the path are inconsistent, and if there is, it proceeds to step 26,
In other cases, the test pattern is a combination of values assuming the settings. This determines that all the routes can be activated, and the process is completed.

In step 26, the path that was the target of activation when the value of the input signal is inconsistent is determined.
Step 27 extracts all the signals on the path which were the targets of activation when the values of the input signals were inconsistent. The signal name extracted here does not create a test pattern that activates the route that was the target of activation when a contradiction occurs, so the route that is not activated by the test pattern, that is, the logical function is not verified. As a signal name indicating a part. It is used as information for presenting the unverified portion of the logic circuit in each of the first and second embodiments.

FIG. 3 is a flow chart of the information of a concrete example for explaining the operation of the first embodiment in more detail. In FIG. 3, the logic description 15 is a logic description created at the time of logic design of the circuit, and the logic expression “K = F1 (D? A * B: B + C)” in the logic description 15 is the signal D.
When the value of signal is "1", the values of signal K are signal A and signal B
Function F1 indicating that when the value of the signal D becomes “0”, the value of the signal K becomes equal to the result of the logical sum of the signals B and C. It is a description. Therefore, in this logic description, the input signals are A, B, C, D and the output signals are K.

First, the logical description analyzing means 11 analyzes the logical description 15 and checks all paths on the logical description. That is, the logical expression “K = F1 (D? A *
B: B + C) ”, a path in which a change in the value of the signal A propagates to the output signal K through the operation of the logical product“ * ”is extracted as the path 1, and the path 1 in the logical operation total path information 16 is similarly extracted.
To route 5 are extracted. In the table, "+" indicates a logical sum, and "-" indicates that a value is directly propagated without performing a logical operation.

The path activation pattern creating means 12 is
Each path in the logical operation all-path information 16 is picked up one by one, and the values of all input signals are sequentially set so that the path is activated, and the temporary test pattern 17 is created. First, the pathway 1 is activated. The activation means that the value P of the input signal A can be observed in the output signal K (see the temporary test pattern 17 in FIG. 3). That is, the condition that the change of the signal A directly affects the value of the output signal K is created as a setting pattern. Therefore, in order that the value of the signal A can be observed on the signal K, at least the value of the logical product of the signal A and the signal B needs to be propagated to the signal K. To this end, the function F1
Considering the operation of, the value of the signal D for controlling the branching condition needs to be "1". Further, since the value of the signal A appears in the result of the logical product of the signal A and the signal B substituted for the signal K, the value of the signal B becomes “1”. Separately, when the value of the signal D takes "1", the value of the logical sum of the signals B and C does not affect the signal K. Therefore, as the analysis result from the logical sum side, the signal It can be seen that both B and C can be any value "X". As described above, the path 1 is activated when all the obtained conditions for each signal are satisfied. Hereinafter, similarly, the pattern creation processing for activation is also performed for the paths 2 to 5, and the temporary test pattern 17 is completed as a combination of input signals for activating each path. In addition, temporary test pattern 1
In FIG. 7, 1 / X of the signal B means that the value of the signal B may be “1” or “X”.

Next, the contradiction signal search means 13 searches the temporary test pattern 17 to see if there is a contradiction in the signal conditions for activation set for each signal, and a contradiction occurs. In this case, the test pattern 18 in a form in which the pattern for activating this pathway is excluded from the temporary test pattern 17 is created. At the same time, the inactive path information 19 indicating the signal name in which the contradiction has occurred and the path for which activation has failed is listed. That is, first, the provisional test pattern 17 is referred to for each path, and only patterns having signals for which a plurality of values are set are picked up. Here, the signal B is applicable, and the pattern set to activate the paths 1, 4, and 5 is the target of the search. First, in the pattern for activating the path 1, the value "1" is taken for the signal B and the arbitrary value "X" is taken. Two conditions are set.
However, since the value "1" is included in the arbitrary value "X", these two conditions are consistent. Therefore, as one of the test patterns for activating the path 1, the signals A, B,
Patterns in which C and D take P, 1, 0 and 1 respectively are created in the test pattern 18. Similarly, in the pattern for activating the path 4, since the condition that the value of the signal B includes “0” in the value “X” is not contradictory, one of the test patterns for activating the path 4 is used. , The signal A,
Patterns in which B, C, and D take 0, 0, P, and 0 are fixed in the test pattern 18. Finally, regarding the pattern for activating the path 5, since two contradictory conditions are set, that is, the value "1" is taken for the signal B and the value "0" is taken, the path 5 is set. The pattern to be activated is not created in the test pattern 18, and “5 (B)” in the inactive path information 19 is created as information on the signal name in which the contradiction has occurred and the path for which activation failed.

The inactive path related signal output means 14
Compares the inactive path information 19 with the logical operation all-routes information 16 and creates a signal name on a path that is not activated by the test pattern 18 as an inactive path list 110. That is, the path not activated by "5 (B)" in the inactive path information 19 is the path 5, and the signals forming the path 5 from the logical operation all-routes information 16 are the signal K and the signal D. Represents all signal names present on the path that are not activated by the test pattern 18 "
K, D "is output as an inactive path list.

FIG. 4 shows a block diagram of the configuration of the second embodiment. The input information, the output information, and the functions of the logic description analysis unit 11, the path activation pattern creation unit 12, and the contradiction signal search unit 13 are the same as those in the first embodiment. Also, the logical description 15 and the logical operation all-routes information 1
6, the temporary test pattern 17, the test pattern 18, and the inactive path information 19 are all the same as those shown in FIG. 1, which is a configuration block diagram of the first embodiment.

The inactive path related description display means 44 collates the inactive path information 19 with the logical operation all-routes information 16, recognizes all the signal names existing on the routes not activated by the test pattern 18, and recognizes these signals. The location where the signal is described in the logic description 15 is searched, and the logic description in the state where the mark is added to the corresponding position is output as the inactive logic description list 410.

FIG. 5 is a flow chart of information showing the operation of the second embodiment. Each data of the logical description 15, the logical operation all-routes information 16, the tentative test pattern 53, the test pattern 17, and the inactive path information 19 is the logical description analysis means 11, the path activation pattern creating means 12, and the contradiction occurrence signal searching means 13. The process of being processed through is the same as that shown in FIG. 3, which is a flow chart of information showing the operation of the first embodiment.

The inactive path related signal output means 44 collates the inactive path information 19, the logical operation all-routes information 16 and the logical description 15, and puts the signal name on the path which is not activated by the test pattern 18 on the logical description. An inactive logic description list 410, which is the logic description in the specified state, is created.
That is, the path not activated by "5 (B)" in the inactive path information 19 is the path 5, and the signals constituting the path 5 from the all logical operation path information 16 are the signal K and the signal D. Recognizing that there is such a signal, the location where these signals are described in the logic description is searched, and a mark "*" is added next to the corresponding signal symbol in the logic description "K * = F1.
(D *? A * B: B + C) ”as inactive logic description list 4
Output as 10. In addition, the signal on the path which is not activated can be clearly indicated by "*" beside the signal symbol, and can also be displayed by reversing display and blinking of the signal symbol portion.

[0023]

As described above, according to the present invention, by presenting the information of the logic circuit portion corresponding to the path on the logic description which is not activated by the created test pattern, the present invention exists in the unverified portion in the logic circuit. This has the effect of preventing omission of detection of possible logic bugs.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is an information flow chart showing a processing procedure of a main part common to the first and second embodiments of the present invention.

FIG. 3 is a configuration block diagram in the first embodiment of the present invention.

FIG. 4 is a configuration block diagram of a second embodiment of the present invention.

FIG. 5 is an information flow chart showing the operation of the second embodiment of the present invention.

[Explanation of symbols]

 11 logic description analysis means 12 path activation pattern creation means 13 contradiction signal search means 14 inactive path related signal output means 15 logic description 16 logical operation all-route information 17 temporary test pattern 18 test pattern 19 inactive path information 110 inactive Path list 21, 22, 24, 25, 26, 27 Step 44 Inactive path related description display means 410 Inactive logical description list

Claims (4)

[Claims] 1. A logic description analysis means for analyzing logic function behavior on a logic description for logic circuit design to create logic behavior all-route information which is a route from all input signals to corresponding output signals, and the logic. A path activation pattern creating means for creating a temporary test pattern of a signal pattern to be set for all input signals so that a change in the value of the input signal in each path can be observed as a change in the output signal stage based on the operation all-path information. And whether or not there is a contradiction in the value to be set for the input signal referenced from a plurality of logical condition points when sequentially determining the test pattern to be set to the input signal by the path activation pattern creating means. Contradiction signal search means for searching and creating inactive path information regarding a route for which activation is abandoned due to occurrence of contradiction, and the inactive path information By the signal value to be set to the input signal based on the serial logic operation all route information is inconsistent,
A test pattern determination device comprising: an inactive path related signal output means for outputting, as an inactive path list, signal names on a path for which activation is abandoned. 2. The logic description analyzing means, the path activation pattern creating means, the contradiction occurrence signal searching means, and the value set in the input signal based on the inactive path information and the logical operation all-routes information. And a path corresponding to the path for which activation is abandoned due to the existence of the active path related description display means for outputting an inactive logic description list displayed on the logic description for logic circuit design. Test pattern determination device. 3. A test pattern determination method for an information processing device comprising an external storage device, an information display device, an output device, an input device and a central processing unit, wherein a logic circuit design logic description input to the information processing device is used. A logical description analysis step of analyzing the logical function operation of the above to create logical operation all-path information which is a path from all input signals to respective corresponding output signals, and an input signal in each path based on the logical operation all-path information A path activation pattern creating step of creating a temporary test pattern of a signal pattern to be set for all input signals so that a change in the value of can be observed as a change in the output signal stage; and the input signal by the path activation pattern creating means. When sequentially determining the test pattern to be set to, the values that should be set for input signals referenced from multiple logical condition locations are inconsistent. Whether there is a contradiction, and a contradiction occurrence signal search step for creating inactive path information regarding a path for which activation has been abandoned due to an inconsistency, and based on the inactive path information and the logical operation all-route information Due to inconsistent signal values set for input signals,
And a step of outputting an inactive path-related signal for outputting a signal name on a path for which activation is abandoned as an inactive path list. 4. The logic description analyzing step, the path activation pattern creating step, the contradiction occurrence signal searching step, the contradiction in a value set in an input signal based on the inactive path information and the logical operation all-routes information. Is present, the location corresponding to the path for which activation is abandoned is displayed on the logic description for logic circuit design, and an inactive path related description display step of outputting an inactive logic description list is included. Test pattern judgment method.