JP2000155156A - Failure-diagnostic device of semiconductor integrated device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relatively quickly extract a suspected failed part by creating the correspondence table of failure detection time and detected failure parts, comparing the table with information from a tester, storing the suspected failure information, and narrowing the suspected failure. SOLUTION: A semiconductor integrated circuit is inspected by a tester, and a failed part that does not match an expectation value is stored in a failed part storage means 101. Failure simulation is made with a test pattern used for inspection, and the correspondence table among the failed part, failure detection time, and external pins is created by a correspondence table generation means 102 and is stored in a correspondence table storage means 103. The details of the correspondence table are compared with each failed part of the failed part storage means 101 by a correspondence table retrieval means 104, and all corresponding failures are extracted as initial suspected failures and are stored in an initial suspected failure storage means 105. A failed part narrow down means 106 gives a test pattern that is used by an inspection to the initial suspected failure, narrows down the suspected failure by failure simulation, and displays the result on a final suspected failure display means 107.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault diagnosis apparatus for extracting a suspected fault inside a semiconductor integrated circuit from a test result of the semiconductor integrated circuit.

[0002]

2. Description of the Related Art A manufactured semiconductor circuit is discriminated into a non-defective product and a non-defective product by inspection with a tester, and the cause of the defective chip is analyzed to improve the manufacturing process. To help. Such an analysis is generally called a failure analysis.

[0003] In the failure analysis, a tester performs a failure diagnosis to extract a suspected fault location inside a circuit that is defective on a circuit netlist for a product determined to be defective by a tester. Identify the physical suspected fault location in the circuit by comparing the location with the layout pattern, directly observe the signal waveform of the internal node with an electron beam tester, and obtain the signal waveform of the internal node obtained in advance by simulation Identify the physical failure position by comparing with the last, and finally confirm the state of the physical defect based on the image observed by the scanning electron microscope to estimate the cause of the manufacturing failure Go through the steps in order.

Conventionally, a failure diagnosis is performed by assuming a certain failure model, a complete failure dictionary is created, and a failure location is diagnosed.

FIG. 7 is a schematic diagram showing the configuration of a conventional semiconductor integrated circuit failure diagnosis apparatus. As shown in FIG. 7, the conventional failure diagnosis device for a semiconductor integrated circuit includes a failure location storage unit 701, a failure dictionary generation unit 702, a failure dictionary storage unit 703, a failure dictionary search unit 704, and a suspected failure display unit 705. You.

Hereinafter, each function of the above configuration will be described. First, as a result of inspecting a target semiconductor integrated circuit (hereinafter simply referred to as a “circuit”) with a tester, a fail point in the tester in which an output signal of the circuit does not match an expected value when no failure exists is failed. Location storage means 701
Remember by

On the other hand, a failure simulation for checking whether each of the assumed faults in the circuit can be detected using the test pattern used in the inspection is executed, and if the assumed faults exist, a failure result is obtained. The failure dictionary generation unit 702 creates a failure dictionary indicating what combination is used, and stores the created failure dictionary in the failure dictionary storage unit 703.

[0008] The failure dictionary search means 704 searches the failure dictionary stored in the failure dictionary storage means 703 for a description of the combination of fail locations stored in the failure location storage means 701, and finds a combination of matching fail locations. The corresponding fault is displayed by the suspected fault display means 705.

The detailed operation of the fault diagnosis apparatus for a semiconductor integrated circuit configured as described above will be described. Here, it is assumed that the test patterns shown in (Table 1) are used to check whether a single stuck-at fault exists in the semiconductor integrated circuit shown in FIG.

[0010]

[Table 1]

In FIG. 6, reference numerals 10 to 13 denote external input signal lines, reference numerals 20 and 21 denote external output signal lines, and reference numerals a to i denote signal lines assuming a single stuck-at fault.

First, for a logic circuit model corresponding to a target semiconductor integrated circuit, faults are defined for all signal lines in the logic circuit, and the presence or absence of a fault in the target circuit is checked. The test pattern and the expected value when there is no fault are generated by the pattern generating means 1 and output to the simulation target fault list. The contents of the simulation target failure list are not changed during the subsequent failure simulation. Then, the failure simulation is performed in time sequence by the failure simulation means using the test pattern used for the inspection.

In each cycle, every fault included in the list of faults to be simulated is set in the logic circuit, a test pattern is input, and a normal value and the influence of the fault are propagated. When the time at which the output from the circuit is observed at the observation point set at the terminal of the logic circuit arrives, it is detected at that observation point by comparison with the normal state at that time obtained by the failure simulation. A list of possible failures is determined and output as detected failure information.

As a result of performing a failure simulation on the circuit of FIG. 6 using the test pattern of (Table 1), the detected failure at each external output terminal at each time is as shown in (Table 2). .

[0015]

[Table 2]

"Detection fault at output 20" in Table 2
"/" In the description in each column of "Detection failure at output 21"
The left side indicates a signal line, and the right side number indicates a failure of the signal line. "1" indicates a stuck-at-1 fault, and "0" indicates a stuck-at-0 fault. Failure dictionary generating means 702 based on detected failure information
Thus, for each assumed internal fault location,
A failure dictionary indicating the relationship between the time at which detection is possible and the name of the observation point at the external output terminal is created.
3 is stored.

When a failure dictionary is created from (Table 2), it becomes as shown in (Table 3).

[0018]

[Table 3]

For example, when there is a stuck-at-0 fault on the signal line a, when the test is performed using the test pattern shown in (Table 1),
This corresponds to the output pin 20 failing at time 4 and the output pin 20 failing at time 5.

A test is performed by applying an input pattern from a tester to the semiconductor integrated circuit, a signal arriving at each output terminal is observed, the tester test result is compared with an expected value created in advance by simulation, and the actual test is performed. The time at which the mismatch between the signal value and the expected value occurs, and information on the external output terminal name are taken into the failure diagnosis device by the fail point storage means 701. By using the failure dictionary search unit 704 to search the failure dictionary from the received fail information, a failure location that may actually exist is determined, and the suspected failure display unit 705 outputs a list of suspected failures. .

[0021]

However, in the conventional fault diagnosis apparatus, in order to accurately narrow down the suspected fault location to the minimum, all faults that may propagate to each observation point throughout the entire pattern are considered. Information on the location and the detection time must be registered in the failure dictionary. Therefore, the execution time of the failure simulation, which always assumes failures in all signal lines in the circuit, the time required to create and search for the failure dictionary, and the storage area of the failure dictionary become enormous as the circuit becomes larger. This has been an obstacle in performing failure diagnosis of large-scale circuits.

Even if a complete failure dictionary can be created for a certain failure model, if there is a failure that does not match the operation of the assumed failure model, the failure dictionary is searched and no corresponding failure is found. was there.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problem and to provide a failure diagnosis apparatus for a semiconductor integrated circuit that can easily extract a suspected failure location on a netlist in a relatively short time.

[0024]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a logic for extracting a possible fault location in a circuit from a test result of the logic circuit and a fault propagation result of a fault simulation after the test of the logic circuit. A failure diagnosis device for a circuit, which, at the same time as test pattern generation, generates a correspondence table of failure detection times, external pins and detected failure locations, and compares information extracted from a tester data log with the contents of the correspondence table. , A correspondence table search device for extracting a fault that may have been detected at a failed portion, a suspected fault storage device for storing information on a suspected fault that is currently a candidate, and a maximum number of suspected faults for completing narrowing down End condition input device for designating a normal state and a assumed one or more fault states when a certain pattern is given In using the fault simulation apparatus for determining a fault to be detected at the output of the simulating circuit operation, performing a logical operation of a plurality of suspected fault set. As a result, it is possible to significantly reduce the time required to extract the suspected fault location on the netlist.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a configuration of a failure diagnosis device for a semiconductor integrated circuit according to the first embodiment of the present invention. As shown in FIG.
1. Correspondence table generation means 102, correspondence table storage means 103, correspondence table search means 104, initial suspected fault storage means 105, fault location narrowing down means 106, final suspected fault display means 10
7 is comprised.

First, as a result of inspecting a target semiconductor integrated circuit with a tester, a fail point in the tester in which the output signal of the circuit does not match the expected value when no failure exists is stored by the fail point storage means 101. .

On the other hand, a failure simulation is performed to check whether or not a target fault in the circuit can be detected using the test pattern used in the inspection, and the fault location in the circuit and each fault are first determined. A correspondence table between the detected time and the external pin is generated by the correspondence table generation means 102, and the created correspondence table is stored in the correspondence table storage means 103. The individual fail locations stored in the fail location storage means 101 are compared with the contents of the correspondence table stored in the correspondence table storage means 103 by the correspondence table search means 104, and all the corresponding faults in the correspondence table are determined to be the initial suspected faults. Extracted as
Initial suspected fault storage means 105 stores information on the initial suspected fault.

The fault location narrowing means 106 provides the test pattern used in the inspection for the initial suspected fault, sets an expected value only for the failed location in the tester, performs a fault simulation, and narrows down the suspected fault. And outputs a fault that has affected many failed locations as a final suspected fault.

The final suspected fault, which is the result of diagnosis by the fault location narrowing down means, is displayed by the final suspected fault display means 107.

The operation of the semiconductor integrated circuit fault diagnostic apparatus according to the first embodiment configured as described above will be described. Here, it is assumed that the test patterns shown in (Table 1) are used to check whether a single stuck-at fault exists in the semiconductor integrated circuit shown in FIG. FIG. 3 is a flowchart showing a processing procedure in the failure location narrowing means according to the first embodiment of the present invention.

Step 301 is a process in which the initial suspected fault extracted by the correspondence table searching means is used as an element of a suspected fault set, and the fail point stored in the fail point storing means is used as a target fail point.

Step 302 sets a fault included in the current set of suspected faults and continues the fault simulation,
This is a process of interrupting the simulation at the earliest fail point among the unprocessed fail points and obtaining a detected failure set.

Step 303 is a process for determining whether or not the detected failure set is an empty set. Step 304
Is a process for setting the detected fault set to a new suspected fault set. Step 305 is a process in which the elements of the suspected fault set are not changed. Step 306 is processing to determine whether or not processing has been completed for all target fail points.

Next, a specific example of failure diagnosis will be described. A failure simulation was performed on the circuit of FIG. 6 by using the test patterns shown in (Table 1) and deleting the failure from the target failures of the subsequent failure simulations when the failure was first detected at the external output terminal of the circuit. As a result, the fault detected at each external output terminal at each time is as shown in (Table 4).

[0036]

[Table 4]

If a correspondence table between the fault location in the circuit, the time at which each fault is first detected, and the external pin is created from (Table 4), the table becomes as shown in (Table 5), and the fault dictionary in (Table 3) Requires less storage capacity than

[0038]

[Table 5]

Next, when the tester failed using the input pattern shown in (Table 1) with respect to the circuit shown in FIG. 6, the test 21 failed at the output 21 at time 3, the output 20 at time 4, and the output at time 5 20, output 2 at time 6
Assume that it was 1. When the initial suspected fault is extracted from the fail information by the correspondence table search means, a / 0, c /
0, d / 0 and g / 1.

Next, these initial suspected faults are narrowed down by fault location narrowing means. For the circuit of FIG. 6, the output 21 at time 3, the output 20 at time 4, and the output 2 at time 5 using the pattern of (Table 1).
An expected value is set only at four points of the output 21 at 0 and time 6, and a failure simulation is performed for the initial suspected failure.

When a set of detected faults is obtained from the output 21 at the time 3, d / 0 and g / 1 are obtained. These are set as new suspected fault sets, and the simulation is continued until time 4. When a set of detected faults is obtained from the output 20 at time 4, the set becomes an empty set. Therefore, the elements of the suspected fault set are not changed, the suspected fault set remains d / 0, g / 1, and the simulation is continued until time 5. When a set of detected faults is obtained from the output 20 at time 5, the set becomes an empty set. Therefore, the elements of the suspected fault set are not changed, and the suspected fault set is d.
/ 0, g / 1, and the simulation is continued until time 6. When a set of detected faults is obtained from the output 21 at the time 6, the result is g / 1. Since all the target fail points have been processed, the final suspected fault, which is the result of diagnosis by the fault location narrowing down means, is g / 1, which is displayed by the suspected fault display means.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described.
An embodiment will be described.

The fault diagnostic apparatus for a semiconductor integrated circuit according to the second embodiment has the same configuration as that of the fault diagnostic apparatus for a semiconductor integrated circuit according to the first embodiment except for a fault location narrowing means. In the process of narrowing down the set of suspected faults detected at each fail location by sequential AND operation, the failure location narrowing means in the embodiment of the present invention separately stores the fail locations that make the operation result an empty set, and stores the other fail locations. The set of suspected faults is narrowed down to only the location,
The narrowing down is performed again only on the fail points stored separately.

Next, the operation of the failure diagnosis apparatus for a semiconductor integrated circuit according to the second embodiment will be described. Here, it is assumed that the test patterns shown in (Table 1) are used to check whether a single stuck-at fault exists in the semiconductor integrated circuit shown in FIG.

FIG. 4 is a flowchart showing a processing procedure in the fault location narrowing means according to the second embodiment of the present invention.

Step 401 is a process in which the initial suspected fault extracted by the correspondence table searching means is used as an element of the suspected fault set, and the fail point stored in the fail point storing means is used as the target fail point. Step 402 is a process of setting a fault included in the current set of suspected faults, continuing the fault simulation, suspending the simulation at the earliest fail point among the unprocessed fail points, and obtaining a detected fault set. . Step 403 is a process of determining whether or not the detected failure set is an empty set.
Step 404 is a process of setting the detected fault set as a new suspected fault set. Step 405 is a process of recording the failed set as an empty set as another set of fail points without changing the elements of the suspected fault set. Step 40
6 is a process for determining whether or not all target fail locations have been processed. Step 407 is processing to determine whether or not there is a separately stored fail point.
Step 408 is a process in which a value obtained by removing a detected fault from the initial suspected fault is used as a new suspected fault set element, and a separately stored fail point is used as a new target fail point.

Next, a specific example of the failure diagnosis will be described. A failure simulation was performed on the circuit of FIG. 6 by using the test patterns shown in (Table 1) and deleting the failure from the target failures of the subsequent failure simulations when the failure was first detected at the external output terminal of the circuit. As a result, the fault detected at each external output terminal at each time is as shown in (Table 4). If a correspondence table between the fault location in the circuit, the time at which each fault is first detected, and the external pin is created from (Table 4), it becomes as shown in (Table 5), which is more necessary than the fault dictionary in (Table 3). Storage capacity is small.

Next, when the tester failed using the input pattern shown in (Table 1) with respect to the circuit of FIG. 6, the test 21 failed at time 3, output 20 at time 4, and output at time 5 20, output 2 at time 6
Assume that it was 1. When the initial suspected fault is extracted from the fail information by the correspondence table search means, a / 0, c /
0, d / 0 and g / 1.

Next, these initial suspected faults are narrowed down by fault location narrowing means. For the circuit of FIG. 6, the output 21 at time 3, the output 20 at time 4, and the output 2 at time 5 using the pattern of (Table 1).
An expected value is set only at four points of the output 21 at 0 and time 6, and a failure simulation is performed for the initial suspected failure.

When a set of detected faults is obtained at the output 21 at the time 3, d / 0 and g / 1 are obtained. These are set as new suspected fault sets, and the simulation is continued until time 4. When a set of detected faults is obtained from the output 20 at time 4, the set becomes an empty set. Therefore, the element of the suspicious failure set is not changed, and the fail point of the output 20 at time 4 when the set is made an empty set is separately recorded. The suspected fault set is d / 0, g /
The simulation is continued until time 5 while keeping the value of 1. When a set of detected faults is obtained from the output 20 at time 5, the set becomes an empty set. Therefore, the element of the suspicious failure set is not changed, and the fail point of the output 20 at the time 5 when the set is set to the empty set is separately recorded. The suspected fault set is d / 0, g /
The simulation is continued until time 6 while keeping 1 as it is. When a set of detected faults is obtained from the output 21 at the time 6, the result is g / 1.

Since all target fail points have been processed, a / 0, c /
0, d / 0 are elements of a new set of suspected faults, and the output 20 at time 4 and the output 20 at time 5 are stored separately.
The failure simulation is performed using the two failed locations as new failed locations.

When a set of detected faults is obtained at the output 20 at the time 4, a / 0 is obtained. These are set as new suspected fault sets, and the simulation is continued until time 5. Time 5
When a set of detected faults is obtained at the output 20 in the above equation, a / 0 is obtained. Since all the target fail locations have been processed and no separately stored fail locations exist, the final suspected faults, which are the diagnosis results by the fault location narrowing means, are a / 0, g /
1 and this is displayed by the suspected fault display means.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described.
An embodiment will be described.

FIG. 2 is a block diagram showing a configuration of a failure diagnosis device for a semiconductor integrated circuit according to a third embodiment of the present invention. As shown in FIG. 2, the failure diagnosis device for a semiconductor integrated circuit includes a failure location storage unit 201, a correspondence table generation unit 202, a correspondence table storage unit 203, and a correspondence table search unit 20.
4. Initial fault suspect storage means 205, fault location narrowing means 206, narrowing end condition input means 207, and final suspect fault display means 208.

First, as a result of inspecting a target semiconductor integrated circuit by a tester, a fail point in the tester in which an output signal of the circuit does not match an expected value when no failure exists is stored by the fail point storage means 201. .

On the other hand, a failure simulation for checking whether or not a target fault in the circuit can be detected by using the test pattern used in the inspection is executed, and the fault location in the circuit and each fault are first determined. A correspondence table between the detected time and the external pin is generated by the correspondence table generation means 202, and the created correspondence table is stored in the correspondence table storage means 203. The individual fail locations stored in the fail location storage means 201 are compared with the contents of the correspondence table stored in the correspondence table storage means 203 by the correspondence table search means 204, and all the applicable faults in the correspondence table are determined to be the initial suspected faults. Extracted as
Initial suspected fault storage means 205 stores information on the initial suspected fault.

The fault location narrowing means 206 gives the test pattern used in the inspection for the initial suspected fault, sets an expected value only at the fail location in the tester, performs a fault simulation, and narrows down the suspected fault. And outputs a fault that has affected many failed locations as a final suspected fault.

The condition for terminating the failure simulation in the failure location narrowing means 206 is designated by the narrowing end condition input means 207. The final suspected fault, which is the result of diagnosis by the fault location narrowing down unit 206, is displayed by the final suspected fault display unit 208.

In the process of narrowing down a set of suspected faults detected at each fail location by sequential AND operation, the failure location narrowing means according to the third embodiment separately stores a fail location which makes the operation result an empty set. In other words, the set of suspected faults is narrowed down only for other failing points, and narrowing down is performed again only for the failing points stored separately. In the process of narrowing down, if the number of elements of the set of suspected faults exceeds the number specified from the end condition input device, the narrowing down is ended.

The operation of the semiconductor integrated circuit failure diagnosis apparatus according to the third embodiment will be described. Here, it is assumed that the test patterns shown in (Table 1) are used to check whether a single stuck-at fault exists in the semiconductor integrated circuit shown in FIG.

FIG. 5 is a flowchart showing a processing procedure in the fault location narrowing means according to the third embodiment of the present invention.

Step 501 is a process in which the initial suspected fault extracted by the correspondence table searching means is used as an element of the suspected fault set, and the fail point stored in the fail point storing means is used as the target fail point. Step 502 is a process of setting a fault included in the current set of suspected faults, continuing the fault simulation, interrupting the simulation at the earliest fail point among unprocessed fail points, and obtaining a detected fault set. . Step 503 is processing to determine whether or not the detected failure set is an empty set.
Step 504 is a process of setting the detected fault set to a new suspected fault set. Step 505 is a process for recording the failed set as an empty set as another set of fail points without changing the elements of the suspected fault set. Step 50
6 is a process for determining whether or not all target fail locations have been processed. Step 507 is processing to determine whether or not the specified narrowing-down ending condition has been reached. Step 508 is processing to determine whether or not there is a separately stored fail point. Step 509 is a process in which a value obtained by removing the detected fault from the initial suspected fault is used as a new suspected fault set element, and a separately stored fail point is used as a new target fail point.

Next, a specific example of failure diagnosis will be described. A failure simulation was performed on the circuit of FIG. 6 by using the test patterns shown in (Table 1) and deleting the failure from the target failures of the subsequent failure simulations when the failure was first detected at the external output terminal of the circuit. As a result, the fault detected at each external output terminal at each time is as shown in (Table 4). If a correspondence table between the fault location in the circuit, the time at which each fault is first detected, and the external pin is created from (Table 4), it becomes as shown in (Table 5), which is more necessary than the fault dictionary in (Table 3). Storage capacity is small.

Next, when the tester failed using the input pattern shown in (Table 1) with respect to the circuit of FIG. 6, the test 21 failed at time 3, output 20 at time 4, and output at time 5 20, output 2 at time 6
Assume that it was 1. When the initial suspected fault is extracted from the fail information by the correspondence table search means, a / 0, c /
0, d / 0 and g / 1.

Next, these initial suspected faults are narrowed down by fault location narrowing means. For the circuit of FIG. 6, the output 21 at time 3, the output 20 at time 4, and the output 2 at time 5 using the pattern of (Table 1).
An expected value is set only at four points of the output 21 at 0 and time 6, and a failure simulation is performed for the initial suspected failure.

When a set of detected faults is obtained from the output 21 at the time 3, the result is d / 0, g / 1. These are set as new suspected fault sets, and the simulation is continued until time 4. When a set of detected faults is obtained from the output 20 at time 4, the set becomes an empty set. Therefore, the element of the suspected fault set is not changed, and the fail point of the output 20 at time 4 when the set is set to the empty set is separately recorded. The suspected fault set is d / 0, g /
The simulation is continued until time 5 while keeping the value of 1. When a set of detected faults is obtained from the output 20 at time 5, the set becomes an empty set. Therefore, the element of the suspicious failure set is not changed, and the fail point of the output 20 at the time 5 when the empty set is set is separately recorded. The suspected fault set is d / 0, g /
The simulation is continued until time 6 while keeping 1 as it is. When a set of detected faults is obtained from the output 21 at the time 6, the result is g / 1.

Since all the target fail points have been processed, it is determined whether or not the next specified narrowing end condition has been reached. If the narrowing-down ending condition specifies that one or more suspected faults have been found, the processing of the faulty spot narrowing means is terminated at this point, and the final suspected fault, which is the diagnosis result by the faulty spot narrowing down means, is terminated. Is g / 1
And this is displayed by the suspected fault display means.

If it is assumed that the narrowing-down ending condition specifies that three or more suspected faults are found, a / 0, c / c, which excludes the detected faults from the initial suspected faults.
0, d / 0 are elements of a new set of suspected faults, and the output 20 at time 4 and the output 20 at time 5 are stored separately.
The failure simulation is performed using the two failed locations as new failed locations.

When a set of detected faults is obtained from the output 20 at the time 4, the result is a / 0. These are set as new suspected fault sets, and the simulation is continued until time 5. Time 5
When a set of detected faults is obtained at the output 20 in the above equation, a / 0 is obtained. Since all the target fail locations have been processed and no separately stored fail locations exist, the final suspected faults, which are the diagnosis results by the fault location narrowing means, are a / 0, g /
1 and this is displayed by the suspected fault display means.

[0070]

As described above, according to the present invention, when performing a failure diagnosis, a complete failure dictionary is not created, but a correspondence table is used. , The processing time can be reduced and the storage capacity can be reduced.

The present invention is also effective for other faults that do not completely match the single stuck-at fault model, such as multiple faults and short faults.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a failure diagnosis device for a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a block diagram illustrating a configuration of a failure diagnosis device for a semiconductor integrated circuit according to a third embodiment of the present invention;

FIG. 3 is a flowchart showing a processing procedure in a failure location narrowing means according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing a processing procedure in a failure location narrowing means according to the second embodiment of the present invention;

FIG. 5 is a flowchart showing a processing procedure in a failure location narrowing means according to the third embodiment of the present invention.

FIG. 6 is a logic circuit diagram showing a semiconductor integrated circuit for which a test pattern is generated.

FIG. 7 is a block diagram showing the configuration of a conventional semiconductor integrated circuit failure diagnosis apparatus.

[Explanation of symbols]

101 fail location storage means 102 correspondence table generation means 103 correspondence table storage means 104 correspondence table retrieval means 105 initial suspected failure storage means 106 failure location narrowing means 107 final suspected failure display means 201 fail location storage means 202 correspondence table generation means 203 correspondence table Storage means 204 Correspondence table search means 205 Initial suspected fault storage means 206 Fault location narrowing down means 207 Narrowing down end condition input means 208 Final suspected fault display means 301-306, 401-408, 501-509 Steps 10-13 External input signal line a To i signal line 20, 21 external output signal line 701 fail location storage means 702 failure dictionary generation means 703 failure dictionary storage means 704 failure dictionary search means 705 suspicious failure display means

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Akira Motohara 1006 Kazuma Kadoma, Osaka Prefecture F-term (reference) in Matsushita Electric Industrial Co., Ltd. 2G032 AA01 AB01 AC03 AC04 AC08 AD05 AD06 AG02 AG03 AG10 AK01 AL18 5B046 AA08 BA09 JA04 5B048 AA20 CC02 DD05 DD09 DD11 DD16

Claims (4)

[Claims] 1. A failure diagnosis apparatus for estimating a failure location of the semiconductor integrated circuit from a mismatch between a test result of the semiconductor integrated circuit and an expected simulation value, wherein the semiconductor integrated circuit is inspected by a tester, and Fail point storage means for storing a fail point in which an output signal of an integrated circuit does not match an expected value when there is no failure in the same test pattern used in the test; and a semiconductor device using the test pattern. A failure simulation is performed to check whether a target fault in the integrated circuit can be detected, and a correspondence table between a fault location in the semiconductor integrated circuit, a time when each fault is first detected, and an external pin is generated. Correspondence table generating means, correspondence table storage means for storing the correspondence table, and collating the fail location with the contents of the correspondence table A correspondence table search means for extracting all applicable failures in the correspondence table as initial suspected failures;
Initial suspected fault storage means for storing the information of the initial suspected fault, and the test pattern is provided for the initial suspected fault, an expected value is set only at the fail point, and a fault simulation is performed to determine the suspected fault. A fault location narrowing unit that narrows down and outputs a failure that has affected many fail locations as a final suspected fault, and a final suspected fault display unit that displays a final suspected fault that is a diagnostic result of the failure location narrowing down unit. A fault diagnosis device for a semiconductor integrated circuit, comprising: 2. The fault location narrowing-down means narrows down a set of suspected faults detected at each fail location by a sequential AND operation, and, in the course of the operation, excludes a failure location that sets the operation result to an empty set. 2. The fault diagnosis apparatus for a semiconductor integrated circuit according to claim 1, wherein a set of suspected faults is narrowed down only for other fail points. 3. The fault location narrowing-down means narrows down a set of suspected faults detected at each fail location by sequential AND operation, and separately stores a fail location that sets the operation result to an empty set in the process of the operation. 2. The fault diagnosis apparatus for a semiconductor integrated circuit according to claim 1, wherein the set of suspected faults is narrowed down only for other failing points, and narrowed down again only for failing points stored separately. . 4. A failure diagnosis apparatus for estimating a failure location of the semiconductor integrated circuit from a mismatch between a test result of the semiconductor integrated circuit and a simulation expected value, wherein the circuit is inspected by a tester, and Fail point storage means for storing a fail point in which the output signal of the same test pattern used in the inspection does not match an expected value when no failure is present in the same test pattern, and the semiconductor using the test pattern A failure simulation for checking whether a target fault in the integrated circuit can be detected is executed, and a correspondence table between a fault location in the semiconductor integrated circuit, a time when each fault is first detected, and an external pin is generated. A correspondence table generation unit, a correspondence table storage unit for storing the correspondence table, and comparing the fail location with the contents of the correspondence table, Correspondence table search means for extracting all applicable faults in the table as initial suspected faults, initial suspected fault storage means for storing information on the initial suspected fault, and providing the test pattern for the initial suspected fault. ,
A fault location narrowing means for setting an expected value only for the fail location, performing a fault simulation to narrow down the suspected fault, and outputting a fault that has affected many fail locations as a final suspected fault, and the fault location narrowing down Means for ending narrowing-down condition inputting means for designating a range of the number of suspected faults as conditions for ending the fault simulation in the means, and final suspected fault displaying means for displaying the last suspected fault as a diagnosis result by the fault location narrowing-down means. The fault location narrowing down means narrows down a set of suspected faults detected at each fail location by a sequential AND operation, and in the course of the operation, separately stores a fail location that sets the operation result to an empty set. The set of suspected faults is narrowed down only to the fail points other than Fault diagnosis apparatus for a semiconductor integrated circuit which is characterized in that the re-refine only the subject.