JPH10247208A - Method and device for testing integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten total test time and to improve a fault detection rate when a function test pattern for a function test is used for an IDDQ test. SOLUTION: A fault simulator 3 extracts an undetected fault point which cannot be detected in the function test with simulation by using the test pattern. An IDDQ fault detection condition setting part 5 obtains the combination of logic values by which the undetected fault point can be detected in the IDDQ test. An IDDQ test pattern selection part 10 selects the test step of a necessary minimum, which satisfies a condition, among the function test patterns based on the result of logic simulation and the combination of the logic values. An LSI tester 13 conducts the IDDQ test in the selected test step and conducts a logic function in the steps except for the selected test step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an LSI (Large Sc
an integrated circuit composed of many internal circuits such as an ale integrated circuit), an IDDQ test for detecting a leak current (quiescent power supply current) flowing through the power supply terminal of the integrated circuit is performed as necessary. The present invention relates to an integrated circuit test method and a test apparatus for efficiently performing quality judgment.

[0002]

2. Description of the Related Art Conventionally, CMOS (Complementary Metal)
In order to detect a failure of a large-scale integrated circuit (hereinafter, abbreviated as LSI) such as an Oxide Semiconductor integrated circuit, two types of test formats are known. One test format is:
It is called a function test, for example, CMOS
A test pattern composed of a combination of logical values “0” and “1” is applied to an input terminal of the integrated circuit, and a value (expected value) to be output from the output terminal in a normal case; It checks whether the value actually output from the output terminal matches.

[0003] With this function test, CM
Detects a stack-at fault (stuck-at fault) in which the input terminal of the OS integrated circuit, the node indicating the interconnection point between the internal circuits, and the output terminal are fixed to the logical value “0” or “1”. can do. Since each of the input terminal, the node, and the output terminal is a test point at which a failure is to be detected, a test pattern for a function test (hereinafter, referred to as a test pattern) is used to detect the presence of a stack-at failure at each test point. , Functional test patterns), it is necessary to create a functional test pattern in which a stack-at fault at a specific test point propagates to the output terminal by changing the combination of the logical values “0” and “1” in various ways. Therefore, assuming that one combination of the logical values “0” and “1” is called a test step, the functional test pattern is composed of a number of test steps having different logical value combinations.

In recent years, a circuit designed as a CMOS integrated circuit has a large-scale and complicated circuit configuration.
Functional test patterns are made up of a large number of test steps, and their creation is also very large. When a functional test pattern is created, a fault detection rate indicating what percentage of a stack-at fault can be detected is obtained by a fault simulation using a stack-at fault model. This failure detection rate is a test quality measure of the created functional test pattern. Of course, the failure detection rate is 1
00% is desirable, but the increase in circuit size in recent years has made it difficult to achieve a failure detection rate of 100%. In practice, development based on a failure detection rate of 95% or more has been performed.

[0005] Another test format described above is an IDD.
This is called the Q test. The name IDDQ is LS
This is based on the fact that the power supply current flowing to the power supply terminal of the LSI when I is not performing a switching operation is generally called I _DDQ . I _DD corresponds to the abbreviation V _DD commonly used for the power supply voltage. Q is
It is an acronym for quiescent.

In the IDDQ test, as in the case of the function test, a test pattern is applied to the input terminal of the CMOS integrated circuit to be inspected, and the power supply current flowing through the power supply terminal of the CMOS integrated circuit is monitored to exceed a specified value. It is checked whether such an abnormal current is flowing.

In general, a CMOS integrated circuit has a property that a large current flows only at the time of a state transition of an internal circuit such as a logic circuit or the above-mentioned node state transition, and almost no current flows at the time of rest. The IDDQ test detects a defect by utilizing such properties of a CMOS integrated circuit.

For example, in a CMOS integrated circuit, if a resistive short circuit occurs in which a portion of an internal circuit or a node and a power supply or a ground are conductive with a certain resistance value, the resistance value is reduced. If it is very large, a leak current that causes a slight variation in the voltage level that is logically determined to be “0” or “1” flows to the power supply terminal. In the IDDQ test, by detecting this leak current, it is possible to detect the presence of a defect inside the CMOS integrated circuit and the location where the defect has occurred.

In this IDDQ test, it is necessary to measure the leak current when the state of a test point such as each node is a logical value “0” and when the state is “1”.
The measurement is performed while changing the internal state of the S integrated circuit as needed.
Therefore, also in the IDDQ test, it is necessary to prepare test patterns in which the combinations of the logical values “0” and “1” are variously changed.

There are a method for preparing a test pattern for the IDDQ test, and a method for preparing a test pattern dedicated to the IDDQ test, and a method for diverting the function test pattern. In general, a test pattern dedicated to IDDQ has a smaller number of test steps than a functional test pattern, but needs to be created separately from the functional test pattern. On the other hand, if a functional test pattern is used for the IDDQ test, there is a disadvantage that the number of test steps increases, but the trouble of creating a test pattern dedicated to the IDDQ test can be omitted. For this reason, a method of diverting the function test pattern for the IDDQ test is often adopted.

For example, Japanese Patent Application Laid-Open No. 6-118131 is known as a prior art relating to the IDDQ test. In the above publication, as shown in FIG. 10, first, a certain function test pattern is created based on the configuration of an integrated circuit to be inspected. Next, when the created function test pattern is input to the integrated circuit, a state change rate T, which is a ratio of how much a node inside the integrated circuit shows two states of logical values “0” and “1”. Ask for.

In parallel with this, a failure simulation for obtaining a failure detection rate K of a stuck-at failure is performed using the created functional test pattern. Then, the addition and correction of the function test pattern are repeated until each of the state change rate T and the failure detection rate K satisfies the set criterion.

Next, a new failure detection scale F (K, T) derived from the state change rate T and the failure detection rate K is obtained.
The above series of processing is repeated until the failure detection scale F (K, T) satisfies the set criterion. It is stated that a sufficiently high-quality test can be performed on a CMOS integrated circuit by performing an IDDQ test (quiescent power supply current measurement) using the added and corrected functional test patterns.

However, the test speed of the CMOS integrated circuit test apparatus is several tens of MHz in the case of the function test, while the IDDQ test requires a waiting time until the power supply current becomes stable for each test step. Because of the necessity, the frequency becomes as slow as several tens KHz. As a result, even if the time required for each test step in the IDDQ test is at most only a few microseconds to several hundred microseconds, the number of test steps becomes very large with an increase in circuit scale. The total will also increase dramatically.

In Japanese Patent Application Laid-Open No. 6-118131,
Since the IDDQ test is performed in all test steps using the functional test pattern,
A very long time is required for quality inspection.

[0016] Therefore, the IDDQ
A test point for performing an IDDQ test, focusing on the point that all nodes need to be measured in two states of a logical value “0” and a logical value “1” in order to perform a test. There is known a method of reducing the time required for an IDDQ test by creating a functional test pattern that does not overlap the IDs.

For example, republished publication WO92 / 01943.
First, a function test pattern is created based on the configuration of an integrated circuit to be inspected. Next, the states of all nodes in each test step constituting the function test pattern are stored in the node state storage file by a logic simulation using the created function test pattern. Subsequently, referring to the node state storage file, the number of nodes at which the stack-at fault fixed to the logical value “0” can be detected by the IDDQ test is fixed to the logical value “1” for each test step. The number of nodes at which a stack-at fault can be detected by the IDDQ test is stored in a frequency file.

Further, referring to the node state storage file, a test step for enabling the IDDQ test to detect a stuck-at fault fixed to the logical value "0" for each node is picked up, and the "0" state file is read. create. Similarly, for each node, a test step that enables a stack-at fault fixed to a logical value “1” to be detected by an IDDQ test is picked up, and “1” is selected.
Create a state file. In the “0” state file and the “1” state file, test steps capable of detecting a stuck-at fault of a certain node are repeatedly picked up.

After that, by repeating the sorting, searching, and condition judging for each file by using a specific key, for example, a test step which can detect a stuck-at failure is less duplicated and a test step corresponding to a node which is hardly activated is given priority. Then, by referring to the frequency file, a test step having a large number of nodes capable of detecting a stuck-at fault is selected in order.
It is stated that this makes it possible to create an IDDQ test pattern capable of performing an IDDQ test by narrowing down the number of test steps while diverting a functional test pattern.

[0020]

However, the above-mentioned re-publication publication WO92 / 01943 discloses, as a specific method, (1) a method for creating a test pattern dedicated to IDDQ test, or (2) a function test pattern. , IDD
A method is disclosed in which a test step effective for a Q test is selected, and a function test and an IDDQ test are used in combination.

In this case, in the method (1), the dedicated I
Since a pattern for the DDQ test must be created, there is a problem that the trouble increases. In the above method (2), although the function test pattern is diverted, the failure and the ID that can be inspected by the function test are determined.
There is no association with a failure that can be tested by the DQ test. For this reason, at a test point where a failure cannot be detected in the function test, the function test and the IDDQ test are performed in an overlapping manner, and there is a problem that the quality inspection is inefficient.

[0022] Thus, the re-publication publication WO92 / 019.
In the method disclosed in No. 43, further C
More efficient IDDs with larger MOS integrated circuits
It is insufficient to provide an integrated circuit test method and a test apparatus that can achieve a high fault coverage while reducing the required test time by reducing the number of test steps in the Q test.

An object of the present invention is to reduce the number of test steps in an IDDQ test as much as possible, and to efficiently detect a fault that cannot be detected by a function test, thereby further reducing the required test time. To provide a test method and a test apparatus.

[0024]

According to a first aspect of the present invention, there is provided a method of testing an integrated circuit, comprising: forming a test pattern for a logic function test comprising a plurality of test steps having different combinations of logical values; Created based on the configuration of the integrated circuit and a plurality of test points set on the integrated circuit, by simulation using the created test pattern, to extract undetected fault points from which no fault can be detected among the test points, For the undetected fault point, a test step that gives a combination of logical values that can detect the fault when the quiescent power supply current is measured is selected from the test pattern, and the quiescent power supply current is determined for the undetected fault point. Perform a logical function test at test points other than the undetected failure point while measuring. It is characterized.

According to the above configuration, even if the test pattern created for the logic function test does not have a failure detection rate of 100%, the undetected failure in which the logic function test using the test pattern cannot detect a failure. Instead of creating new test patterns for points,
From the created test patterns, a test step capable of detecting a failure by measuring the static power supply current is selected.

In this case, an undetected fault point is extracted by simulation using the created test pattern, a combination of logical values that makes the undetected fault point detectable by measuring the quiescent power supply current, and the logical value is determined. The determination of a test step that includes a combination of values
This is important as a test step selection process.

As described above, by diverting the test pattern created for the logic function test, the processing required for preparing the test pattern can be simplified, and
Processing time can be reduced. Furthermore, since the measurement of the quiescent power supply current, which requires more time than the logic function test, is performed only for the undetected fault points, the test time is much longer than when a failure is detected only by measuring the quiescent power supply current for all test points. Can be shortened. In addition, as a result of combining the measurement of the quiescent power supply current with the logic function test, the failure detection rate by the logic function test can be reliably improved.

According to a second aspect of the present invention, there is provided an integrated circuit test method according to the first aspect, wherein the test pattern is used to minimize the number of test steps used for measuring the quiescent power supply current. It is characterized by selecting a test step.

According to the above configuration, one test step for one undetected fault point does not always enable the detection of a fault by measuring the quiescent power supply current, and one test step for one undetected fault point In some cases, more than one test step applies. That is, depending on how the test step is selected, there is a possibility that the detection of a failure by measuring the quiescent power supply current may be performed at the same undetected failure point.

Therefore, by selecting test steps from the above test patterns so that the number of test steps used for measuring the quiescent power supply current is minimized, the quiescent power supply current can be measured for the same undetected fault point. It is possible to avoid performing a duplicate test by Thereby, the test time can be further reduced as compared with the test method according to the first aspect.

According to a third aspect of the present invention, in the method of testing an integrated circuit according to the first aspect, when the test step is selected from the test patterns, the test step is further performed for each test step. The number of undetected fault points at which a fault can be detected by measuring the quiescent power supply current is counted, the test step with the maximum count value is selected, and the undetected fault point that can be detected by the selected test step is determined by the following. It is characterized in that it is repeatedly removed from the count.

According to the above configuration, by preferentially selecting a test step that maximizes the number of undetected fault points at which a fault can be detected by measuring the quiescent power supply current,
In one selected test step, as many undetected fault points as possible can be checked for a fault. In addition, since the undetected fault points that can be detected by the selected test step are excluded from the next count, the next selected test step may check for an undetected fault point that overlaps with the already selected test step. Can be avoided.

Thus, the test time can be further shortened as compared with the test method described in claim 1, and a test method that embodies the test method described in claim 2 can be provided.

According to a fourth aspect of the present invention, in the integrated circuit test apparatus, a test pattern for a logical function test composed of a plurality of test steps having different combinations of logical values is integrated with a test target integrated circuit (for example, a CMOS). A test pattern creation unit (for example, a test pattern generation unit) created based on the configuration of the integrated circuit and a plurality of test points set on the integrated circuit; A fault simulation means (for example, a fault simulator) for extracting an undetected fault point in which a fault cannot be detected, and a logical value that enables the fault to be detected when the quiescent power supply current is measured for the undetected fault point Failure detection condition setting means for obtaining a minimum combination (for example, IDDQ A fault detection condition setting unit), a logic simulation unit (for example, a logic simulator) for determining a logic value indicated by each test point for each test step when the test pattern is input to the integrated circuit, and a fault detection unit. By comparing the combination of the logical values obtained by the condition setting means with the logical values of the respective test points obtained by the logical simulation means, the above-described method is performed so that the number of test steps used for measuring the static power supply current is minimized. It is characterized by including test pattern selection means (for example, an IDDQ failure detection availability determination unit, a determination result storage unit, and an IDDQ test pattern selection unit) for selecting a test step from a test pattern.

According to the above configuration, even when the test pattern creating means for the logic function test created for the integrated circuit to be inspected does not have a failure detection rate of 100%, A test that can detect a fault by measuring the static power supply current from the created test pattern instead of creating a new test pattern for undetected fault points where a fault cannot be detected by the logic function test using the test pattern. Steps are selected.

In this case, for the undetected fault points extracted by the fault simulation means, the minimum necessary combination of logical values that can detect a fault by measuring the quiescent power supply current is obtained by the fault detection condition setting means. On the other hand, the logic simulation means simulates the operation of the integrated circuit by the test pattern, and obtains a logical value as an expected value of each test point for each test step.

Subsequently, the test pattern selecting means obtains a test step including the necessary minimum combination of the logical values obtained by the fault detection condition setting means, and the required minimum combination of the logical values and the logic simulation means. By comparing with the logical value of each test point, a selection is made from the above test patterns. In addition, the test pattern selecting means selects such that the number of test steps used for measuring the static power supply current is minimized.

As a result, the static power supply current is measured using the selected test step, and a fault that cannot be detected by the logic function test is detected. Therefore, compared to the case where only the logic function test is performed using the test pattern, The failure detection rate can be reliably improved. In addition, by diverting the test pattern created for the logic function test, the processing required for preparing the test pattern can be simplified, and the processing time required for preparing the test pattern can be reduced. Furthermore, since the measurement of the quiescent power supply current, which requires more time than the logic function test, is performed by focusing on the undetected failure points, the failure is detected only by measuring the quiescent power supply current at all test points, or the logic function test is performed. The test time can be greatly reduced as compared with the case where the measurement of the quiescent power supply current is repeatedly performed for an undetected fault point that cannot be detected by performing the test.

According to a fifth aspect of the present invention, in the test apparatus for an integrated circuit, when the test pattern selecting means selects test steps in descending order of the number of undetected fault points at which a fault can be detected by measuring the quiescent power supply current, Mask data generating means (for example, mask) for generating mask data for excluding an undetected fault point that can be detected by measuring the quiescent power supply current using the test step that has already been selected from the selection of the next test step Pattern storage unit), and based on the final mask data at the time when the test pattern selection unit has finished selecting all test steps, determines an undetected fault point that cannot be detected even by measuring the static power supply current. Failure determination means (for example, an undetected failure report output unit) contacts the mask data generation means. It is characterized in that it is.

According to the above arrangement, the mask data is generated by the mask data generating means in order to exclude an undetected fault point which can be detected by measuring the quiescent power supply current from selection of the next test step. Therefore, by repeatedly generating the mask data, the finally generated mask data has an indirect correspondence with the remaining undetected fault points that cannot be detected even by measuring the static power supply current.

Therefore, the undetected fault determining means can determine the remaining undetected fault points based on the mask data finally generated by the mask data generating means.

As described above, since the mask data prepared for selecting the test step used for measuring the quiescent power supply current is used to determine the remaining undetected fault point, such undetected fault points are used. Failure point determination processing can be simplified. In addition, determining the undetected fault point means that the position and state of the remaining undetected fault can be specified.

As a result, the location and state of an undetected fault that cannot be detected even by measuring the quiescent power supply current can be processed very easily.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

First, the flow of the integrated circuit test method according to the present embodiment will be schematically described. That is, as shown in FIG. 2, first, assuming that a CMOS integrated circuit is to be inspected, a functional test pattern used for a function test is created based on the circuit configuration and a plurality of test points for detecting a failure. (Step 1, hereinafter S
Abbreviated as 1). In addition, the above test point is CM
The setting is made for each input side terminal and output side terminal of the OS integrated circuit and each node inside the CMOS integrated circuit.

Next, using this function test pattern,
A failure simulation is sequentially performed to check whether a simulated failure can be detected at each node or the like inside the CMOS integrated circuit (S2). Further, a node in which a failure cannot be detected and its failure state are specified by the above failure simulation, and are set as test points at which an IDDQ test is to be executed (S3). With respect to the test points narrowed down in this way, an IDDQ test pattern that enables the failure state to be detected by the IDDQ test is created (S4). Then, using the function test pattern created in S1 and the IDDQ test pattern created in S4 to compensate for the insufficiency of the function test pattern,
A quality inspection of the MOS integrated circuit is performed (S5).

As a result, a high-quality inspection can be performed while shortening the inspection time by executing the minimum IDDQ test as necessary, mainly using the function test.

Next, the configuration of the test apparatus 1 for performing the above-described integrated circuit test method will be described. As shown in FIG. 1, the test apparatus 1 creates a functional test pattern used for a function test based on a configuration of an integrated circuit to be tested and a plurality of test points set according to the configuration of the integrated circuit. And a test pattern generation unit 2 (test pattern generation means). In the present embodiment, the integrated circuit is a CMOS integrated circuit including, for example, a NAND circuit and a NOR circuit.

A functional test pattern composed of a plurality of test steps, each of which is provided with an identification address (hereinafter referred to as a pattern address), is supplied from the test pattern generator 2 to the failure simulator 3 (failure simulation means). Are sequentially sent out. In the failure simulator 3, each node inside the CMOS integrated circuit has a logical value “0”.
Alternatively, by simulating the stack-at fault fixed to “1” according to the stack-at fault model, a fault simulation is performed to determine whether the stack-at fault of each node can be detected using the input function test pattern. . This failure simulation is performed for all nodes for each test step. As a result, a stack-at fault that cannot be detected even if a fault simulation is performed up to the last test step is picked up.

An undetected fault list storage unit 4 is connected to the fault simulator 3. The undetected fault list storage unit 4 stores undetectable stuck-at faults picked up by the fault simulator 3 as an undetected fault list.

Further, the undetected fault list storage unit 4 stores
The IDDQ failure detection condition setting unit 5 (failure detection condition setting means) is connected. IDDQ failure detection condition setting unit 5
Refers to the undetected fault list stored in the undetected fault list storage unit 4 and obtains an IDDQ fault detection condition for enabling detection by the IDDQ test for each stack-at fault picked up therein. In other words, the IDDQ fault detection condition setting unit 5 sets the logic value “0” or “0” which must be given to each input terminal or each node of the CMOS integrated circuit as the IDDQ fault detection condition, as will be described later in detail. Find a combination of 1 ".

On the other hand, the function test patterns created by the test pattern generator 2 are sequentially sent to the logic simulator 6 (logic simulation means). The logic simulator 6 simulates a circuit configured by modeling each circuit element of the CMOS integrated circuit on a computer, and performs a logic simulation to obtain an expected value of a logic value at each node. The logical value of each node obtained by the logical simulation is stored in a logical value table in a node logical value storage unit 7 connected to the logical simulator 6.

An IDDQ failure detection availability determination unit 8 is connected to each of the IDDQ failure detection condition setting unit 5 and the node logical value storage unit 7. The IDDQ failure detection availability determination unit 8 includes an IDDQ failure detection condition input from the IDDQ failure detection condition setting unit 5 and a node logical value storage unit 7.
And a test step having a combination of logical values that match the IDDQ failure detection condition is specified. This identified test step
A stack-at fault that is originally created for a function test but cannot be detected by a function test can be detected by diverting it to an IDDQ test.

Further, the IDDQ failure detection availability determination section 8
Also has a function of setting a flag "1" in the correspondence table between the above-mentioned undetected failure list and each test step, which enables the failure detection by the IDDQ test. The correspondence table (IDDQ failure detection data table described later) with the flag set in this way is stored in the determination result storage unit 9.

An IDDQ test pattern selection unit 10 is connected to the judgment result storage unit 9. The IDDQ test pattern selection unit 10 reads out the correspondence table stored in the determination result storage unit 9 to determine that the flag is set most frequently, in other words, in order from the test step with the largest number of failure detections by the IDDQ test. The pattern address is selected and output to the IDDQ test address output unit 11.

The IDDQ failure detection availability determination section 8, determination result storage section 9, and IDDQ test pattern selection section 10 constitute a test pattern selection means described in the claims.

Further, while receiving the address information from the IDDQ test address output unit 11, the test control unit 12 uses the function test pattern called from the test pattern generation unit 2 to send the LSI tester 13 only for a specific test step. An IDDQ test is performed, and the LSI tester 13 performs a function test except for the specific test step.

As shown by the two-dot chain line in FIG. 1, the above-mentioned undetected fault list storage unit 4, IDDQ fault detection condition setting unit 5, node logical value storage unit 7, IDDQ fault detection availability determination unit 8, Judgment result storage unit 9, IDDQ test pattern selection unit 10, IDDQ test address output unit 1
1, a failure detection scale calculation unit 30 and an undetected failure report output unit 31, which will be described later, constitute an IDDQ test pattern generation device.

Next, the internal configuration of the IDDQ test pattern selector 10 will be described in detail.

As shown in FIG. 3, the IDDQ test pattern selector 10 includes a storage register 14, an AND
5, a NOT operation unit 16, a counter unit 17, an address count UP unit 18, a final address determination unit 19, and a processing end determination unit 20 are provided as main components. Further, the storage register 14 includes a current address storage unit 21, a maximum count value storage unit 22, a maximum count point address storage unit 23, a maximum count point flag storage unit 24, a mask pattern storage unit 25, and a selected address storage unit 26. Have.

As described above, the IDDQ test pattern selecting section 10 sequentially assigns the pattern addresses to the test steps in which the flag is set most frequently in accordance with the correspondence table stored in the determination result storage section 9 as described above. To make a selection, the contents of the correspondence table are read out in the order of the pattern addresses of the test steps, and the number of flags is counted by the AND operation unit 15 and the counter unit 17.

Here, the current address storage unit 21
Is a register for storing a pattern address being counted by the counter unit 17. Also,
The address count UP unit 18 sequentially increments the pattern address stored in the current address storage unit 21 so that the contents of the correspondence table of the next pattern address are read from the determination result storage unit 9.

The last address judging section 19 judges whether or not the counting in the counter section 17 has been performed for all pattern addresses. The processing end determination unit 20 determines whether there is no more pattern address to be selected as a result of repeating the processing of selecting the pattern address of the test step with the most flags set.

The maximum count value storage section 22 is a register that compares the number of flags in each test step each time the counter section 17 counts, and updates and stores the maximum value of the number of flags. The maximum count point address storage unit 23 is a register that stores a pattern address of a test step in which the number of flags is maximum in the maximum count value storage unit 22. Further, the count maximum point flag storage unit 24 is a register that stores the state of the flag in the test step of the pattern address stored in the count maximum point address storage unit 23 in an array of “1” and “0”.

The mask pattern storage section 25 corresponds to the mask data generating means according to claim 5, and after the process of selecting the pattern address of the test step in which the flag is set most frequently goes through once, Is a register for creating mask data for excluding a pattern address that has already been selected from selection targets when performing a process of selecting a pattern address of a test step in which many flags are set.

The selection address storage unit 26 selects the pattern address stored in the maximum count point address storage unit 23 when the process of selecting the pattern address of the test step in which the flag is set most has been completed. This is a register for storing the pattern address to be stored. Therefore, after the process of selecting the pattern address is repeated in the selected address storage unit 26 in order from the test step in which many flags are set, after the number of failure detections by the IDDQ test is large, that is, activation is performed. The pattern addresses arranged in the order in which the pattern addresses are arranged are stored.

The selected address storage unit 26 stores the I
The DDQ test address output unit 11 is connected. I
The result stored in the selected address storage unit 26 is output to the DDQ test address output unit 11 when the pattern address selection processing in the IDDQ test pattern selection unit 10 ends.

As shown in FIGS. 1 and 3, the mask pattern storage unit 25 is connected to a failure detection scale calculation unit 30 and an undetected failure report output unit 31. First, the failure detection scale calculation unit 30 performs an IDDQ test in a test step of the pattern address selected by the IDDQ test pattern selection unit 10, and calculates a failure detection scale when performing a function test in other test steps. . The failure detection scale corresponds to the accuracy of failure detection. A failure detection scale storage unit 32 is connected to the failure detection scale calculation unit 30, and the calculation result is stored in the failure detection scale storage unit 32.

On the other hand, an undetected failure report output unit 31 is further connected to an undetected failure report storage unit 33. The undetected failure report output unit 31 corresponds to the undetected failure determination unit according to claim 5, and the flag is set even if the flag is set in the correspondence table stored in the determination result storage unit 9. If the IDDQ test pattern selection unit 10 does not find a test step that can detect a fault location that is present, the fault location is output to the undetected fault report storage unit 33 and stored.

In the above configuration, the operation of the test apparatus 1 will be described with reference to FIG. 1 and FIGS. 4 to 9 by giving a configuration example of a simple logic circuit. As a specific logic circuit, a 5-input / 1-output logic circuit 50 including NAND circuits 51 and 52 and NOR circuits 53 and 54 shown in FIG. 4 was used.

According to the present invention, a function test pattern that can detect a stack-at fault that cannot be detected by the function test by performing the IDDQ test is selected.
It is intended to minimize the implementation of IDDQ tests. Therefore, first, a failure that can be detected by the IDDQ test, that is, a correspondence between a resistive short-circuit failure (hereinafter, abbreviated as a short-circuit failure) of a MOS transistor that is a constituent unit of a CMOS integrated circuit and a stack-at failure that can be detected by a function test. The relationship will be described. Note that the short-circuit failure is defined as MO
This is a failure in which a leakage current flows between the source and the drain when the S transistor is off.

First, the input terminals A and B shown in FIG.
A description will be given using a NAND circuit 61 having an output terminal Z and an output terminal Z as an example. As shown in FIG. 5B, the NAND circuit 61 includes four MOS transistors (hereinafter simply referred to as transistors) TR1 to TR4. Hereinafter, the combination of the logical values given to the input terminals A and B is expressed in the form of (A, B) = (the logical value given to the input terminal A, the logical value given to the input terminal B).

For example, when (A, B) = (1, 1), if there is no failure in each of the transistors TR1 to TR4, the transistors TR1 and TR2 are turned off and the transistors TR3 and TR4 are turned on. No leakage current flows from the power supply V to the ground GND. But,
Assuming that a short-circuit fault occurs in the transistor TR1, at that time, the power supply V is switched to the ground GND.
A current flows through the path of the transistors TR1, TR3, and TR4. As a result, a leakage current is observed, and can be detected by the IDDQ test.

When a short-circuit fault occurs in the transistor TR2, a current flows from the power supply V to the ground GND through the path of the transistors TR2, TR3, and TR4, and thus can be similarly detected by the IDDQ test.

Since the transistors TR3 and TR4 are in an ON state in which current flows regardless of whether or not each transistor is faulty, when (A, B) = (1, 1),
It is meaningless to assume a short-circuit failure of the transistors TR3 and TR4.

Next, let us consider applying the above-mentioned short fault to a stack-at fault. When there is no stuck-at fault, the output terminal Z outputs "0" when (A, B) = (1, 1). On the other hand, a stack-at fault in which the input terminal A is fixed to “0” (denoted as A-sa0) or a stack-at fault in which the input terminal B is fixed to “0” (denoted as B-sa0) When (A), (A, B) = (1, 1),
Since the output terminal Z outputs "1", the fault propagates.

Therefore, transistor TR1 or T
The short-circuit fault of R2 and the stack-at fault A-sa0 or B-sa0 both have fault states that can be observed only when (A, B) = (1, 1). It can be classified.

When (A, B) = (1, 0), if there is no short circuit in each of the transistors TR1 to TR4, the transistors TR1 and TR4 are turned off and the transistors TR2 and TR3 are turned on. No leakage current flows from the power supply V to the ground GND. However, assuming that a short-circuit failure occurs in the transistor TR4, at that time, the power supply V is switched to the ground GND.
A current flows to D through the path of the transistors TR2, TR3, and TR4. As a result, a leakage current is observed, and can be detected by the IDDQ test.

When a short-circuit fault occurs in the transistor TR1, no current path is formed from the power supply V to the ground GND. Therefore, when (A, B) = (1, 0), the transistor TR1 Cannot detect the short-circuit failure of Also, the transistors TR2, T
Since R3 is in the ON state, a short circuit failure cannot be assumed in any case.

The above short fault is applied to a stack-at fault and considered. When there is no stuck-at fault, when (A, B) = (1, 0), the output side terminal Z
Outputs “1”. On the other hand, when a stack-at fault (indicated as B-sa1) in which the input side terminal B is fixed to “1” occurs, despite (A, B) = (1, 0) , Output terminal Z outputs "0", and the fault propagates.

Therefore, the short-circuit fault of the transistor TR4 and the stuck-at fault B-sa1 can be observed only when (A, B) = (1, 0). It can be classified.

Further, when (A, B) = (0, 1), similarly, the short-circuit fault of the transistor TR3 and the stack-at fault A-sa1 can be classified as equivalent fault types.

On the other hand, when (A, B) = (0, 0), a current path from the power supply V to the ground GND is not formed due to a short-circuit failure of the transistors TR1 to TR4. Whether I exists
It cannot be detected by the DDQ test. Further, even in the case of a stack-at fault, the fault does not propagate to the output terminal Z.

From the above, the NAN shown in FIG.
In the D circuit 61, the correspondence between the stack-at fault detectable by the function test and the short-circuit fault detectable by the IDDQ test is as shown in Table 1.

[0085]

[Table 1]

Also, for the NOR circuits shown in FIGS. 6A and 6B, the correspondence shown in Table 2 is obtained with respect to the short-circuit fault and the stuck-at fault based on the same concept.

[0087]

[Table 2]

On the premise of the above, a process for testing the logic circuit 50 shown in FIG. 4 will be described. Note that the test pattern generation unit 2 generates a functional test pattern created in advance for a function test of the logic circuit 50 based on the configuration of the logic circuit 50 and a test point at which a test is performed on the logic circuit 50 for the presence or absence of a failure. An example is shown in Table 3 below. In other words, this function test pattern sequentially gives eight combinations of logic values “0” or “1” shown in Table 3 to each of the input terminals a, b, c, d, and e of the logic circuit 50. Each test step is identified by pattern addresses <1> to <8>.

[0089]

[Table 3]

The logic simulator 6 performs the above-described logic simulation on the logic circuit 50 by using the functional test patterns shown in Table 3, and obtains each of the nodes f, g, h inside the logic circuit 50 and the output terminal. Table 4 shows a logical value table for obtaining the expected value at z.

[0091]

[Table 4]

As shown in FIG. 7, first, in S11, each test step of pattern addresses <1> to <8> is performed by the test pattern generation unit 2 and the failure simulator 3
, And the above-described failure simulation is performed. At this time, the failure simulator 3 sets the input terminal a,
For each of b, c, d, e, nodes f, g, h, and output terminal z, the above two types of stack-at faults sa0
Alternatively, it is determined whether or not sa1 can be detected for each test step. Table 5 below shows a stack-at failure detection list created as a result of the determination.

[0093]

[Table 5]

In Table 5, detectable stack-at faults are indicated by circles. For example, when a failure simulation is performed using the test step of the pattern address <1>, a logical value “0” is output to the output terminal z in a normal state, as can be seen from Table 4. On the other hand, the fault propagates so that the logical value “0” is not output to the output terminal z as expected and the logical value “1” is output, and the stack-at fault that can be detected is e-sa0. Table 5 shows that z-sa1 and z-sa1.

From the results in Table 5, the pattern address <1>
When a function test is performed using each test step of <8>, a stack-at fault b-sa1, c-sa
1. It can be seen that d-sa0 is not detected. Therefore,
The failure simulator 3 obtains the result of the failure simulation,
The stack-at faults b-sa1, c-sa1, and d-sa0 are picked up and stored in the undetected fault list storage unit 4 as an undetected fault list.

In the case of the logic circuit 50, as shown in Table 5, 18 types of stack-at faults from a-sa0 to z-sa1 can be assumed. On the other hand, in the above function test, three stack-at faults b-sa1, c-sa1, and d-sa
0 is not detected, the failure detection rate of the function test using the function test pattern shown in Table 3 is 15 /
18 (83.3%).

Therefore, for example, if it is intended to achieve a failure detection rate of 100% only by a function test, it is necessary to add a test pattern as shown in Table 6 below.

[0098]

[Table 6]

However, the integrated circuit to be actually inspected is not a small-scale circuit configuration like the logic circuit 50 of the present embodiment, but an LSI having several hundred thousand gates. Therefore, in the case of the above-described logic circuit 50, it is relatively easy to obtain an additional test step. However, in the case of an actual integrated circuit, the operation of creating such a new test step is very complicated. It is not easy.
Therefore, in the present invention, a test step capable of detecting a failure by the IDDQ test is found out of the function test patterns for the function test, and the inspection speed of the high-quality test is reduced.

Therefore, in S12 following S11, the ID
The DQ fault detection condition setting unit 5 refers to the undetected fault list stored in the undetected fault list storage unit 4 and, for each stack-at fault picked up therein, IDDQ
An IDDQ failure detection condition for detection by a test is determined. The IDDQ fault detection condition is obtained based on the correspondence between the short fault and the stack-at fault as shown in Table 1 or Table 2.

For example, since the stack-at fault b-sa1 in the undetected fault list is generated by the NAND circuit 51,
See Table 1 for NAND circuits. According to Table 1, the stack-at fault b-sa1 is (A, B) =
This corresponds to a combination of (1, 0) and the stack-at fault B-sa1. Therefore, a combination of logical values where a = 1 and b = 0 indicates that the stack-at fault b-sa1 has an ID
It can be seen that the minimum necessary detection condition that can be detected by the DQ test is obtained.

Since the stack-at fault d-sa0 in the undetected fault list is generated by the NOR circuit 53,
See Table 2 for the R circuit. According to Table 2,
The stuck-at fault d-sa0 is (A, B) = (0, 1)
And a stack-at fault B-sa0. Therefore, it can be seen that the combination of the logical values of g = 0 and d = 1 is the minimum necessary detection condition that enables the stuck-at fault d-sa0 to be detected by the IDDQ test.

The IDDQ fault detection conditions for all the stack-at faults b-sa1, c-sa1, and d-sa0 in the undetected fault list are as shown in Table 7 below. Further, for the input side terminals a, b, c, d and nodes f, g extracted as shown in Table 7, ID
When the DQ failure detection condition table (correspondence table described above) is created, it is as shown in Table 8 below. Table 8 shows input terminals a, b, c, d and nodes f, g for detecting each stack-at fault b-sa1, c-sa1, d-sa0.
Shows the necessary condition of the logical value to be given to. The location where the symbol * is entered may be either a logical value “0” or “1”.

[0104]

[Table 7]

[0105]

[Table 8]

In this example, the logical values of the input terminal e, the node h, and the output terminal z are omitted as they are unnecessary as detection conditions. Further, the IDDQ failure detection condition table may be configured to be stored in the memory by the IDDQ failure detection condition setting unit 5.

Subsequently, in S13, each test step of the pattern addresses <1> to <8> is sequentially input from the test pattern generation unit 2 to the logic simulator 6, and the above-described logic simulation is performed. As a result, the logical value of each unit output by the logical simulator 6 is taken into the node logical value storage unit 7 as an internal signal, and the above-described logical value table shown in Table 4 is created and stored (S14).

In S15, the IDDQ failure detection availability determination section 8 performs a test step on the IDDQ failure detection condition input from the IDDQ failure detection condition setting section 5 and the logical value table stored in the node logical value storage section 7. Each test is compared to determine a test step having a combination of logical values that match the IDDQ failure detection condition.

For example, for the test step of pattern address <4>, the internal signal state “abcdfg” = “10
1110 "is compared with the IDDQ failure detection condition or the IDDQ failure detection condition table.
It can be seen that the condition matches "10 ****" which is the IDDQ failure detection condition of No. 1 and "*** 1 * 0" which is the IDDQ failure detection condition of the stack-at fault d-sa0.

Thus, it is determined that the test step of pattern address <4> enables the stack-at faults b-sa1 and d-sa0 to be detected by the IDDQ test.
That is, as shown in Table 9 below, the IDDQ failure detection possibility determination unit 8 determines that the pattern address <4>, the stack-at faults b-sa1 and d-sa0 are in the correspondence table between the undetected fault list and the pattern address. A flag “1” is set for each of the correspondences.

In this manner, the IDDQ failure detection availability determination section 8 repeats the processing of S15 for all test steps until it is determined that the internal signal state has been compared with the IDDQ failure detection condition in S17. . As a result, an IDDQ failure detection data table shown in Table 9 is created and stored in the determination result storage unit 9 (S16).

[0112]

[Table 9]

Note that, in the flowchart of FIG.
The processing returns from before to S15, and after completion of the logical value table of Table 4, the processing of S15 and S16 is repeated for each test step. However, the present invention is not limited to this, and the processing returns from S17 to S13 before S13 to S13.
The process of S16 may be repeated.

Next, in S18, the IDDQ test pattern selection unit 10 refers to the IDDQ failure detection data table obtained above, and determines the pattern address of the test step that can be used for the IDDQ test based on the criteria described below. Then, selection is made according to the flow shown in FIG.

As shown in FIG. 8, first, in S31, initialization of mask data output from the mask pattern storage unit 25 is performed. In the example of the logic circuit 50, three stack-at faults b-sa1 and c-
Since sa1 and d-sa0 have been extracted, the mask data is initialized to “111”. As a result, for all the stack-at faults b-sa1, c-sa1, and d-sa0, the IDD
Processing for searching for a test step that can be detected by the Q test is executed.

Note that when the process of searching for and selecting a test step that meets the criterion has been completed for all test steps, a stack-at fault in which a test step that can be detected by the IDDQ test is found, for example, b-sa1,
The mask data corresponding to either c-sa1 or d-sa0 is 0
Is set to Thereby, the mask data at that time can indicate the number and position of the stack-at faults for which a test step that can be detected by the IDDQ test cannot be found.

In the current address storage unit 21 and the count maximum value storage unit 22, 0 is set as an initial value (S32). Then, the address count UP unit 18
As a result, the value (current address) of the current address storage unit 21 is incremented by one (S33).
Then, the contents of the IDDQ failure detection data table shown in Table 9 are sequentially read from the determination result storage unit 9 from the pattern address <1>. At this time, the AND operation unit 15
An AND operation is performed between the mask data and the IDDQ failure detection data of each pattern address (S34). further,
The counter unit 17 counts the number of the flag “1” for each test step from the result of the AND operation (S35).
The number of the flags “1” indicates the number of stack-at faults that can be detected by the IDDQ test by the test step to be counted.

For example, in the IDDQ failure detection data table shown in Table 9, the first round of the AN of the IDDQ failure detection data of each pattern address and the mask data "111" is performed.
As a result of the D operation, the number of flags "1" is 0 for pattern address <1>, 0 for pattern address <2>, 0 for pattern address <3>, 2 for pattern address <4>, and The number is one for address <5>, zero for pattern address <6>, zero for pattern address <7>, and one for pattern address <8>.

The count value of the counter unit 17 is output to the maximum count value storage unit 22 for each pattern address. The maximum count value storage unit 22 compares the stored maximum count value with the newly input count value (S3).
6) When the maximum count value during storage is equal to or greater than the count value, the maximum count value during storage is held as it is, and when the maximum count value during storage is less than the count value, the count value is stored again as the maximum count value. I do. Therefore, in the first round of the AND operation, the count value “2” for the pattern address <4> is held by the maximum count value storage unit 22.

The maximum count point address storage unit 23 stores a pattern address corresponding to the count value stored in the maximum count value storage unit 22. That is, in the first round of the AND operation, the pattern address <4> is held in the maximum count point address storage unit 23. Further, the maximum count point flag storage unit 24 stores the pattern address I stored in the maximum count point address storage unit 23.
DDQ failure detection data is held. That is, the first
In the round AND operation, the ID of the pattern address <4>
The DQ failure detection data “101” is held in the count maximum point flag storage unit 24.

A series of processes in the above-described maximum count value storage unit 22, maximum count point address storage unit 23, and maximum count point flag storage unit 24 are performed in S37.

In S36, the maximum count value storage unit 2
When the maximum count value stored in the second address is not less than the count value, that is, when the maximum count value is equal to or more than the count value, the process proceeds to S38, and whether the current address stored in the current address storage unit 21 is the last pattern address, In other words, the final address determination unit 19 determines whether the AND operation for comparing the IDDQ failure detection data and the mask data has been performed for all pattern addresses. If the current address is not the last pattern address, the process returns to S33, and S33
Steps S38 to S38 are repeated.

On the other hand, if it is determined in S38 that the current address is the last pattern address, the process proceeds to S39.
Then, the processing end determination section 20 determines whether or not the count maximum value stored in the count maximum value storage section 22 is “0”. The fact that the count maximum value held in the count maximum value storage unit 22 is “0” means that a test pattern that can detect a stuck-at fault by the IDDQ test is not found. Conversely, the fact that the count maximum value held in the count maximum value storage unit 22 is not “0” means that at least 1
This means that a test pattern that can detect two stack-at faults by the IDDQ test has been found.

In S39, when the maximum count value held in the maximum count value storage section 22 is not "0",
Proceed to 40 and count maximum point address storage unit 23
Is read and stored in the selected address storage unit 26. This means that the ID
The number of stuck-at faults that can be detected by the DQ test means that the largest test pattern has been selected. For example, in the first round of the AND operation, a test step of a pattern address <4> that enables two stack-at faults b-sa1 and d-sa0 to be detected by an IDDQ test is selected, and the pattern address <4> is selected. > Is stored in the selected address storage unit 26.

Subsequently, in S41, the above mask data is updated so that the stuck-at fault that can be detected in the test step of the pattern address selected in S40 is excluded from the next round of the AND operation.
Therefore, the mask pattern storage unit 25 stores the IDDQ stored in the maximum count point flag storage unit 24.
The failure detection data is read out, and the NOT
A new mask data is created by causing the AND operation unit 15 to perform a T operation and an AND operation between the result of the NOT operation and the mask data before updating.

For example, the mask data used in the first AND operation is “111”, and the IDDQ failure detection data stored in the maximum count point flag storage unit 24 is “101”. The AND operation result “010” of the NOT operation result “010” of the failure detection data “101” and the mask data “111” is the second operation result.
This becomes new mask data used in the round AND operation.

Thereafter, the process returns to S32, and by performing the same processing as described above, a test step in which the number of stack-at faults that can be detected by the IDDQ test is the next largest is selected.

For example, when an AND operation is performed on the IDDQ failure detection data shown in Table 9 and the mask data “010”,
It can be seen that the number of flags "1" is 0 for pattern addresses <1> to <7>, and the number of flags "1" is 1 for pattern address <8>. Therefore, in the second AND operation, "1" is stored as the maximum count value in the maximum count value storage unit 22, the pattern address <8> is stored in the maximum count point address storage unit 23, and the maximum count point flag The storage unit 24 stores IDDQ failure detection data “010”.

As a result, the pattern address <8> is selected and stored in the selected address storage unit 26. That is, the test step of pattern address <8> is ID
The number of stuck-at faults that can be detected by the DQ test is selected as the next highest test step.

The mask data for the third round of the AND operation includes the NOT operation result “101” of the IDDQ failure detection data “010” stored in the count maximum point flag storage unit 24 and the mask data “010” before the update. A with
It becomes “000” according to the ND operation result. Therefore, in the third round of the AND operation, the number of flags “1” becomes 0 and the value of the maximum count value storage unit 22 becomes 0 in all pattern addresses <1> to <8>. Since the determination is made in S39, all the processing in the IDDQ test pattern selection unit 10 ends.

At the stage where S18 of the flow shown in FIG. 7 has been completed, the IDDQ
Pattern addresses are arranged and stored in descending order of the number of stack-at faults that can be detected by the test. That is, in the above example, the pattern addresses are stored in the selected address storage unit 26 in the order of <4> and <8>.

At S19, the selected address storage unit 26
The selected pattern address is read out to the IDDQ test address output unit 11 from the device, and the IDDQ test address output unit 11 outputs the selected pattern address to the LSI tester 13, so that the LSI tester 13 uses only the selected pattern address. Perform IDDQ test,
At other pattern addresses, a function test is performed.

As a result, the function test pattern created in advance by the test pattern generation unit 2 is diverted, and the IDDQ test, which requires more time than the function test, is performed only by the minimum necessary test steps. The time required for a quality test of a large-scale integrated circuit can be significantly reduced.

For example, in the above example, the timing image when the LSI tester 13 executes a test step on the logic circuit 50 is as shown in FIG. This timing image assumes that the function test requires 100 [ns] per test step, and the IDDQ test includes the time required for the power supply current to stabilize. It takes 10 [μs] per time.

As shown in the timing image, L
The SI tester 13 performs the IDDQ test only for the test steps of the pattern addresses <4> and <8>. As a result, the total test time is 20.6 [μs].
This is the IDDQ for all eight test steps.
The test time is significantly reduced as compared with the required time of 80 [μs] when the test is performed.

Returning to the flow shown in FIG. 7, in S20,
The failure detection scale calculation unit 30 calculates a failure detection scale when the function test using the functional test pattern created by the test pattern generation unit 2 is combined with the IDDQ test in the test step selected in S18. The calculation result is output to the failure detection scale calculation unit 30.
Are output to the failure detection scale storage unit 32 and stored in the failure detection scale storage unit 32.

More specifically, the failure detection scale calculation unit 30 calculates
From the mask data stored in the mask pattern storage unit 25, the number of remaining stack-at faults i that cannot be detected even by the IDDQ test is known, and the fault detection scale = 1− A failure detection scale is calculated using an expression represented by (i / j).

In the above example, the final mask data is “0”.
00 ”, the failure detection scale calculation unit 30 determines that there is no“ 1 ”in the final mask data, that is, the mask flag“ 1 ”is 0, and substitutes 0 for the remaining number of stuck-at failures i. Since the total number j of the stack-at faults is 18, the fault detection scale is 1- (i / j).
= 1− (0/18) = 1, that is, 100.0 [%]. Therefore, as a failure detection scale, 100.0
[%] Is stored in the failure detection scale storage unit 32.

As a result, the failure detection rate (83.3%) when only the above-described function test is performed is reduced by the IDD.
It can be seen that the improvement was achieved by combining the Q test.

If the final mask data is "10"
0 ”, the remaining number of stuck-at faults i is 1
From the above equation, the detected failure scale is 1- (1/1)
8) ≒ 0.944, that is, 94.4%. Therefore, 94.4 [%] is stored in the failure detection scale storage unit 32 as the failure detection scale.

Finally, in S21, the undetected fault report output unit 31 determines the position and state of the stuck-at fault that cannot be detected by the IDDQ test from the mask data stored in the mask pattern storage unit 25. The position and the state are output to the undetected failure report storage unit 33 as an undetected failure report, and are stored in the undetected failure report storage unit 33.

In the above example, the final mask data is "10
If it is 0 ", it is determined from Table 9 that b-sa1 is the position and state of the stack-at fault to be output to the undetected fault report storage unit 33 as the undetected fault report.

As described above, when S21 ends, all the processing in the test apparatus 1 ends.

In the above example, the final mask data is “000”, and as a result, the failure detection scale is 10
Although the case where it is 0.0 [%] has been described, an example where the failure detection scale does not become 100.0 [%] will also be briefly described. From the following description, it will be understood that whether or not the final failure detection scale becomes 100.0 [%] depends on the function test pattern prepared first.

For example, a functional test pattern composed of test steps of pattern addresses <1> to <6> excluding the test steps of pattern addresses <7> and <8> from the functional test patterns shown in Table 3 is a test pattern. It is assumed that it is first prepared by the pattern generation unit 2.

In this case, since the test steps for pattern addresses <7> and <8> are eliminated in the stack-at fault detection list shown in Table 5, the above-mentioned stack-at fault b which is not detected by the function test pattern in Table 3 In addition to -sa1, c-sa1, and d-sa0, stack-at faults a-sa1, c-sa0, d-sa1, f-sa0, g-sa1, and h-sa0
Is added as an undetected fault.

When an IDDQ fault detection condition table as shown in Table 8 is created for these nine undetected faults, the result is as shown in Table 10 below.

[0148]

[Table 10]

Next, based on a comparison between the IDDQ failure detection condition table of Table 10 and the logical value tables of the pattern addresses <1> to <6> shown in Table 4, the IDDQ failure detection data as shown in Table 9 is obtained. When the table is created, it is as shown in Table 11 below.

[0150]

[Table 11]

Using the IDDQ failure detection data table shown in Table 11, the test step selection processing in S31 to S41 is executed, and the pattern address <5>,
<4> and <6> are stored in the selected address storage unit 26 in this order. When the final mask data output from the mask pattern storage unit 25 becomes “000100001”, the maximum count value held in the maximum count value storage unit 22 becomes “0”.

The undetected fault report output unit 31 receives the mask data “000100001” from the mask pattern storage unit 25, and outputs the fourth stack-at fault c- in the IDDQ fault detection data table shown in Table 11.
ID of sa1 and ninth stack-at fault h-sa0
It is determined that a stack-at fault that cannot be detected even by the DQ test. Therefore, the stuck-at fault c-
sa1 and h-sa0 are output to the undetected failure report storage unit 33 and stored as undetected failure reports.

Note that the fault detection scale of this example is obtained assuming that i = 2 and j = 18 in accordance with the above-mentioned formula, and the fault detection scale = 1− (i / j) = 1− (2/18) ≒ 8
8.9%.

As described above, the test apparatus 1 according to the present invention
By using mask data used for selecting a test step for performing an IDDQ test, a function is provided for easily pointing out the position and state of a stack-at fault that cannot be detected by the IDDQ test.

As described above, the test apparatus 1 according to the present invention performs an IDDQ test on an integrated circuit in which a failure cannot be found in a function test while focusing on a failure location in which the failure cannot be found in a function test.
Since the test step that enables the failure to be detected in the test is selected from the function test patterns created for the function test, there is no need to create a test pattern for the IDDQ test from scratch. As a result, the failure detection rate per time can be increased, and defective products having a failure can be efficiently eliminated.

In the above-described test apparatus 1, the ID
The undetected fault report output from the undetected fault report output unit 31 makes it easy to know which part of the integrated circuit includes a fault that remains even after the DQ test is combined. Therefore, IDDQ
It is also possible to easily add a test pattern for eliminating a fault that remains even after the tests are combined. Furthermore, since the final failure detection rate can be known from the output of the failure detection scale calculation unit 30, IDD
Quantitative quality evaluation when the Q test is combined becomes possible.

The NA used in the logic circuit 50 is
Although only two types of logic circuits, ND circuits 51 and 52 and NOR circuits 53 and 54, have been specifically described,
It goes without saying that the test method of the present invention can be applied even if other logic circuits are used.

Note that the integrated circuit test apparatus according to the present invention may be configured as follows.

That is, the test apparatus for a CMOS integrated circuit operates on the internal circuit or the internal node of the CMOS integrated circuit to input a test pattern giving one or the other logical value, and to supply the power supply current for each test pattern step. Of a CMOS integrated circuit which measures a plurality of functional test patterns, and generates a plurality of preset functional test patterns; Fault simulation means (fault simulator 3) for verifying how much a stack-at (degeneration) fault inside a CMOS integrated circuit can be detected when a functional test pattern is input, and a fault simulation result and a list of all faults. Failure not detected in the function test using the above test pattern And output means of the extracted undetected fault list (fault simulator 3), the individual undetected fault I
IDDQ to determine conditions for detection in DDQ test
Failure detection condition setting means (IDDQ failure detection condition setting unit 5) and logic simulation means (logic) for determining a logic value of an internal signal node of the CMOS integrated circuit when a function test pattern generated from the test pattern generation means is input. Simulator 6), internal signal fetching means (node logical value storage unit 7) for reading internal signal values of logic simulation, and IDDQ failure detection conditions and internal signal values to determine whether or not they can be detected by an IDDQ test. IDDQ failure detection availability determination means (IDDQ failure detection availability determination section 8), a determination result storage means (determination result storage section 9) for storing the result determined by the IDDQ failure detection availability determination section, and the most effective IDDQ IDDQ test address selection means (IDDQ test pattern) for sequentially selecting test points And a down selection unit 10) and the.

According to the above configuration, a stack-at fault that cannot be detected by a plurality of test patterns generated by the test pattern generating means, that is, an undetected fault, can be obtained by the fault simulation means.

The IDDQ fault detection condition setting means associates the undetected fault of the stack-at fault model obtained by the fault simulation means with the short-circuit fault model of the transistor used in the IDDQ test, and detects the fault. Set the signal conditions of the internal circuit. Further, the IDDQ failure detection condition setting means sets detection conditions for all undetected failures.

After setting the IDDQ failure detection condition, the signal value of the internal circuit in each step of the test pattern is obtained by the logic simulation means and the internal signal fetch means.

The IDDQ failure detection availability determination means determines whether each undetected failure can be detected in each step of the test pattern, and writes information on the detection availability into the determination result storage means.

After execution of all steps of the test pattern,
The IDDQ test address selecting means sequentially selects the steps capable of detecting the most undetected failures from the IDDQ failure detection availability information of each step, and determines the IDDQ test points. This processing has a function of masking an undetected fault that can be detected by the already selected step and a function of counting the number of remaining undetected faults that have not been detected yet.

In this way, after selecting all test points that can be detected by the IDDQ test due to a failure that has not been detected in the function test, the addresses of all the steps for performing the IDDQ test are output.

Even when the integrated circuit test apparatus according to the present invention is configured as described above, the function test pattern is
Since the IDDQ test points are narrowed down and the integrated circuit is tested using a very simple algorithm so as to divert the test time to the Q test, defects of the integrated circuit can be most effectively rejected.

[0167]

As described above, the test method for an integrated circuit according to the first aspect of the present invention is a method for testing a test pattern for a logic function test composed of a plurality of test steps having different combinations of logic values. It is created based on the configuration of the integrated circuit and a plurality of test points set on the integrated circuit, and a simulation using the created test pattern is used to extract undetected fault points from which the faults cannot be detected among the test points. For the undetected fault point, a test step for providing a combination of logical values that can detect the fault when the quiescent power supply current is measured is selected from the test pattern. While performing a logical function test at test points other than the undetected failure point A.

Therefore, by diverting the test pattern created for the logical function test, the processing required for preparing the test pattern can be simplified, and the processing time can be shortened. Furthermore, since the measurement of the quiescent power supply current, which requires more time than the logic function test, is performed only for the undetected fault points, the test time is much longer than when a failure is detected only by measuring the quiescent power supply current for all test points. Can be shortened. In addition, as a result of measuring the quiescent power supply current in addition to the logic function test, various effects that the failure detection rate by the logic function test can be surely improved can be obtained.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the test method of the integrated circuit is designed to minimize the number of test steps used for measuring the quiescent power supply current. , A test step is selected from the test patterns.

Therefore, when a plurality of test steps that can detect a fault by measuring the quiescent power supply current correspond to one undetected fault point, the quiescent power supply current is measured for the same undetected fault point. It is possible to avoid performing a duplicate test by This allows
According to the test method of the first aspect, the test time can be further reduced.

According to a third aspect of the present invention, in addition to the configuration of the first or second aspect, when the test step is selected from the test patterns, the method further comprises the steps of: For each test step, count the number of undetected fault points where a fault can be detected by measuring the quiescent power supply current, select the test step with the maximum count value, and select the undetected fault that can be detected by the selected test step In this configuration, the failure point is excluded from the next count repeatedly.

Therefore, in one selected test step, the presence / absence of a failure at as many undetected failure points as possible can be checked, and the next selected test step is the same as the already selected test step. Since it is possible to avoid waste such as inspecting a failure point, it is possible to further reduce the test time as compared with the test method according to claim 1, and to implement a test that further embodies the test method according to claim 2. There is an effect that a method can be provided.

The test apparatus for an integrated circuit according to the fourth aspect of the present invention, as described above, integrates a test pattern for a logical function test composed of a plurality of test steps having different combinations of logical values into an integrated circuit to be inspected. Test pattern creation means created based on a circuit configuration and a plurality of test points set on an integrated circuit, and an undetected failure point at which a failure cannot be detected among the test points by a simulation using the created test pattern. Fault detection means for extracting the minimum combination of logical values that can detect the fault when the quiescent power supply current is measured for the undetected fault point; and the test pattern Is input to the above integrated circuit, the logical value indicated by each test point is By comparing the combination of the logic value determined by the logic simulation means determined for each step and the logic value determined by the fault detection condition setting means with the logic value of each test point determined by the logic simulation means, the static power supply current can be measured. Test pattern selecting means for selecting a test step from the test patterns so as to minimize the number of test steps to be used.

Therefore, the quiescent power supply current is measured using the selected test step, and a fault that cannot be detected by the logic function test is detected. Therefore, compared with the case where only the logic function test is performed using the test pattern, The failure detection rate can be reliably improved. In addition, by diverting the test pattern created for the logic function test, the processing required for preparing the test pattern can be simplified, and the processing time required for preparing the test pattern can be reduced. Furthermore, since the measurement of the quiescent power supply current, which requires more time than the logic function test, is performed only for the undetected fault points, the test time is much longer than when a failure is detected only by measuring the quiescent power supply current for all test points. Can be also shortened.

According to a fifth aspect of the present invention, as described above, in addition to the configuration of the fourth aspect, the test pattern selecting means can detect a failure by measuring a quiescent power supply current. When selecting the test steps with the largest number of undetected fault points in order, the undetected fault points that can be detected by measuring the quiescent power supply current using the already selected test steps are excluded from the selection of the next test step. Mask data generating means for generating mask data for performing the operation, and based on the final mask data at the time when the test pattern selecting means completes the selection of all the test steps, cannot be detected even by measuring the static power supply current. An undetected failure determining means for determining a detected failure point is connected to the mask data generating means.

Therefore, the position and the state of the undetected fault which cannot be detected even by measuring the quiescent power supply current are specified by using the mask data prepared for selecting the test step used for measuring the quiescent power supply current. In addition to the effect of the configuration of claim 4, it is possible to very easily specify the position and state of such a fault that is finally undetected.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing one configuration example of a test device for an integrated circuit according to the present invention.

FIG. 2 is a flowchart showing an overall rough processing flow in one embodiment of the integrated circuit test method according to the present invention.

FIG. 3 is a block diagram illustrating an example of an internal configuration of an IDDQ test pattern selection unit illustrated in FIG. 1;

FIG. 4 is a circuit diagram showing a specific example of an integrated circuit to which the test method of the present invention is applied.

FIGS. 5A and 5B are circuit diagrams of a NAND circuit composed of MOS transistors.

FIGS. 6A and 6B are circuit diagrams of a NOR circuit composed of MOS transistors.

FIG. 7 is a flowchart showing one embodiment of a processing flow in the integrated circuit test method according to the present invention.

FIG. 8 is a flowchart showing a flow of a process of selecting a test step used for an IDDQ test in S18 of FIG. 7;

FIG. 9 is an explanatory diagram showing a timing image of each test step by the integrated circuit test method according to the present invention.

FIG. 10 is a flowchart illustrating a conventional example of a process of creating an IDDQ test pattern based on a function test pattern.

[Description of Signs] 1 Test apparatus 2 Test pattern generation unit (test pattern creation unit) 3 Failure simulator (failure simulation unit) 5 IDDQ failure detection condition setting unit (failure detection condition setting unit) 6 Logic simulator (logic simulation unit) 8 IDDQ failure detection availability determination unit (test pattern selection unit) 9 determination result storage unit (test pattern selection unit) 10 IDDQ test pattern selection unit (test pattern selection unit) 25 mask pattern storage unit (mask data generation unit) 31 undetected failure Report output unit (undetected failure determination means) 50 Logic circuit (integrated circuit) a Input terminal (test point) b Input terminal (test point) c Input terminal (test point) d Input terminal (test point) e Input terminal (test point) f Node (test point) g Node (test point) h Node (test point) z Output terminal (test point)

Claims (5)

[Claims] 1. A test pattern for a logic function test comprising a plurality of test steps having different combinations of logic values based on a configuration of an integrated circuit to be inspected and a plurality of test points set on the integrated circuit. A non-detected fault point in which a fault cannot be detected is extracted from the test points by a simulation using the generated test pattern, and the fault is detected when the quiescent power supply current is measured for the undetected fault point. A test step for providing a combination of logical values that can be detected is selected from the test pattern, and a quiescent power supply current is measured for the undetected fault point, while a logic function test is performed for test points other than the undetected fault point. A test method for an integrated circuit. 2. The test method for an integrated circuit according to claim 1, wherein the test steps are selected from the test patterns so that the number of test steps used for measuring the quiescent power supply current is minimized. 3. When the test step is selected from the test patterns, the number of undetected fault points at which a fault can be detected by measuring the quiescent power supply current is counted for each test step. 3. The method for testing an integrated circuit according to claim 1, further comprising: selecting a test step to be performed, and excluding an undetected fault point that can be detected by the selected test step from a next count. . 4. A test pattern for a logic function test composed of a plurality of test steps having different combinations of logical values based on a configuration of an integrated circuit to be inspected and a plurality of test points set on the integrated circuit. Test pattern creating means for creating a test pattern, a failure simulation means for extracting an undetected fault point from which a failure cannot be detected among the test points by simulation using the created test pattern, and a static power supply for the undetected fault point. Fault detection condition setting means for obtaining a minimum combination of logical values that can detect the fault when the current is measured; and when the test pattern is input to the integrated circuit,
A logic simulation means for determining a logic value indicated by each test point for each test step, a combination of a logic value obtained by the fault detection condition setting means and a logic value of each test point obtained by the logic simulation means are compared. A test pattern selecting means for selecting a test step from the test pattern so that the number of test steps used for measuring the quiescent power supply current is minimized. . 5. The method according to claim 1, wherein the test pattern selecting means selects a test step in which the number of undetected fault points at which a fault can be detected by measuring the quiescent power supply current in descending order. Mask data generation means for generating mask data for excluding undetected fault points that can be detected by measuring current from the selection of the next test step is provided, and the test pattern selection means completes the selection of all test steps Based on the final mask data at the point of time, an undetected failure determination unit that determines an undetected failure point that cannot be detected even by measuring the static power supply current is connected to the mask data generation unit. An integrated circuit test apparatus according to claim 4.