JPH01156680A - Fault diagnosing method for logic circuit - Google Patents
Fault diagnosing method for logic circuitInfo
- Publication number
- JPH01156680A JPH01156680A JP62315366A JP31536687A JPH01156680A JP H01156680 A JPH01156680 A JP H01156680A JP 62315366 A JP62315366 A JP 62315366A JP 31536687 A JP31536687 A JP 31536687A JP H01156680 A JPH01156680 A JP H01156680A
- Authority
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- Prior art keywords
- fault
- probability
- external output
- output terminal
- fault detection
- Prior art date
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Links
- 238000000034 method Methods 0.000 title claims description 14
- 238000001514 detection method Methods 0.000 claims abstract description 25
- 238000003745 diagnosis Methods 0.000 claims abstract description 16
- 238000004088 simulation Methods 0.000 claims abstract description 12
- 230000007547 defect Effects 0.000 claims description 3
- 238000012360 testing method Methods 0.000 abstract description 6
- 238000007689 inspection Methods 0.000 abstract 1
- 238000012545 processing Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000011161 development Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 210000004899 c-terminal region Anatomy 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
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- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） この発明は論理集積回路に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to logic integrated circuits.
（従来の技術）
論理回路の故障診断において通常知られている方法では
、故障シミュレーションにより故障辞書を作成し、テス
ターからの故障検出情報に基づき故障辞書を検索する。(Prior Art) In a commonly known method for fault diagnosis of logic circuits, a fault dictionary is created by fault simulation, and the fault dictionary is searched based on fault detection information from a tester.
故障辞書には特定の故障が何番目のテストパターンで検
出され、その時何番目の外部出力端子で正常回路と故障
回路に差異が生じるかが示されている。故障辞書の作成
に要する時間と故障辞書の検索に要する時間は回路規模
の増大と共に急激に増大し、最近のＶＬＳＩに対しては
適用不可能になりつつある。The fault dictionary indicates at which test pattern a specific fault is detected and at which external output terminal a difference occurs between a normal circuit and a faulty circuit. The time required to create a fault dictionary and the time required to search a fault dictionary increases rapidly as the circuit scale increases, and this method is becoming inapplicable to recent VLSIs.
故障シミュレーションを高速化する目的で確率的故障シ
ミュレータ（例えば昭和６２年電子情報通信学会創立７
０周年記念総合全国大会論文集Ｐ、２−１２１、中沢、
平林：確率的故障シミュレータの開発）が開発されたが
、この方法は故障がどの出力端子で検出されるかの情報
を与えないため、故障辞書の作成には使えない。Probabilistic fault simulators (for example, the Institute of Electronics, Information and Communication Engineers was founded in 1985) were developed for the purpose of speeding up fault simulation.
0th Anniversary Comprehensive National Conference Proceedings P, 2-121, Nakazawa,
Hirabayashi: Development of a Stochastic Fault Simulator) was developed, but this method cannot be used to create a fault dictionary because it does not provide information on which output terminal a fault is detected at.
また故障辞書の検索時間を短縮する方法も知られていな
い。Furthermore, there is no known method for shortening the time required to search a fault dictionary.
（発明が解決しようとする問題点）
この、発明の目的は前項記載の故障辞書作成と故障辞書
検索に要する時間を削減し、故障診断に要する時間を飛
羅的に短縮することにある。(Problems to be Solved by the Invention) The purpose of the invention is to reduce the time required for fault dictionary creation and fault dictionary search as described in the previous section, and to dramatically shorten the time required for fault diagnosis.
（問題点を解決するための手段）
先ず、この発明で使用する正常回路のシミュレーション
結果から故障検出確率を算出する方法を前記論文（中沢
、平林：確率的故障シミュレータの開発）に基いて説明
する。第２図に確率的故障シミュレーションの処理フロ
ーを示す。正常回路の各ノードをＯに制御する確率、Ｃ
Ｏと１に制御する確率、Ｃ１をシミュレーション結果か
らＣＯ＝ （論理値がＯになるステップ数）／（総ステ
ツプ数）Ｃ１＝（論理値が１になるステップ数）／（総
ステツプ数）によって算出する。第３図を例にしてノー
ドＡの０を観測する確率、ＢＯ（Ａ）と１を観測する確
率Ｂ１（Ａ）を求めると
ＢＯ（Ａ） ＝ＢＯ（０）・Ｐ（Ａ＝０．Ｂ＝１．Ｃ＝
１ ＞ ／Ｃｏ（Ａ）。(Means for solving the problem) First, a method for calculating the failure detection probability from the simulation results of a normal circuit used in this invention will be explained based on the above paper (Nakazawa, Hirabayashi: Development of a Stochastic Failure Simulator). . Figure 2 shows the processing flow of stochastic failure simulation. Probability of controlling each node of a normal circuit to O, C
The probability of controlling O and 1, C1, is calculated from the simulation results by CO = (number of steps where the logical value becomes O) / (total number of steps) C1 = (number of steps where the logical value becomes 1) / (total number of steps) calculate. Using Fig. 3 as an example, find the probability of observing 0 at node A, BO(A), and the probability B1(A) of observing 1: BO(A) = BO(0)・P(A=0.B =1.C=
1>/Co(A).
８１ （Ａ） ＝ Ｂｌ （０）・Ｐ（Ａ＝１．Ｂ＝１
．Ｃ＝ １ ） ／Ｃ１（Ａ）。81 (A) = Bl (0)・P(A=1.B=1
．． C=1)/C1(A).
となるる。但し。It becomes. however.
Ｐ（Ａ＝０．Ｂ＝ｌ、Ｃ＝１）＝（Ａ＝０．Ｂ＝ｌ、Ｃ
＝１になるステップ数）／（総ステツプ数）。P(A=0.B=l, C=1)=(A=0.B=l, C
= 1 (number of steps)/(total number of steps).
Ｐ（Ａ＝１．Ｂ＝１’、Ｃ＝１）＝（Ａ＝１．Ｂ＝１．
Ｃ＝１になるステップ数）／（総ステツプ数）。P(A=1.B=1', C=1)=(A=1.B=1.
number of steps for which C=1)/(total number of steps).
である。確率的故障シミュレーションでは外部出力端子
でｆｉｌ １１１ｇ確率を無条件に１としている。即ち
、第４図においてノードＤが外部出力端子とすればＢＯ
（Ｄ）＝ １ 、 Ｂｌ（Ｄ）＝ １ 。It is. In the stochastic failure simulation, the fil 111g probability is unconditionally set to 1 at the external output terminal. That is, in FIG. 4, if node D is an external output terminal, BO
(D)=1, Bl(D)=1.
である。ステップ当りの故障検出確率は制御確率と観測
確率から計算される。例えば、第４図においてノードＡ
の０縮退故障のステップ当りの検出確率、Ｄｏ（Ａ）と
１縮退故障のステップ当りの検出確率、Ｄｉ（Ａ）は
ＤＯ（Ａ） ＝ＣＩ（Ａ）・Ｂｌ（Ａ） 。It is. The fault detection probability per step is calculated from the control probability and observation probability. For example, in FIG.
The detection probability per step of a stuck-at-0 fault, Do(A), and the detection probability per step of a stuck-at-1 fault, Di(A), are DO(A) = CI(A)·Bl(A).
ＤＩ（Ａ） ＝Ｃ０（Ａ）・ＢＯ（Ａ） 。DI(A) = C0(A)・BO(A).
で求められる。さらにＮステップのテストパターンでの
故障検出確率は、ノードＡのＯ縮退故障に対して
Ｐｓａｏ（Ａ） ＝ １− （１−ＤＯ（Ａ））Ｎ１縮
退故障に対して
Ｐｓａｏ（Ａ） ＝ １− （１−Ｄｏ（Ａ））Ｎとな
る。上記の故障検出確率は与えられたテストパターンで
故障が外部出力端子のどれかで検出される確率を意味し
ている。一方、故障診断の場合は特定の不良回路の不良
原因をＬＳＩテスターからの故障検出情報に基き固定す
ることになり、故障がどの外部出力端子で検出されたか
は確定している。そこで、この発明で主張する故障診断
法では、ＬＳＩテスターからの故障検出確率報において
、外部出力端子が正常回路の場合にＯ１故障回路の場合
に１のとｊＢＯ＝１とし、正常回路の場合に１、故障回
路の場合にＯのときＢ１＝１として、これらに該当しな
い場合はＢＯ＝ Ｏ、Ｂ１＝ Ｏとして故障検出確率を
算出する。処理フローを第１図に示す。その結果、故障
検出確率が０．５以上になる故障が不良原因の候補とい
うことになる。is required. Furthermore, the fault detection probability in the N-step test pattern is Psao(A) = 1- (1-DO(A)) for the O stuck-at fault at node A, and Psao(A) = 1- for the N1 stuck-at fault. (1-Do(A))N. The above fault detection probability means the probability that a fault will be detected at any of the external output terminals in a given test pattern. On the other hand, in the case of fault diagnosis, the cause of a fault in a particular faulty circuit is fixed based on fault detection information from an LSI tester, and it is determined at which external output terminal the fault was detected. Therefore, in the fault diagnosis method claimed in this invention, in the fault detection probability report from the LSI tester, if the external output terminal is a normal circuit, O1 is set to 1 in the case of a faulty circuit, and jBO = 1, and in the case of a normal circuit, 1. In the case of a faulty circuit, when O is set, B1=1 is set, and when these do not apply, BO=O and B1=O are set to calculate the fault detection probability. The processing flow is shown in FIG. As a result, a fault with a fault detection probability of 0.5 or more is a candidate for the cause of the defect.
（作 用）
前項の説明から明らかなように、この発明ではＬＳＩテ
スターからの故障検出情報により外部出力端子の観測確
率を決定し、正常回路のシミュレーション結果と合せて
故障検出確率を算出し、それにより故障診断するために
、通常の故障診断法における故障辞書作成と故障辞書検
索のように処理時間を要する作業が、いずれも不必要に
なり、故障診断時間が大幅に短縮される。(Function) As is clear from the explanation in the previous section, in this invention, the observation probability of the external output terminal is determined based on the failure detection information from the LSI tester, and the failure detection probability is calculated by combining it with the simulation result of a normal circuit. In order to perform fault diagnosis using this method, operations that require processing time, such as fault dictionary creation and fault dictionary search in normal fault diagnosis methods, are no longer necessary, and the fault diagnosis time is significantly shortened.
（実施例）
この発明の故障診断法を第４図の半加算器を例にして説
明する。Ｘ、Ｙは外部入力端子、Ｓ、Ｃは外部出力端子
とする。正常回路の動作は第５図の通りである。ＬＳＩ
テスターからＣの端子では故障は検出されず、Ｓの端子
において最初のテストパターンで正常回路がＯ１故障回
路が１になることがわかったとすれば、第１図の処理フ
ローに従って算出した故障検出確率は第６図のようにな
る。故障検出確率が０．５以上の故障は不良原因の候補
であるが、その条件だけからすればＳが１に縮退した故
障（Ｓａ工（Ｓ））も候補である。ところがＳａｔ （
Ｓ））の場合は全てのテストパターンでＳが１となり、
ＬＳＩテスターからの情報に反するために候補から除外
する。残る候補はＳａｏ （Ｘ） −Ｓａ□（Ｘ）。(Example) The fault diagnosis method of the present invention will be explained using the half adder shown in FIG. 4 as an example. X and Y are external input terminals, and S and C are external output terminals. The operation of the normal circuit is as shown in FIG. LSI
If the tester finds that no fault is detected at the C terminal, and that the normal circuit is O1 and the faulty circuit is 1 at the S terminal in the first test pattern, then the fault detection probability calculated according to the processing flow in Figure 1 is is as shown in Figure 6. A fault with a fault detection probability of 0.5 or more is a candidate for the cause of the defect, but based on that condition alone, a fault in which S degenerates to 1 (Sa(S)) is also a candidate. However, Sat (
In the case of S)), S becomes 1 for all test patterns, and
It is excluded from the candidates because it contradicts the information from the LSI tester. The remaining candidates are Sao (X) −Sa□(X).
５ａ１（Ｙ） 、５ａｏ（Ｅ） 、Ｓａ、（Ｅ）、 ５
ａｏ（Ｆ）、 ｓａ、（ｃ）にしばられる。5a1(Y), 5ao(E), Sa, (E), 5
It is bound by ao (F), sa, and (c).
故障検出確率を正常回路の論理シミュレーション結果か
ら算出する手段と、ＬＳＩテスターからの故障検出情報
から外部出力端子のｖＡ測確率を決定する手段により、
通常の故障診断法における故障辞書作成と故障辞書作成
と故障辞書検索の作業を不必要にし、故障診断時間を大
幅に短縮することができる。By means of calculating the failure detection probability from the logical simulation results of a normal circuit and by means of determining the vA measurement probability of the external output terminal from the failure detection information from the LSI tester,
This makes it unnecessary to create a fault dictionary, create a fault dictionary, and search the fault dictionary in a normal fault diagnosis method, thereby significantly shortening the fault diagnosis time.
第１図は、この発明の処理フローを示す図、第２図は確
率的故障シミュレーションの処理フローを示す図、第３
図はＡＮＤゲートの例を示す図。
第４図は半加算器の例を示す図、第５図は半加算器の動
作例を示す図、第６図は故障診断のための故障検出率算
出結果を示す図である。
代理人 弁理士 則 近 憲 佑
同 松山光之
第１図
第２図
第３図
ＸＹＥＦ Ｇ ＳＣ
θ θ ｆｆｆ θ θ
θ １ ｆ θ θ ｆ θ
ｆ θ ρ ｆｏ ｌ θ
ｆｆ θ ０ θ Ｏｆ
第５図FIG. 1 is a diagram showing the processing flow of the present invention, FIG. 2 is a diagram showing the processing flow of stochastic failure simulation, and FIG.
The figure shows an example of an AND gate. FIG. 4 is a diagram showing an example of a half adder, FIG. 5 is a diagram showing an example of the operation of the half adder, and FIG. 6 is a diagram showing a result of calculating a fault coverage rate for fault diagnosis. Agent Patent Attorney Yudo Ken Chika Mitsuyuki Matsuyama Figure 1 Figure 2 Figure 3
Claims (3)
障が検出された外部出力端子でのみ観測確率を１とし、
他の外部出力端子では観測確率を０として故障検出確率
を正常回路の論理シミュレーション結果から算出する手
段を有し、故障検出確率を用いて不良原因を特定するこ
とを特徴とする論理回路の故障診断方法。(1) Based on the fault detection information from the LSI tester, the observation probability is set to 1 only at the external output terminal where a fault has been detected,
Fault diagnosis of a logic circuit characterized in that other external output terminals have means for calculating a fault detection probability from the logic simulation results of a normal circuit with an observed probability of 0, and the fault detection probability is used to identify the cause of a failure. Method.
場合に１のとき０を観測する確率を１とし、正常回路の
場合に１、故障回路の場合に０のとき１を観測する確率
を１とし、それ以外の場合の観測確率を０とすることを
特徴とする特許請求の範囲第１項記載の論理回路の故障
診断方法。(2) The probability of observing 0 when the external output terminal is 0 when it is a normal circuit and 1 when it is a faulty circuit is set to 1, and 1 is observed when it is 1 when the external output terminal is a normal circuit and 0 when it is a faulty circuit. 2. The fault diagnosis method for a logic circuit according to claim 1, wherein the probability is set to 1, and the observed probability is set to 0 in other cases.
良原因の候補とすることを特徴とする特許請求の範囲第
１項記載の論理回路の故障診断方法。(3) A fault diagnosis method for a logic circuit according to claim 1, characterized in that a fault with a calculated fault detection probability of 0.5 or more is considered as a candidate for a cause of a defect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62315366A JPH01156680A (en) | 1987-12-15 | 1987-12-15 | Fault diagnosing method for logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62315366A JPH01156680A (en) | 1987-12-15 | 1987-12-15 | Fault diagnosing method for logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01156680A true JPH01156680A (en) | 1989-06-20 |
Family
ID=18064546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62315366A Pending JPH01156680A (en) | 1987-12-15 | 1987-12-15 | Fault diagnosing method for logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01156680A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6205559B1 (en) | 1997-05-13 | 2001-03-20 | Nec Corporation | Method and apparatus for diagnosing failure occurrence position |
| US6301685B1 (en) | 1997-11-19 | 2001-10-09 | Nec Corporation | Error propagation path extraction system, error propagation path extraction method, and recording medium recording error propagation path extraction control program |
| US6308293B1 (en) | 1997-09-30 | 2001-10-23 | Nec Corporation | Fault diagnosis apparatus and recording medium with a fault diagnosis program recorded thereon |
| US20130297049A1 (en) * | 2011-03-29 | 2013-11-07 | Mitsubishi Electric Corporation | Abnormality diagnosis device and abnormality diagnosis system for servo control device |
-
1987
- 1987-12-15 JP JP62315366A patent/JPH01156680A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6205559B1 (en) | 1997-05-13 | 2001-03-20 | Nec Corporation | Method and apparatus for diagnosing failure occurrence position |
| US6308293B1 (en) | 1997-09-30 | 2001-10-23 | Nec Corporation | Fault diagnosis apparatus and recording medium with a fault diagnosis program recorded thereon |
| US6301685B1 (en) | 1997-11-19 | 2001-10-09 | Nec Corporation | Error propagation path extraction system, error propagation path extraction method, and recording medium recording error propagation path extraction control program |
| US20130297049A1 (en) * | 2011-03-29 | 2013-11-07 | Mitsubishi Electric Corporation | Abnormality diagnosis device and abnormality diagnosis system for servo control device |
| US9348332B2 (en) * | 2011-03-29 | 2016-05-24 | Mitsubishi Electric Corporation | Abnormality diagnosis device and abnormality diagnosis system for servo control device |
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