CN108120917B - Method and device for determining test clock circuit - Google Patents
Method and device for determining test clock circuit Download PDFInfo
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- CN108120917B CN108120917B CN201611075594.8A CN201611075594A CN108120917B CN 108120917 B CN108120917 B CN 108120917B CN 201611075594 A CN201611075594 A CN 201611075594A CN 108120917 B CN108120917 B CN 108120917B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The embodiment of the invention discloses a method and a device for determining a test clock circuit, wherein the method comprises the following steps: grouping the circuits to obtain test groups; all circuits of one said test packet use the same test clock; determining the adding position of a multiplexing unit according to the test packet, and adding the multiplexing unit at the adding position; wherein the multiplexing unit is configured to select the test signal or the functional clock and input the selected test signal or functional clock into the test packet; determining the branching positions of different transmission paths of the test clock input into one test packet according to a test clock balancing strategy and a public path maximum strategy; the test clock equalization strategy is used for enabling the transmission delay difference value of one test clock in a plurality of transmission paths to be within a preset range; the common path maximization strategy is used for maximizing a common path which is passed by one test clock when the test clock passes through a plurality of transmission paths.
Description
Technical Field
The present invention relates to the field of circuits, and in particular, to a method and an apparatus for determining a test clock circuit.
Background
A large number of clock domain crossing asynchronous circuits exist in a chip, and during fixed fault testing, the clock domain crossing asynchronous circuits are converted into synchronous paths, so that a large number of timing violation paths need to be repaired.
The current Design for Testability (DFT) clock scheme has some drawbacks: full chip equalization of the low speed test clock results in large clock tree delays. After the actual circuit is manufactured by using the designed circuit determined in the above manner, the designed circuit cannot be used as an ideal balance in the circuit determination process due to the process deviation problem, so that the On-Chip Variation (OCV) of the actual circuit is large.
Furthermore, an excessive OCV will present a large number of timing violation paths. By inserting buffers on the data path, some timing violations can be repaired, but the chip area is increased; and a part of timing violation paths can not be repaired, and the part of paths can not be tested, so that the test coverage rate of the chip is reduced.
Disclosure of Invention
It is therefore desirable to provide a method and apparatus for determining a test clock circuit, which at least partially solve the above problems
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a first aspect of an embodiment of the present invention provides a method for determining a test clock circuit, including:
grouping circuits to obtain test groups, wherein all circuits of one test group use the same test clock;
determining the adding position of a multiplexing unit according to the test packet, and adding the multiplexing unit at the adding position; wherein the multiplexing unit is configured to select the test signal or the functional clock and input the selected test signal or functional clock into the test packet;
determining the branching positions of different transmission paths of the test clock input into one test packet according to a test clock balancing strategy and a public path maximum strategy; the test clock equalization strategy is used for enabling the transmission delay difference value of one test clock in a plurality of transmission paths to be within a preset range; the common path maximization strategy is used for maximizing a common path which is passed by one test clock when the test clock passes through a plurality of transmission paths.
Based on the above scheme, the obtaining of the test packet for the circuit packet includes at least one of:
grouping according to the relation between clock domains to obtain the test grouping;
grouping according to the circuit scale to obtain the test grouping;
grouping according to interaction paths among different modules to obtain a test group;
and grouping according to the position relation among the modules to obtain a test group.
Based on the above scheme, the grouping according to the relationship between clock domains to obtain the test packet includes:
and dividing modules covered by different functional clocks into different test groups.
Based on the above scheme, the grouping according to the circuit scale to obtain the test packet includes:
and when one module comprises sub-modules using different functional clocks, and the size of the module is larger than a size threshold value, grouping the sub-modules using the different functional clocks to obtain at least two test groups.
Based on the above scheme, the grouping according to the interaction paths between different modules to obtain a test grouping includes:
dividing two modules with the number of interaction paths larger than a first preset number into one test group;
and/or the presence of a gas in the gas,
and dividing two modules, the number of interaction paths of which is less than a second preset number and different functional clocks are used, into different test packets.
Based on the above scheme, the grouping according to the position relationship between the modules to obtain the test grouping includes:
when the distance between two modules is larger than a first preset distance, dividing the two modules into different test groups;
and/or the presence of a gas in the gas,
and when the distance between the two modules is smaller than a second preset distance, dividing the two modules into the same test group.
Based on the above scheme, after obtaining the test packet, the method further includes:
adding a buffer marking the test clock on the circuit according to the test packet.
A second aspect of an embodiment of the present invention provides a test clock circuit determination apparatus, including:
a grouping unit for grouping the circuits to obtain test groups; wherein all circuits of one of the test packets use the same test clock;
an adding unit for determining an adding position of a multiplexing unit according to the test packet and adding the multiplexing unit at the adding position; wherein the multiplexing unit is configured to select the test signal or the functional clock and input the selected test signal or functional clock into the test packet;
the determining unit is used for determining the branching positions of different transmission paths in one test packet input by the test clock according to a test clock balancing strategy and a public path maximum strategy; the test clock equalization strategy is used for enabling the transmission delay difference value of one test clock in a plurality of transmission paths to be within a preset range; the common path maximization strategy is used for maximizing a common path which is passed by one test clock when the test clock passes through a plurality of transmission paths.
Based on the above scheme, the grouping unit is specifically configured to perform grouping according to a relationship between clock domains to obtain the test grouping; and/or, grouping according to the circuit scale to obtain the test grouping; and/or grouping according to interaction paths among different modules to obtain test groups; and/or grouping according to the position relation among the modules to obtain a test grouping.
Based on the above scheme, the grouping unit is specifically configured to divide the two modules covered by different functional clocks into different test groups.
Based on the above scheme, the grouping unit is specifically configured to, when one module includes sub-modules using different functional clocks, and the size of the module is greater than a size threshold, group the sub-modules using different functional clocks to obtain at least two test groups.
Based on the above scheme, the grouping unit is specifically configured to divide two modules, the number of which is greater than a first preset number, into one test group; and/or dividing two modules, the number of interaction paths of which is less than a second preset number and uses different functional clocks, into different test groups.
Based on the above scheme, the grouping unit is specifically configured to, when a distance between two modules is greater than a first preset distance, group the two modules into different test groups; and/or when the distance between the two modules is smaller than a second preset distance, the two modules are classified into the same test group.
Based on the above scheme, the apparatus further comprises:
and the marking unit is used for adding a buffer for marking the test clock on a circuit according to the test packet after the test packet is obtained.
According to the method and the device for determining the test clock circuit, when the test clock is determined, circuit grouping is carried out to obtain a plurality of test groups, the same test clock is used by circuits in one test group, and when the test clock is determined to be input to different transmission paths of one test group, the common paths passed by the test clocks in one test group on different transmission paths are maximized according to a test clock balancing strategy and a common path maximum strategy, so that the transmission of non-common paths is reduced, the problem of large delay difference caused by the transmission of the non-common paths is reduced, and the phenomenon of large OVC (over-the-horizon) applied to an actual circuit is reduced; and because of the determination of the test grouping, the OVC is reduced, so that the timing violation is reduced, and the number of buffers introduced for repairing the timing violation is reduced, so that the scale of the whole chip is reduced, and the chip area is reduced. Meanwhile, the phenomena that the coverage of the test clock is reduced and the test coverage is low due to timing sequence violation are reduced because part of the untestable paths which cannot be repaired are reduced. Therefore, the method and the device for determining the test clock circuit provided by the embodiment of the invention have the characteristics of small OCV, high test coverage rate and small chip area.
Drawings
FIG. 1 is a flowchart illustrating a method for determining a test clock circuit according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a test clock circuit determination apparatus according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating another method for determining a test clock circuit according to an embodiment of the present invention;
fig. 4 to 9 are grouping diagrams of test packets according to an embodiment of the present invention;
FIG. 10 is a diagram illustrating a test clock circuit according to an embodiment of the present invention;
fig. 11 is a schematic circuit diagram of a conventional method for designing a test clock circuit based on a functional clock circuit similar to that shown in fig. 10.
Detailed Description
The technical solution of the present invention is further described in detail with reference to the drawings and the specific embodiments of the specification.
As shown in fig. 1, the present embodiment provides a method for determining a test clock circuit, including:
step S110: grouping the circuits to obtain test groups; all circuits of one said test packet use the same test clock;
step S120: determining the adding position of a multiplexing unit according to the test packet, and adding the multiplexing unit at the adding position; wherein, the multiplexing unit is used for selecting the test signal or the functional clock to input the test packet;
step S130: determining the branching positions of different transmission paths of the test clock input into one test packet according to a test clock balancing strategy and a public path maximum strategy; the test clock equalization strategy is used for enabling the transmission delay difference value of one test clock in a plurality of transmission paths to be within a preset range; the common path maximization strategy is used for maximizing a common path which is passed by one test clock when the test clock passes through a plurality of transmission paths.
The test clock circuit determination method can also be called as a test clock circuit design method. The functional clock may be an operating clock after the circuit is determined, and the test clock may be a clock for measuring the circuit.
In this embodiment, the transmission path is a path from an input port to an output port; the two transmission paths differ at least in part. Typically the transmission input ports of the multiple transmission paths within one of said test packets are identical, but the output ports are different. For example, one of the test packets includes a transmission path a and a transmission path B; the transmission path a and the transmission path B have a part of the paths common to each other and a part of the paths separate from each other, the common part is referred to as the common path, and the separate parts are referred to as the non-common paths. In this embodiment, when the test clock is input again, the test clock may follow the common path to the maximum extent, so that the transmission path a and the transmission path B share the path and the logic gates on the path as much as possible, on one hand, the usage of the gate circuit may be reduced, and on the other hand, as the longer the common path through which the test clock passes, the shorter the non-common path through which the test clock passes, the smaller the transmission delay difference due to the non-common path, and therefore, the OVC may be reduced.
The step S110 is to group circuits, for example, the circuits include many modules, the division of the modules may be based on functions or physical distances, in short, the circuits are divided into many modules, and the circuits between the modules or within the modules are grouped.
The grouping of step S110 may include grouping circuits according to the coverage of the functional clock to obtain the test packet. Normally, the circuit covered by the same functional clock is divided into one test packet and not into two test packets. The circuit coverage of different functional clocks may be divided into one test packet or different test packets, which may depend on other parameters of the circuit, such as the circuit size of two different functional clock coverages. The circuit scale here may mean: the number of logic gates included in a module and/or the interaction paths between logic gates, etc.
The test clock used by a test packet, i.e. the test clock passed by all circuits within a test packet, comes from the same test clock. In step S120, a multiplexing unit is added according to the test packet.
Generally, the multiplexing unit includes two inputs and an output, one input is used for inputting the test clock, the other input is used for inputting the functional clock, the output is used for outputting the test clock or the functional clock, when the test is carried out, the multiplexing unit will select to output the test clock, when the circuit works normally, the multiplexing unit will select to output the functional clock, so that the circuit works normally based on the functional clock. The position of the addition of the multiplexing unit will be determined in this embodiment based on the test packet. For example, a test packet includes one input, multiple test outputs; typically the number of multiplexing units is equal to the number of test outputs. And the adding position of the multiplexing unit is the test clock, and the test clock respectively enters the fork points of different paths corresponding to different test outputs.
Of course, the adding position of the multiplexing unit is also related to the input starting position of different functional clocks in the test packet; for example, one of the test packets includes two functional clock covered circuits, and when the test clock is input to the intersection of the two functional clocks, the multiplexing unit is disposed at the intersection of the different functional clock covered circuits, so that selection of different functional clocks and test clocks in test and operation can be realized.
In a specific implementation, the step S120 may include: multiplexing units of different test packets are added respectively, and multiplexing units of transmission paths of the same test packet using different functional clocks are added respectively.
In step S130, when the circuit design is performed, not only the test clock equalization policy but also the common path maximization policy need to be followed. In this way, the common path that a test clock passes through in a test packet is the largest, so that the non-common paths are reduced, and the test delay difference caused by the inconsistency of the non-common paths is reduced.
Because circuit grouping is performed in the embodiment, test groups are obtained, and different test clocks used by different test groups are different, the phenomena of time sequence violation and large chip area increase due to the time sequence violation can be reduced, and the phenomenon of coverage rate reduction caused by unrepairable time sequence violation can be reduced.
In some embodiments, the step S110 may include at least one of:
grouping according to the relation between clock domains to obtain the test grouping;
grouping according to the circuit scale to obtain the test grouping;
grouping according to interaction paths among different modules to obtain a test group;
and grouping according to the position relation among the modules to obtain a test group.
A clock domain may be a functional clock overlay circuit, which may be understood as a clock domain, and in this embodiment, the clock domains may be grouped directly according to the relationship of the clock domains, for example, different clock domains may be divided into different test groups, or different clock domains sharing the same clock source may be divided into a test group.
The circuit scale may be determined according to the number of logic gates and connection paths between the logic gates. The data of the logic gate of the circuit included in one test group is not too large or too small, which may cause the problems of too much test clock or too many multiplexing units, and the circuit cost is increased; if the maximum strategy of the subsequent common path is satisfied, the common path passed by the test clock is little overall, and the OVC is affected.
If there are many interaction paths between two modules and many connections between logic gates of two modules, it is obvious that the two modules have close relationship and can be divided into one test packet, and if there are few interactions and different functional clocks are used, different test packets can be divided to reduce OVC as much as possible.
Specifically, the grouping according to the relationship between the clock domains to obtain the test packet includes:
and dividing modules covered by different functional clocks into different test groups.
Specifically, the grouping according to the circuit scale to obtain the test packet includes:
and when one module comprises sub-modules using different functional clocks, and the size of the module is larger than a size threshold value, grouping the sub-modules using the different functional clocks to obtain at least two test groups.
Specifically, as described above, the grouping according to the interaction paths between different modules to obtain a test group includes: dividing two modules with the number of interaction paths larger than a first preset number into one test group; and/or dividing two modules, the number of interaction paths of which is less than a second preset number and uses different functional clocks, into different test groups.
Here, the first preset number and the second preset number are both preset thresholds, and usually the first preset number is larger than the second preset data.
Specifically, as described above, the grouping according to the position relationship between the modules to obtain the test group includes:
when the distance between the two modules is larger than a preset distance, dividing the two modules into different test groups;
and/or the presence of a gas in the gas,
and when the distance between the two modules is smaller than a second preset distance, dividing the two modules into the same test group.
The distance is represented by the position relationship, and the two modules are far away from each other on the chip, so that one test clock is not needed and different test clocks can be used; if the distance between the two modules on the chip is very close, it is obvious that one test clock can be shared. The distance may be represented by the first preset distance and the second preset distance. The first predetermined distance is typically greater than the second predetermined distance.
In some embodiments, after the step S110, the method further comprises:
adding a buffer marking the test clock on the circuit according to the test packet.
Typically one of said test clocks corresponds to one of said buffers, which is set to a special flag; therefore, in the subsequent convenient circuit design and application process, the number of the test clocks and the coverage range or the distribution position of each test clock are determined according to the number of the buffers for marking.
The buffer, which in this embodiment marks the test clock, is typically located at the fork position. Of course, different test clocks in this embodiment may be generated by the same test clock source. In this embodiment, the step of inserting the buffer only needs to be performed after the step S110, may be performed after the step S120, or may be performed before the step S120, and specifically, the step of setting the buffer may be set according to an operation requirement, which is not limited in the embodiment of the present invention, and the step of setting the buffer may be preferably performed before the step S130. As a further improvement of this embodiment, the buffer is preferably disposed on a common path of the test packet, so as to facilitate subsequent checking of the correspondence between the buffer and the test clock.
As shown in fig. 2, the present embodiment provides a test clock circuit determination apparatus, including:
a grouping unit 110 for grouping the circuits to obtain test packets; all circuits of one said test packet use the same test clock;
an adding unit 120, configured to determine an adding position of a multiplexing unit according to the test packet, and add the multiplexing unit at the adding position; the multiplexing unit is used for selecting the test signal or the functional clock and inputting the selected test signal or the selected functional clock into the test packet;
a determining unit 130, configured to determine, according to a test clock balancing policy and a common path maximum policy, a branch position where the test clock inputs different transmission paths in one test packet; the test clock equalization strategy is used for enabling the transmission delay difference value of one test clock in a plurality of transmission paths to be within a preset range; the common path maximization strategy is used for maximizing a common path which is passed by one test clock when the test clock passes through a plurality of transmission paths.
The apparatus for determining a test clock circuit according to this embodiment may be an information processing apparatus applied to various electronic devices, where the electronic devices may be a desktop computer, a notebook computer, a tablet computer, various servers, or a cloud computing platform.
The grouping unit 110, the adding unit 120 and the determining unit 130 may all correspond to a processor or a processing circuit in an electronic device. The processor may comprise a central processing unit CPU, a microprocessor MCU, a digital signal processor DSP, an application processor AP, a programmable array PLC, or the like. The processing circuitry may comprise an application specific integrated circuit ASIC or the like. The processor or the processing circuit may implement the functions of the above units through execution of the executable codes.
In this embodiment, the apparatus performs a functional circuit when determining a test clock circuit, where the functional circuit is a circuit that performs some function, for example, a circuit that performs one or more functions on a chip. The test clock circuit is used for testing the functional circuit.
In the embodiment, the test clock bifurcation position is determined by determining the test grouping and based on the test clock equalization strategy and the common path maximization strategy, so that the circuit designed in the way can be applied to an actual circuit, and has the characteristics of small OCV, small time sequence repairing difficulty, high test coverage rate and small chip area.
In some embodiments, the grouping unit 110 is specifically configured to perform grouping according to a relationship between clock domains to obtain the test packet; and/or, grouping according to the circuit scale to obtain the test grouping; and/or grouping according to interaction paths among different modules to obtain test groups; and/or grouping according to the position relation among the modules to obtain a test grouping.
In the present embodiment, how the grouping unit 110 specifically performs test grouping can be referred to the corresponding parts in the foregoing embodiments. The clock domains are relations among the clock domains corresponding to the functional clocks.
Specifically, the grouping unit 110 is specifically configured to divide modules covered by different functional clocks into different test groups.
Still more specifically, the grouping unit 110 is specifically configured to, when a module includes sub-modules using different functional clocks, and the size of the module is greater than a size threshold, group the sub-modules using different functional clocks into at least two test groups.
In addition, the grouping unit 110 is specifically configured to divide two modules, the number of which is greater than a first preset number, into one test group; and/or dividing two modules, the number of interaction paths of which is less than a second preset number and uses different functional clocks, into different test groups.
In some embodiments, the grouping unit 110 is specifically configured to, when a distance between two modules is greater than a first preset distance, group the two modules into different test groups; and/or when the distance between the two modules is smaller than a second preset distance, the two modules are classified into the same test group.
In the embodiment, the device also introduces: and the marking unit is used for adding a buffer for marking the test clock on a circuit according to the test packet after the test packet is obtained. The marking unit adds a buffer for marking the test clock on the circuit according to the test packet, so that information such as each test packet, the number of the test clocks and the like can be determined according to the buffer for marking the test clock when circuit identification is carried out subsequently. In this embodiment, the marking unit may be specifically configured to insert the buffer into the branch position, so that a common path and a non-common path through which a test clock in a test packet passes may be subsequently determined according to the buffer.
Several specific examples are provided below in connection with any of the embodiments described above:
example one:
the present example introduces a DFT clock scheme and an implementation method based on a grouping strategy to reduce the OCV effect and reduce the difficulty in repairing the timing problem. According to the example, the DFT clock scheme is reasonably designed according to the scale and the implementation mode of digital logic, and the low-speed test clocks are grouped, so that the OCV effect can be effectively reduced, and the design requirement of a large-scale digital logic chip is met.
As shown in fig. 3, the method provided by the present example includes three parts:
s1: grouping clocks according to module division, module scale, asynchronous path number and module implementation mode;
s2: reasonably inserting multiplexing units according to the grouping relation;
s3: and (4) synthesizing the test clock trees, wherein the test clocks in the test groups are balanced firstly and then the test clocks among the test groups are balanced when the test clock trees are synthesized.
The number of asynchronous paths is the number of transmission paths using different functional clocks.
The method specifically comprises the following steps:
firstly, grouping clocks according to the relationship between clock domains corresponding to functional clocks: the test clocks of different modules are divided into different groups; when the module scale is larger, the modules can be further grouped in the module, the sub-modules with more interactive paths can be in the same test group, and the sub-modules with less interactive paths can be in different test groups; when different sub-modules in the same module are dispersed, the sub-modules can be divided into different test groups.
Second, a path multiplexing unit for inserting a test clock: the path multiplexing unit should be added inside the module; multiplexing units of different test packets are respectively added; and the multiplexing units of the test clocks of different functional clock domains in the same test packet are respectively added.
And thirdly, for the test clock of each test group, adding a Buffer (Buffer) of the test clock on the test clock, and identifying the test clock so as to facilitate the identification of a back-end tool.
Fourthly, when the clock tree synthesis is carried out, balancing the test clocks in each test grouping group to ensure that the delay difference of the test clock tree is as small as possible; and then the test clocks of different test groups are equalized, so that the equalization of the test clocks of the whole circuit is ensured.
Therefore, by adopting the method of the example, the OCV of the test clock can be effectively reduced, the delay of the test clock tree is reduced, and the difficulty of repairing the timing sequence problem is reduced, so that the aims of improving the test coverage rate of the chip and reducing the area of the chip are fulfilled.
Example two:
the present example, with reference to fig. 3 to fig. 11, specifically illustrates a method for determining a test clock circuit according to an embodiment of the present invention, including:
the first step is as follows: grouping to obtain a test group; the basic principles of grouping are:
different modules are divided into different test groups, as shown in fig. 4, a module a and a module B are divided into a test group a and a test group B, respectively;
when the size of the module is larger, the circuits of one module can be divided into different test groups, and as shown in fig. 5, the module C is divided into a test group C1 and a test group C2;
dividing sub-modules or parts with more interaction paths into the same test group, as shown in fig. 5, a module C includes a part C1, a part C2, a part C3 and a part C4, wherein the part C1 and the part C2 have more interaction paths, the part C3 and the part C4 have more interaction paths, and the other parts also have fewer interaction paths or no interaction paths; depending on how many interaction paths the circuitry within module C is divided into two test packets, test packet C1 and test packet C2, where test packet C1 includes part C1 and part C2; the test packet C2 includes a test packet C3 and a test packet C4.
When the physical positions of different parts in the same module are relatively dispersed, the different test groups can be divided, as shown in fig. 6, the physical positions of the part D1 and the part D2 in the module D are relatively close to each other and are divided into the same test group D1, and the physical positions of the part D3 and the part D4 in the module D are relatively close to each other and are divided into the same test group D2.
Next, a multiplexing unit is inserted according to the test packet. One end of the multiplexing unit is connected with the functional clock, and the other end of the multiplexing unit is connected with the test clock. The test clocks corresponding to the same test packet clock come from the same source. To provide a starting point for test clock tree synthesis, a buffer needs to be added to the test clock path.
In fig. 7 to 9, the buffer on the transmission path of the test clock is used as the starting point of the test clock tree, which corresponds to the branch position, and the synthesis of the test clock tree is performed to ensure the balance of the test clock tree in the test packet. And then, carrying out full-chip clock tree synthesis to ensure full-chip balance of the test clock.
In fig. 7 to 9, the logic gate in the dashed box is the multiplexing unit, and the black triangle indicates the buffer.
Fig. 10 and fig. 11 correspond to circuits of the same functional clock, fig. 10 is a diagram illustrating that, by using the method provided in this embodiment, test packets are first performed, then each test packet is respectively provided with a test clock, and following the test clock averaging strategy and the maximum common path strategy, the branching position of the test clock is determined, and a buffer is inserted into the branching position, and the small triangle shaded by the slash in fig. 10 is the buffer marking the test clock. It is apparent that the entire circuit is tested using one test clock compared to fig. 11, and it is apparent that the common path taken by the test clock in one test packet in fig. 10 is longer and the non-common transmission path is shorter, which obviously reduces OCV.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (14)
1. A test clock circuit determination method, comprising:
grouping circuits to obtain test groups, wherein all circuits of one test group use the same test clock;
determining the adding position of a multiplexing unit according to the test packet, and adding the multiplexing unit at the adding position; the multiplexing unit is used for selecting the test clock or the functional clock and inputting the selected test clock or the selected functional clock into the test packet;
determining the branching positions of different transmission paths of the test clock input into one test packet according to a test clock balancing strategy and a public path maximum strategy; the test clock equalization strategy is used for enabling the transmission delay difference value of one test clock in a plurality of transmission paths to be within a preset range; the common path maximization strategy is used for maximizing a common path which is passed by one test clock when the test clock passes through a plurality of transmission paths.
2. The method of claim 1,
the grouping of circuits to obtain test packets includes at least one of:
grouping according to the relation between clock domains to obtain the test grouping;
grouping according to the circuit scale to obtain the test grouping;
grouping according to interaction paths among different modules to obtain a test group;
and grouping according to the position relation among the modules to obtain a test group.
3. The method of claim 2,
the grouping according to the relationship between the clock domains to obtain the test grouping comprises:
and dividing modules covered by different functional clocks into different test groups.
4. The method of claim 2,
the grouping according to the circuit scale to obtain the test packet includes:
and when one module comprises sub-modules using different functional clocks, and the size of the module is larger than a size threshold value, grouping the sub-modules using the different functional clocks to obtain at least two test groups.
5. The method of claim 2,
the grouping according to the interaction paths among the different modules to obtain the test grouping comprises the following steps:
dividing two modules with the number of interaction paths larger than a first preset number into one test group;
and/or the presence of a gas in the gas,
and dividing two modules, the number of interaction paths of which is less than a second preset number and different functional clocks are used, into different test packets.
6. The method of claim 2,
the grouping according to the position relationship among the modules to obtain the test grouping comprises the following steps:
when the distance between two modules is larger than a first preset distance, dividing the two modules into different test groups;
and/or the presence of a gas in the gas,
and when the distance between the two modules is smaller than a second preset distance, dividing the two modules into the same test group.
7. The method according to any one of claims 1 to 6,
after obtaining the test packet, the method further comprises:
adding a buffer marking the test clock on the circuit according to the test packet.
8. A test clock circuit determination apparatus, comprising:
the circuit grouping unit is used for grouping circuits to obtain test groups, wherein all the circuits of one test group use the same test clock;
an adding unit for determining an adding position of a multiplexing unit according to the test packet and adding the multiplexing unit at the adding position; the multiplexing unit is used for selecting the test clock or the functional clock and inputting the selected test clock or the selected functional clock into the test packet;
the determining unit is used for determining the branching positions of different transmission paths in one test packet input by the test clock according to a test clock balancing strategy and a public path maximum strategy; the test clock equalization strategy is used for enabling the transmission delay difference value of one test clock in a plurality of transmission paths to be within a preset range; the common path maximization strategy is used for maximizing a common path which is passed by one test clock when the test clock passes through a plurality of transmission paths.
9. The apparatus of claim 8,
the grouping unit is specifically configured to perform grouping according to a relationship between clock domains to obtain the test grouping; and/or, grouping according to the circuit scale to obtain the test grouping; and/or grouping according to interaction paths among different modules to obtain test groups; and/or grouping according to the position relation among the modules to obtain a test grouping.
10. The apparatus of claim 9,
the grouping unit is specifically used for dividing modules covered by different functional clocks into different test groups.
11. The apparatus of claim 9,
the grouping unit is specifically configured to, when one module includes sub-modules using different functional clocks, and the size of the module is greater than a size threshold, group the sub-modules using different functional clocks to obtain at least two test groups.
12. The apparatus of claim 9,
the grouping unit is specifically configured to divide two modules, the number of which is greater than a first preset number, into one test group; and/or dividing two modules, the number of interaction paths of which is less than a second preset number and uses different functional clocks, into different test groups.
13. The apparatus of claim 9,
the grouping unit is specifically configured to, when a distance between two modules is greater than a first preset distance, divide the two modules into different test groups; and/or when the distance between the two modules is smaller than a second preset distance, the two modules are classified into the same test group.
14. The apparatus according to any one of claims 8 to 13,
the device further comprises:
and the marking unit is used for adding a buffer for marking the test clock on a circuit according to the test packet after the test packet is obtained.
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| CN112906345B (en) * | 2021-03-30 | 2022-10-04 | 天津飞腾信息技术有限公司 | Method, system, and medium for validating paths in logic circuits |
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| DE602007011840D1 (en) * | 2006-01-20 | 2011-02-24 | Silicon Image Inc | Simultaneous code checker and hardware-efficient high-speed input / output with built-in self-test and debug functions |
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