CN111064449A - Digital down-sampling filter verification platform and method based on UVM platform - Google Patents
Digital down-sampling filter verification platform and method based on UVM platform Download PDFInfo
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Abstract
The invention discloses a verification platform and a method of a digital down-sampling filter based on a UVM platform, wherein the verification platform comprises a test sample, a transaction data packet, a data interface, a data packet generator, a verification environment and a to-be-tested digital down-sampling filter module DUT; a scoreboard, a master agent and a slave agent are integrated in an authentication environment, wherein the master agent comprises a data packet receiver, a data packet driver and a data packet collector, and the slave agent only comprises the data packet collector. And a gold model based on matlab of a digital down-sampling filter is introduced into the scoring board assembly through a UVM platform and a DPI interface of c language to perform data comparison with the unit to be tested so as to perform functional test. The invention utilizes the UVM verification methodology to establish a verification platform which is reusable, high in flexibility, high in efficiency and capable of interacting with matlab, and can completely test the digital down-sampling filter module, thereby greatly improving the reliability of the module.
Description
Technical Field
The invention relates to the field of digital circuit verification, in particular to a verification platform and a method of a digital down-sampling filter based on a UVM platform, which are used for verifying the functional correctness of a down-sampling filter module
Background
With the development of advanced processes of integrated circuits, the functions of chips become more and more complex, the scale of chip design becomes larger and larger, and chip verification before silicon becomes more and more critical to chip development under high chip cost. The high-efficiency verification method not only can effectively shorten the development period of the chip, but also can greatly improve the development quality of the chip.
In the world of everything interconnection, data collection and processing cannot be performed everywhere, and the down-sampling filter is widely applied to the processing process of digital signals, so that the design of a digital filter with high reliability is particularly important. Aiming at a digital filter, a traditional verification method is to compile a specific test sample through verilog language, store the test sample in a text form, and then call matlab to compare the sample data with a circuit output result after processing, and the verification method structurally lacks hierarchical design and has no completeness, flexibility and reusability. Directional testing also does not maximize functional coverage.
UVM is called general verification methodology, is a newly developed verification methodology in the chip verification industry, constructs a perfect verification platform, develops abundant library functions based on a systemverilog language, and verification engineers can construct required characteristic components through general components to generate complex, large and constrained random excitation.
Disclosure of Invention
Therefore, in order to solve the above-mentioned deficiencies, the present invention provides a verification platform and a method for a digital down-sampling filter based on a UVM platform, so as to have an automatic, simple and controllable verification platform with high reliability, reusability and portability for efficiently verifying a digital filtering module.
The invention is realized by constructing a verification platform of a digital down-sampling filter based on a UVM platform, which is characterized in that; the digital down-sampling verification platform comprises a plurality of pluggable and reusable modular components, wherein:
testing a sample TESTCASE, packaging all testing components and data, and operating on a testing platform to complete verification;
the filter module to be tested DUT completes down-sampling filtering in a circuit module form;
transaction type data packet transaction, which comprises data distribution processing of test data, and also has specific parameters indicating the type of the data packet, and can generate a specific data packet type through the selection of the parameters;
the data interface completes data interaction and data type conversion between the unit to be tested and the verification environment in a virtual interface mode;
the data packet generator sequence is responsible for generating test data and generating random data or specific data through parametric control;
the verification environment comprises a master agent, a slave agent and a score board, wherein the master agent is packaged with a data packet driver, a data packet collector and a data packet receiver; and only one component of the data packet collector is arranged in the slave agent component; and the score board scoreboard is responsible for comparing data, detecting whether the function of the unit to be detected is correct or not, and setting a DPI interface to perform data interaction with the matlab.
The verification platform of the digital down-sampling filter based on the UVM platform is characterized by comprising a platform body, a filter and a filter, wherein the platform body is provided with a filter input end and a filter output end; the technical indexes of the down-sampling filter module are as follows: 256 times data down-sampling, passband attenuation below 0.01dB, stopband attenuation above 90 dB.
The verification platform of the digital down-sampling filter based on the UVM platform is characterized by comprising a platform body, a filter and a filter, wherein the platform body is provided with a filter input end and a filter output end; data among the platforms are interacted by a TLM transaction layer, and data transmission is carried out among the components through a port and an export port; the transaction class data packet may include input data and output data of a unit under test; the data packet generator sequence randomizes the data, and the randomization can randomly generate a data packet with a higher boundary value than the specific value or a data packet with a specific meaning through the band constraint; in the verification process, the generated data packet is sent to a sequence in a main agent, a driver in the main agent acquires the data packet in the sequence through a handshake mechanism, drives data in the data packet into a time sequence signal on an input interface and sends the time sequence signal to a DUT (device under test), and meanwhile, a monitor in the main agent receives input data on the input interface according to the time sequence and assembles the input data into a transaction-level data packet to be sent to a scoreboard in the environment; the monitor in the slave agent receives data on the output port and assembles the data into transaction-level data packets according to the time sequence, and the transaction-level data packets are transmitted to the scoreboard in the environment.
The verification platform of the digital down-sampling filter based on the UVM platform is characterized by comprising a platform body, a filter and a filter, wherein the platform body is provided with a filter input end and a filter output end; the transaction type data packet transaction encapsulates a data generation function, and the data types which can be generated by the function in the verification process are as follows: 1) fully random data; 2) data with a boundary value higher than the gravity; 3) data for all minima; 4) data that are all maximum values; 5) a sinusoidal signal with a frequency of 20 kHz; 6) a sinusoidal signal with a frequency of 15 kHz; 7) a sinusoidal signal with a frequency of 200 Hz; 8) a sinusoidal signal with a frequency of 100 Hz; the data type required by the test is covered more completely.
The verification platform of the digital down-sampling filter based on the UVM platform is characterized by comprising a platform body, a filter and a filter, wherein the platform body is provided with a filter input end and a filter output end; in the component scoreboard, by setting up a DPI interface, an algorithmic c language model based on matlab is embedded, which is obtained by using the mcc compiler in matlab. After receiving the input data transmitted by the main agent, the scoreboard component imports the data into the model through the DPI interface for processing to obtain a correct data packet, compares the correct data packet with an output data packet transmitted by the agent, and checks whether the data processing function of the DUT is correct.
The verification platform of the digital down-sampling filter based on the UVM platform is characterized by comprising a platform body, a filter and a filter, wherein the platform body is provided with a filter input end and a filter output end; for the generated packets, a coverage collection is set, the full coverage requires that both binary cases of 0,1 for each bit of data must be covered.
The verification platform of the digital down-sampling filter based on the UVM platform is characterized by comprising a platform body, a filter and a filter, wherein the platform body is provided with a filter input end and a filter output end; and at the report phase stage of the UVM, the verification platform prints the coverage rate information and the data comparison result, and the comparison is successful only if the data are completely the same.
The verification platform of the digital down-sampling filter based on the UVM platform is characterized by comprising a platform body, a filter and a filter, wherein the platform body is provided with a filter input end and a filter output end; the specific method for embedding the matlab reference algorithm into the scoring board is that a correct matlab algorithm model is obtained, an mcc compiler is used for compiling the M model into a C dynamic library, and the model is compiled into the dynamic library libmtfun.so; on one side of the score board, a DPI-C interface is used for pointing to a dynamic library, so that a C algorithm model can be called in UVM; and embedding a matlab reference algorithm in the score board.
A digital down-sampling filter verification method based on UVM platform is characterized in that; the method comprises the following steps:
step 1, instantiating all components and interfaces of a DUT (device under test) and a UVM (universal video management) of a unit to be tested and connecting a verification platform and a DUT module at a platform top layer, and starting a test sample;
step 2, in the sample, the sequence sends a request for acquiring the transaction data packet to start the sequence to generate a data packet to be tested according to the set parameters, and the data packet driver acquires the data packet through a handshake mechanism and drives the data packet into an interface signal to be transmitted to the DUT module;
step 3, the DUT module completes data processing, and the slave agent completes output interface transaction-level data collection and transmits result data to the score counting board;
step 4, the master agent finishes the transaction-level data collection of the input interface and transmits the data to the scoring board, the scoring board calls a reference model to process the input data to obtain an expected output data packet, and then the expected output data packet is compared with the data packet from the output interface to obtain a verification result; step 3 and step 4 are carried out synchronously;
and 5, printing a coverage rate report and a verification result in a reporting stage. And if the coverage rate is less than one hundred percent, modifying the parameter setting, and verifying again.
The invention has the following advantages: the invention discloses a verification platform and a method of a digital down-sampling filter based on a UVM platform, wherein the verification platform comprises a test sample TESTCASE, a transaction data packet transaction, a data interface, a data packet generator sequence, a verification environment and a DUT (device under test). The system comprises a score board scoreboard, a master agent master _ agent and a slave agent slave _ agent, wherein the score board scoreboard, the master agent master _ agent and the slave agent slave _ agent are integrated in a verification environment, a data packet receiver sequence, a data packet driver and a data packet collector monitor are contained in the master agent, and only the data packet collector monitor is contained in the slave agent. And a gold model based on matlab of a digital down-sampling filter is introduced into the score board scoreboard assembly through a UVM platform and a DPI interface of c language to perform data comparison with a unit to be tested for performing functional test. The invention utilizes the UVM verification methodology to establish a verification platform which is reusable, high in flexibility, high in efficiency and capable of interacting with matlab, and can completely test the digital down-sampling filter module, thereby greatly improving the reliability of the module.
The invention has the following obvious advantages: (1) the invention is based on a UVM verification platform, generates the excitation required by the test through a UVM rich library function, ensures the diversity, randomness and completeness of the excitation, and can traverse all possible value spaces of the digital down-sampling filter. And the excitation is simultaneously sent to the RTL code and the high-level reference model, the output of the RTL code and the high-level reference model are compared, and the functionality of the circuit for realizing the algorithm is verified. (2) The UVM verification platform has a good structure, the components have high reusability and high portability, and the cross use of different digital signal processing modules and the integration of a multi-module environment are facilitated. Meanwhile, the credibility of the verification is enhanced by taking the function coverage rate as a guide.
Drawings
FIG. 1 is a schematic diagram of a validation platform framework;
FIG. 2 is a schematic diagram of a verification process;
FIG. 3 is a schematic data flow diagram for verification;
FIG. 4 is a schematic diagram of a tree structure of a verification platform assembly;
fig. 5 is a block diagram of a digital down-sampling filter.
Detailed Description
The present invention will be described in detail with reference to fig. 1 to 5, and the technical solutions in the embodiments of the present invention will be clearly and completely described, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a verification method of a digital down-sampling filter based on a UVM platform by improving, so that the digital filtering module can be efficiently verified by a verification platform which is automatic, simple, controllable, high in reliability, reusable and transplantable.
The invention relates to a verification platform of a digital down-sampling filter based on a UVM platform, which mainly comprises: the system comprises a test sample TESTCASE, a transaction data packet transaction, a data interface, a data packet generator sequence, a verification environment and a digital down-sampling filter module to be tested.
The transaction type data packet transaction encapsulates a data generation function, and the data types which can be generated by the function in the verification process are as follows: 1) fully random data; 2) data with a boundary value higher than the gravity; 3) data for all minima; 4) data that are all maximum values; 5) a sinusoidal signal with a frequency of 20 kHz; 6) a sinusoidal signal with a frequency of 15 kHz; 7) a sinusoidal signal with a frequency of 200 Hz; 8) sinusoidal signals with a frequency of 100 Hz.
The data interface comprises an input/output interface of the module to be tested;
the data packet generator sequence generates diversified test data through the control parameters;
the verification environment comprises a master agent, a slave agent and a scoreboard.
The main agent comprises three components of a data driver, a data collector monitor and a data receiver sequence, and the data driver drives the transaction-level data into a time sequence signal on a port according to the time sequence of a unit to be tested; otherwise, the data collector collects and assembles the time sequence signals on the ports into transaction-level data according to the time sequence and sends the transaction-level data to the score board; the data receiver receives the data packet generated by the data packet generator outside the authentication environment.
The slave agent comprises a data receiver monitor which is responsible for collecting time sequence signals on the output port according to time sequence, assembling the time sequence signals into transaction-level data packets and sending the transaction-level data packets to the scoreboard.
Wherein a data coverage model is defined in the receiver;
the specific method for embedding the matlab reference algorithm in the score board is to obtain a correct matlab algorithm model, compile the M model into a C dynamic library by using an mcc compiler, and compile the model into the dynamic library libmtfun. On the scoring board side, a DPI-C interface is used to point to the dynamic library, so that the C algorithm model can be called in UVM. And embedding a matlab reference algorithm in the score board.
The verification platform also has a report printing function, and the comparison result and the defined coverage value are printed after the data comparison is finished
The invention has the following obvious advantages: (1) the invention is based on a UVM verification platform, generates the excitation required by the test through a UVM rich library function, ensures the diversity, randomness and completeness of the excitation, and can traverse all possible value spaces of the digital down-sampling filter. And the excitation is simultaneously sent to the RTL code and the high-level reference model, the output of the RTL code and the high-level reference model are compared, and the functionality of the circuit for realizing the algorithm is verified. (2) The UVM verification platform has a good structure, the components have high reusability and high portability, and the cross use of different digital signal processing modules and the integration of a multi-module environment are facilitated. Meanwhile, the credibility of the verification is enhanced by taking the function coverage rate as a guide.
The invention will be further elucidated with reference to the drawings and specific embodiments.
The framework structure of the verification platform of the invention is shown in fig. 1, and the verification platform comprises a module to be tested DUT, an interface module interface of the DUT, a test case layer test, a verification environment layer env, a score board scoreboard, a data packet generator sequence, a master agent master _ agent and a slave agent slave _ agent, a data packet receiver sequence, a data packet driver and a data packet collector monitor.
The top layer is testbench, the digital down-sampling filter module DUT, the UVM test case layer and the interface module on the module are instantiated, the interface module comprises all input and output signals on the DUT, and the DUT and the verification environment perform data interaction through signals in the interface. While the associated clock and reset signals are generated in testbench.
the test layer is a test case, and the UVM instantiates the corresponding test case according to the simulation command type + UVM _ TESTNAME. The control parameters under different test cases are different, so that different test data can be generated simply and conveniently.
env is a verification environment layer for instantiating specific verification components, including master _ agent, slave _ agent, scoreboard. The master _ agent comprises sequence, driver and monitor, wherein the sequence is responsible for sending defined random excitation to the driver, the driver converts data into corresponding input signals and sends the input signals to the input end of the DUT, and the monitor is responsible for collecting the input signals and the output signals and counting the functional coverage rate. And the scoreboard calls the reference model for processing the data input into the data transmission module, and the obtained result is compared with the data at the output end.
The simulation verification flow chart is shown in fig. 2, testbench starts simulation by calling run _ test () function, before simulation time starts, according to the phase mechanism of UVM, the platform will complete instantiation of each component, and the tree structure hierarchy chart of the instantiated component is shown in fig. 4.
In sequence, different test data packets are generated according to different parameters, the data packets comprise input data and output data, the most basic data is data which is random by using a randomize function, and a function generation () is also embedded, and 1) data with high boundary value proportion can be generated by transmitting parameters 1-7; 2) data for all minima; 3) data that are all maximum values; 4) a sinusoidal signal with a frequency of 20 kHz; 5) a sinusoidal signal with a frequency of 15 kHz; 6) a sinusoidal signal with a frequency of 200 Hz; 7) sinusoidal signals with a frequency of 100 Hz. Meanwhile, a plurality of data packets can be generated in sequence to be sequentially driven. The one-time complete verification process includes 10 randomly generated packets and one specific data packet.
After the sequence receives the data packet and receives the data request of the driver, the sequence sends the data packet to the driver.
And the driver is in a standby state, once a data packet is obtained, the data in the packet is sequentially driven to the input port of the DUT on the rising edge of the clock signal according to the time sequence requirement of the filter until all the data are transmitted, and at the moment, a handshake signal is sent to the sequencer to inform that the current data packet is finished.
The monitor, which is also always on standby, detects the signal on the input port of the DUT, generates a new data packet upon detection of the valid signal for input or output data, and loads the output data into the packet on the rising edge of the valid signal. Meanwhile, a coverage rate group is set in the monitor, and two bins of 0 and 1 are set for each bit of input data and output data, so that the data can be completely covered to all possible intervals. When the data capacity in the packet reaches a preset value, the packet is finished, the packet is sent to a TLM port while coverage rate statistics is carried out, and the data packet enters two FIFOs respectively corresponding to a master _ agent and a slave _ agent. The use of a FIFO can effectively avoid loss of data.
scoreboard gets the packets in the two FIFOs in a blocking manner, respectively, and the corresponding verification data flow is shown in fig. 3. For the data packet from master agent, scoreboard imports the data into the algorithmic model from matlab in the dynamic library compiled and converted into C in advance through the dynamic program interface DPI of the systemverilog, and exports the result into scoreboard. The cooperation of the two is realized by a header file of the C program. And comparing the exported data with the data of the output port to obtain a verification result.
After all data in the sequence are sent and compared, a report printing stage is entered, all comparison results and coverage rate statistical results are printed, if all comparison results are successful, verification is successful, and meanwhile, the target coverage rate is one hundred percent.
And finishing the verification of the digital down-sampling filter.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A digital down-sampling filter verification platform based on a UVM platform is characterized in that; the digital down-sampling verification platform comprises a plurality of pluggable and reusable modular components, wherein:
testing a sample TESTCASE, packaging all testing components and data, and operating on a testing platform to complete verification;
the filter module to be tested DUT completes down-sampling filtering in a circuit module form;
transaction type data packet transaction, which comprises data distribution processing of test data, and also has specific parameters indicating the type of the data packet, and can generate a specific data packet type through the selection of the parameters;
the data interface completes data interaction and data type conversion between the unit to be tested and the verification environment in a virtual interface mode;
the data packet generator sequence is responsible for generating test data and generating random data or specific data through parametric control;
the verification environment comprises a master agent, a slave agent and a score board, wherein the master agent is packaged with a data packet driver, a data packet collector and a data packet receiver; and only one component of the data packet collector is arranged in the slave agent component; and the score board scoreboard is responsible for comparing data, detecting whether the function of the unit to be detected is correct or not, and setting a DPI interface to perform data interaction with the matlab.
2. The UVM platform based digital down-sampling filter verification platform according to claim 1, wherein; the technical indexes of the down-sampling filter module are as follows: 256 times data down-sampling, passband attenuation below 0.01dB, stopband attenuation above 90 dB.
3. The UVM platform based digital down-sampling filter verification platform according to claim 1, wherein; data among the platforms are interacted by a TLM transaction layer, and data transmission is carried out among the components through a port and an export port; the transaction class data packet may include input data and output data of a unit under test; the data packet generator sequence randomizes the data, and the randomization can randomly generate a data packet with a higher boundary value than the specific value or a data packet with a specific meaning through the band constraint; in the verification process, the generated data packet is sent to a sequence in a main agent, a driver in the main agent acquires the data packet in the sequence through a handshake mechanism, drives data in the data packet into a time sequence signal on an input interface and sends the time sequence signal to a DUT (device under test), and meanwhile, a monitor in the main agent receives input data on the input interface according to the time sequence and assembles the input data into a transaction-level data packet to be sent to a scoreboard in the environment; the monitor in the slave agent receives data on the output port and assembles the data into transaction-level data packets according to the time sequence, and the transaction-level data packets are transmitted to the scoreboard in the environment.
4. The UVM platform based digital down-sampling filter verification platform according to claim 1, wherein; the transaction type data packet transaction encapsulates a data generation function, and the data types which can be generated by the function in the verification process are as follows: 1) fully random data; 2) data with a boundary value higher than the gravity; 3) data for all minima; 4) data that are all maximum values; 5) a sinusoidal signal with a frequency of 20 kHz; 6) a sinusoidal signal with a frequency of 15 kHz; 7) a sinusoidal signal with a frequency of 200 Hz; 8) a sinusoidal signal with a frequency of 100 Hz; the data type required by the test is covered more completely.
5. The UVM platform based digital down-sampling filter verification platform according to claim 1, wherein; in the component scoreboard, by setting up a DPI interface, an algorithmic c language model based on matlab is embedded, which is obtained by using the mcc compiler in matlab. After receiving the input data transmitted by the main agent, the scoreboard component imports the data into the model through the DPI interface for processing to obtain a correct data packet, compares the correct data packet with an output data packet transmitted by the agent, and checks whether the data processing function of the DUT is correct.
6. The UVM platform based digital down-sampling filter verification platform according to claim 1, wherein; for the generated packets, a coverage collection is set, the full coverage requires that both binary cases of 0,1 for each bit of data must be covered.
7. The UVM platform based digital down-sampling filter verification platform according to claim 1, wherein; and at the report phase stage of the UVM, the verification platform prints the coverage rate information and the data comparison result, and the comparison is successful only if the data are completely the same.
8. The UVM platform based digital down-sampling filter verification platform according to claim 1, wherein; the specific method for embedding the matlab reference algorithm into the scoring board is that a correct matlab algorithm model is obtained, an mcc compiler is used for compiling the M model into a C dynamic library, and the model is compiled into the dynamic library libmtfun.so; on one side of the score board, a DPI-C interface is used for pointing to a dynamic library, so that a C algorithm model can be called in UVM; and embedding a matlab reference algorithm in the score board.
9. A digital down-sampling filter verification method based on UVM platform is characterized in that; the method comprises the following steps:
step 1, instantiating all components and interfaces of a DUT (device under test) and a UVM (universal video management) of a unit to be tested and connecting a verification platform and a DUT module at a platform top layer, and starting a test sample;
step 2, in the sample, the sequence sends a request for acquiring the transaction data packet to start the sequence to generate a data packet to be tested according to the set parameters, and the data packet driver acquires the data packet through a handshake mechanism and drives the data packet into an interface signal to be transmitted to the DUT module;
step 3, the DUT module completes data processing, and the slave agent completes output interface transaction-level data collection and transmits result data to the score counting board;
step 4, the master agent finishes the transaction-level data collection of the input interface and transmits the data to the scoring board, the scoring board calls a reference model to process the input data to obtain an expected output data packet, and then the expected output data packet is compared with the data packet from the output interface to obtain a verification result; step 3 and step 4 are carried out synchronously;
and 5, printing a coverage rate report and a verification result in a reporting stage. And if the coverage rate is less than one hundred percent, modifying the parameter setting, and verifying again.
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| CN114826995A (en) * | 2022-04-22 | 2022-07-29 | 电子科技大学 | UVM-based verification platform supporting PCIe gigabit Ethernet chip |
| CN114896931A (en) * | 2022-05-12 | 2022-08-12 | 北京联盛德微电子有限责任公司 | Bluetooth transceiving path verification method and system based on handshake mechanism |
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