CN113671349A

CN113671349A - FPGA chip test platform and FPGA chip test method

Info

Publication number: CN113671349A
Application number: CN202110964376.4A
Authority: CN
Inventors: 杨萌
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2021-08-22
Filing date: 2021-08-22
Publication date: 2021-11-19

Abstract

The invention discloses a FPGA chip test platform, which comprises: an agent module for stimulus generation and transmission configured to generate a random stimulus sequence; the reference model is configured to receive a random excitation sequence generated by the agent module and transmitted by excitation generation, and generates target data based on the random excitation sequence; the scoring board is configured to compare target data generated by the reference model with output data of the FPGA chip to obtain a test result; the agent module for generating and sending the excitation is connected with the FPGA chip through a serial protocol interface, and the agent module for generating and sending the excitation sends a random excitation sequence to the FPGA chip and receives output data of the FPGA chip. The invention also discloses a FPGA chip testing method. The invention can reduce the testing workload and improve the testing efficiency, and the multiplexing characteristic of the invention is suitable for the excitation generation of different testing modules, thereby greatly reducing the repetitive labor.

Description

FPGA chip test platform and FPGA chip test method

Technical Field

The invention relates to the technical field of testing, in particular to an FPGA chip testing platform and an FPGA chip testing method.

Background

An FPGA (Field-Programmable Gate Array) is a customizable chip in an IC (Integrated Circuit) relative to an ASIC (Application Specific Integrated Circuit), and has a wide Application range and is updated faster than the ASIC.

The test process of FPGA chip research and development is relatively tedious, because it is programmable chip, the structure complexity is often higher than ASIC, and the excitation point is many moreover, and the range of variation is big. Meanwhile, FPGA design companies are rare, and design methods are not transparent. Therefore, the FPGA has the disadvantages of large workload, high complexity and poor reusability.

The existing FPGA Test is a manual directional Test, a tester needs to manually write a Test stimulus according to the requirement of a module to be tested in the FPGA, then the driver module is used for sending the stimulus to the FPGA through a Joint Test Action Group (JTAG), and the stimulus is collected and output for testing.

The disadvantages of the prior art include: the method has the advantages that the excitation compiling efficiency is low, the manual compiling speed is low, and testers need to consider excitation generation item by item; the error rate is high, and because the judgment is carried out one by manual operation, the error of writing or incomplete consideration is inevitable; the test platform is complex to maintain, the manual writing of test excitation codes is large in amount, and the maintenance and modification are relatively complex; the multiplexing rate is low, and due to the directional programming, the test excitation is in a fixed mode, so the test multiplexing applied to similar modules is not good.

Disclosure of Invention

In view of this, an object of the embodiments of the present invention is to provide an FPGA chip testing platform and an FPGA chip testing method, where the testing platform for the FPGA chip is built, so that testing workload can be reduced, testing efficiency can be improved, a failure rate can be reduced, and the characteristics of multiplexing can be adapted to excitation generation of different testing modules under the condition of little change, so that repetitive labor can be greatly reduced.

Based on the above object, an aspect of the embodiments of the present invention provides an FPGA chip testing platform, including: an agent module for stimulus generation and transmission configured to generate a random stimulus sequence; the reference model is configured to receive the random excitation sequence generated by the agent module and transmitted by the excitation generation module, and generate target data based on the random excitation sequence; the scoring board is configured to compare the target data generated by the reference model with the output data of the FPGA chip to obtain a test result; the agent module for generating and sending the excitation is connected with the FPGA chip through a serial protocol interface, and the agent module for generating and sending the excitation sends the random excitation sequence to the FPGA chip and receives output data of the FPGA chip.

In some embodiments, the platform further comprises: and the configuration module of the excitation generation environment is configured to change the parameter value of the test based on different FPGA chips.

In some embodiments, the platform further comprises: and the coverage rate counting module is configured to count the coverage rate of the random excitation sequence to judge whether the random excitation sequence is complete.

In some embodiments, the incentive generation transmission agent module is further configured to: sending the generated random excitation sequence to the reference model; and sending the received output data of the FPGA chip to the scoring board.

In some embodiments, the incentive generating sending agent module comprises: the excitation package module is configured to define an excitation package, and the excitation package comprises variable numbers and an excitation random range; the excitation sequence generation module is configured to call the excitation packet module to generate different random excitation sequences; and the driver is configured to send the random excitation sequence generated by the excitation sequence generation module to an FPGA chip and receive output data of the FPGA chip.

In some embodiments, the excitation sequence generation module is further configured to: sending the generated random excitation sequence to the reference model.

In some embodiments, the drive is further configured to: and sending the received output data of the FPGA chip to the scoring board.

In some embodiments, the reference model is further configured to: and sending the generated target data to the scoring board.

On the other hand, the embodiment of the invention also provides a test method of the FPGA chip, which is applied to the test platform and comprises the following steps: generating a random excitation sequence by an agent module for excitation generation and transmission, and respectively transmitting the random excitation sequence to a reference model and an FPGA chip; receiving the random excitation sequence by the reference model, generating target data based on the random excitation sequence, and sending the target data to a scoring board; the agent module which is generated and sent by the excitation receives the output data of the FPGA chip and sends the output data to the scoring board; and comparing the target data with the output data by the scoring board to obtain a test result.

The invention has at least the following beneficial technical effects: the test platform for the FPGA chip is built, so that the test workload can be reduced, the test efficiency is improved, the error rate is reduced, and the multiplexing characteristic of the test platform can adapt to the excitation generation of different test modules under the condition of little change, so that the repetitive labor is greatly reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of an FPGA chip test platform provided by the present invention;

FIG. 2 is a schematic diagram of an embodiment of an FPGA chip test platform provided by the present invention;

fig. 3 is a schematic diagram of an embodiment of a method for testing an FPGA chip provided in the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

Based on the above purpose, the first aspect of the embodiment of the present invention provides an FPGA chip test platform. Fig. 1 is a schematic diagram illustrating an embodiment of an FPGA chip test platform provided in the present invention.

As shown in fig. 1, the FPGA chip test platform according to the embodiment of the present invention includes:

an agent module S100 for stimulus generation and transmission configured to generate a random stimulus sequence;

the reference model S200 is configured to receive a random excitation sequence generated by the agent module S100 and sent by excitation generation, and generates target data based on the random excitation sequence; and

the scoring board S300 is configured to compare target data generated by the reference model S200 with output data of the FPGA chip to obtain a test result;

the agent module S100 for generating and sending the excitation is connected with the FPGA chip through a serial protocol interface, and the agent module S100 for generating and sending the excitation sends a random excitation sequence to the FPGA chip and receives output data of the FPGA chip.

In this embodiment, the FPGA chip test platform is built in a sv (system verilog) -based UVM (Universal Verification Methodology) form, and the test platform has high reusability and flexible excitation generation. The SV is a hardware description language, combines the respective advantages of Verlilg and c + +, is the most widely applied language in the current IC design verification, can describe a circuit at an action level and can describe module functions at a logic level, has inheritance and reuse characteristics due to the object-oriented language, and provides guarantee for the completeness of generating test excitation at the logic level. UVM is the most powerful IC verification at present, applies the most extensive methodology, has fully verified its powerful general structure in ASIC field, because FPGA and ASIC are IC design together, so its method of verifying the test field has very big commonality, and the excitation that this paper used produces platform architecture, is just based on UVM and builds.

In this embodiment, fig. 2 is a schematic diagram illustrating an embodiment of an FPGA chip test platform provided in the present invention. As shown in fig. 2, Env is the environment top layer, and its interior instantiates config (configuration module of the stimulus generation environment), agent (agent module of the stimulus generation and transmission), coverage (coverage statistics module), reference model (reference model), scoreboard (score board).

The Reference model is a Reference model and describes a functional model which is the same as that of the tested module, after excitation is generated in the sequence, the excitation is sent to the Reference model, target data is generated in the Reference model, the target data is sent to the scoerboard, and the target data is compared with actual data received by the driver from the FPGA chip, so that a verification result is obtained.

The Scoreboard is a scoring board, realizes a data comparison function, and compares target data generated by the reference model with actual data output by the FPGA to obtain a verification result.

In this embodiment, the reference model is a fully-customized design for digital-analog mixing in the FPGA, and a prior model is used to replace an analog module that needs to use spice simulation, so as to generate a manu pattern excitation packet with coverage characteristics based on an ATE input format, where the excitation packet can be converted into a JTAG input format through a specific conversion module, and front-end tool simulation is performed through drv. The wafer or packaged chip may also be subjected to ATE testing by ATE equipment.

In this embodiment, for packaging forms with different numbers of pins, an adaptive pin conversion scheme is adopted, and the generated binary excitation file can be packaged by a scripting language, and the packaged ports are divided into DATA 0-2, CLK, RST and OUT. And compressing control signals except CLK.RST into DATA 0-2, realizing a soft core unpacking module inside the FPGA, unpacking the compressed DATA, and releasing the unpacked DATA to IO pins of different packages, thereby realizing the ATE test and front-end simulation of the FPGA chip with coverage.

In some embodiments of the invention, the platform further comprises: and the configuration module of the excitation generation environment is configured to change the parameter value of the test based on different FPGA chips.

In this embodiment, with continued reference to fig. 2, Config is a configuration module that stimulates the generation environment, and can match the tests of different FPGA chips by changing the parameter values.

In some embodiments of the invention, the platform further comprises: and the coverage rate counting module is configured for counting the coverage rate of the random excitation sequence to judge whether the random excitation sequence is complete.

In this embodiment, with continuing reference to fig. 2, the Coverage module is a Coverage statistics module, and the SV description is used to generate the random excitation, so as to ensure the completeness of the random excitation, Coverage statistics needs to be performed, and when the Coverage is 100%, it is complete that the excitation generation already covers all cases.

In some embodiments of the invention, the agent module for incentive generation transmission is further configured to: sending the generated random excitation sequence to a reference model; and sending the received output data of the FPGA chip to a scoring board.

In some embodiments of the invention, the agent module that instigates a generation of a transmission comprises: the excitation package module is configured for defining an excitation package, and the excitation package comprises variable numbers and an excitation random range; the excitation sequence generation module is configured for calling the excitation packet module to generate different random excitation sequences; and the driver is configured to send the random excitation sequence generated by the excitation sequence generation module to the FPGA chip and receive output data of the FPGA chip.

In this embodiment, with continued reference to fig. 2, the Agent generates and sends an Agent module for stimulus, and the Agent module internally includes sequence (stimulus sequence), sequence (stimulus sequence generation module), and driver (driver). The seq _ item is a module of the excitation packet, and defines an excitation packet internally, which contains the number of variables and the random range of excitation. Sequence is an excitation Sequence, which consists of multiple seq _ items. The sequence generates different random excitation sequences by calling the sequence, and the generated sequences are sent to the driver. The Driver is a module which is in physical communication with the FPGA chip, the excitation sequence is finally started to the FPGA chip through the Driver, similarly, the output of the FPGA is also sampled by the Driver and is further transmitted to the scoreboard through an agent and scoreboard interface, and the communication protocol between the FPGA chip and the Driver is JTAG.

In some embodiments of the invention, the excitation sequence generation module is further configured to: the generated random excitation sequence is sent to the reference model.

In some embodiments of the invention, the drive is further configured to: and sending the received output data of the FPGA chip to a scoring board.

In some embodiments of the invention, the reference model is further configured for: and sending the generated target data to a scoring board.

Based on the above purpose, a second aspect of the embodiments of the present invention provides a method for testing an FPGA chip. Fig. 3 is a schematic diagram illustrating an embodiment of the FPGA chip testing method provided by the present invention. As shown in fig. 3, the FPGA chip testing method according to the embodiment of the present invention includes: s01, generating a random excitation sequence by the agent module for excitation generation and transmission, and respectively transmitting the random excitation sequence to the reference model and the FPGA chip; s02, receiving the random excitation sequence by the reference model, generating target data based on the random excitation sequence, and sending the target data to the score counting board; s03, the agent module which is generated and sent by excitation receives the output data of the FPGA chip and sends the output data to the score counting board; and S04, comparing the target data with the output data by the score board to obtain a test result.

In some embodiments of the invention, the method further comprises: and counting the coverage rate of the random excitation sequence to judge whether the random excitation sequence is complete.

It should be particularly noted that, the steps in the embodiments of the FPGA chip testing method may be mutually intersected, replaced, added, or deleted, so that the FPGA chip testing method with these reasonable permutation and combination transformations shall also belong to the scope of the present invention, and shall not limit the scope of the present invention to the embodiments.

Finally, it should be noted that, as one of ordinary skill in the art can appreciate, all or part of the processes in the methods of the above embodiments may be implemented by instructing relevant hardware through a computer program, and the program of the FPGA chip testing method may be stored in a computer readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. The FPGA chip test platform is characterized by comprising:

an agent module for stimulus generation and transmission configured to generate a random stimulus sequence;

the reference model is configured to receive the random excitation sequence generated by the agent module and transmitted by the excitation generation module, and generate target data based on the random excitation sequence; and

the scoring board is configured to compare the target data generated by the reference model with the output data of the FPGA chip to obtain a test result;

the agent module for generating and sending the excitation is connected with the FPGA chip through a serial protocol interface, and the agent module for generating and sending the excitation sends the random excitation sequence to the FPGA chip and receives output data of the FPGA chip.

2. The FPGA chip test platform of claim 1, further comprising:

and the configuration module of the excitation generation environment is configured to change the parameter value of the test based on different FPGA chips.

3. The FPGA chip test platform of claim 1, further comprising:

and the coverage rate counting module is configured to count the coverage rate of the random excitation sequence to judge whether the random excitation sequence is complete.

4. The FPGA chip test platform of claim 1 wherein said stimulus generation and transmission agent module is further configured to:

sending the generated random excitation sequence to the reference model;

and sending the received output data of the FPGA chip to the scoring board.

5. The FPGA chip test platform of claim 1, wherein the agent module for stimulus generation and transmission comprises:

the excitation package module is configured to define an excitation package, and the excitation package comprises variable numbers and an excitation random range;

the excitation sequence generation module is configured to call the excitation packet module to generate different random excitation sequences;

and the driver is configured to send the random excitation sequence generated by the excitation sequence generation module to an FPGA chip and receive output data of the FPGA chip.

6. The FPGA chip test platform of claim 5, wherein the stimulus sequence generation module is further configured to:

sending the generated random excitation sequence to the reference model.

7. The FPGA chip test platform of claim 5, wherein the driver is further configured to:

and sending the received output data of the FPGA chip to the scoring board.

8. The FPGA chip test platform of claim 1, wherein said reference model is further configured to:

and sending the generated target data to the scoring board.

9. An FPGA chip testing method, which is applied to the testing platform of any one of claims 1 to 8, and comprises the following steps:

generating a random excitation sequence by an agent module for excitation generation and transmission, and respectively transmitting the random excitation sequence to a reference model and an FPGA chip;

receiving the random excitation sequence by the reference model, generating target data based on the random excitation sequence, and sending the target data to a scoring board;

the agent module which is generated and sent by the excitation receives the output data of the FPGA chip and sends the output data to the scoring board;

and comparing the target data with the output data by the scoring board to obtain a test result.

10. The FPGA chip testing method of claim 9, further comprising:

and counting the coverage rate of the random excitation sequence to judge whether the random excitation sequence is complete.