CN110705191B - Method for constructing polymorphic simulation verification environment - Google Patents

Abstract

The invention relates to a method for constructing a polymorphic simulation verification environment, which comprises the following steps: defining excitation generation rules under the whole chip, realizing an excitation resource management and allocation mechanism, and managing and allocating resource spaces uniformly; defining an external unified interface parameter list of a script tool library to realize the analysis support of various input parameters and commands; when the environment needs the virtual model, the script library automatically generates the virtual model modeling of the design module; when the environment needs a real model, finding a corresponding real model in a verification model library; the virtual model or the real model is used for realizing the cutting or the replacement of the design module, and the change of the environment topological structure is completed; test validation is run with a test sequence provided by the command line based on the newly generated environmental topology design code and the environmental code. The invention can reduce the workload of development environment and excitation of the verifier.

Description

Method for constructing polymorphic simulation verification environment

Technical Field

The invention relates to the technical field of microprocessing verification, in particular to a method for constructing a polymorphic simulation verification environment.

Background

With the increasing scale and complexity of integrated circuits, the functions of processor chips become more and more complex, and the corresponding verification work becomes more and more difficult. The verification personnel need to establish the simulation environment at the module level for verification and establish the simulation environment at the chip level for verification. In contrast to module-level analog simulation, a chip-level or system-level analog simulation environment involves a large number of design modules, as well as a large number of IPs. At present, a common simulation environment construction mode is to respectively construct a module-level simulation environment and a chip-level simulation environment and separately test the module-level simulation environment and the chip-level simulation environment, and an environment topological structure is relatively fixed. Firstly, higher requirements are put forward on the capability of verification personnel when a complex simulation environment is to be constructed; secondly, development and maintenance are costly.

In the prior art, in the environment verification with relatively small design scale, the influence of environment performance and resource utilization rate is relatively small or can be ignored. However, for very large scale designs involving billions or even billions of transistors, the environment and excitation applicability are very significant in the verification process, mainly in the aspects of verification efficiency and resource utilization. However, the commonly used built simulation environment has two drawbacks: firstly, module-level environment verification and chip-level simulation environments are mutually independent, and verification personnel respectively carry out verification; secondly, the incentives for the development of each environment are not compatible with each other, such as: resulting in a module-level environmental stimulus that cannot operate in a chip-level environment. This requires the development of corresponding stimuli for each environment separately, resulting in relatively inefficient verification.

Disclosure of Invention

The invention aims to solve the technical problem of providing a method for constructing a polymorphic simulation verification environment, which can reduce the workload of a verifier on developing the environment and excitation.

The technical scheme adopted by the invention for solving the technical problem is as follows: the method for constructing the polymorphic simulation verification environment comprises the following steps:

(1) Defining excitation generation rules under the whole chip, realizing an excitation resource management and allocation mechanism, and managing and allocating resource spaces uniformly;

(2) Defining an external unified interface parameter list of a script tool library to realize the analysis support of various input parameters and commands;

(3) When the environment needs the virtual model, the script library automatically generates the virtual model modeling of the design module; when the environment needs a real model, finding a corresponding real model in a verification model library;

(4) The virtual model or the real model is used for realizing the cutting or the replacement of the design module, and the change of the environment topological structure is completed;

(5) Test validation is run with a test sequence provided by the command line based on the newly generated environmental topology design code and the environmental code.

In the step (1), uniform resource management logic is used for carrying out consistent resource allocation and management on the module level environment, and address spaces corresponding to respective cores are respectively managed in the real module level environment and the virtual module level environment.

In the step (1), the real module level environment and the virtual module level environment are configured to be in place at the same time for the chip level environment, the space addresses of the core accesses of the real module level environment and the virtual module level environment are different, automatic compatible adaptation can be achieved, and the space addresses of the core accesses of the real module level environment and the virtual module level environment are the same, so that the pseudo sharing of the Cache block is achieved due to the access granularity.

The step (2) specifically comprises the following steps:

(21) Detecting whether a design module needs to be in place in an input command, and if so, judging whether a real model needs to be used; if not, judging whether a virtual model needs to be used;

(22) And analyzing the design codes, splitting the design instantiation array module needing to be related into a plurality of single instantiation modules, and checking the grammar rules of line width, splitting width and sign bit.

Advantageous effects

Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: according to the invention, under the condition of the existing resources, a system resource mechanism for unified management is established, virtual and real models can be adopted to replace real designs to construct different simulation environments according to the requirements of users, and the self-adaption under different test and excitation environments is realized, so that the verification efficiency is improved, the requirements on the resources are reduced, the development environment and the excitation workload of verification personnel can be reduced, the verification personnel can focus on the verification more, and the verification progress is accelerated.

Drawings

FIG. 1 is a flow chart of the present invention;

fig. 2 is a configuration diagram of a real module-level environment and a virtual module-level environment in a chip-level environment.

Detailed Description

The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.

The embodiment of the invention relates to a method for constructing a polymorphic simulation and verification environment, which relates to a reusable script library, a DUT (device under test), a VIP (very important person) model library, a Testbench and a test stimulus library. The DUT is a design code, the VIP model library is a library (short for: a verification model library or a real model library) composed of a verification unit with a self-developed design model function and a module-level verification environment, the Testbench is used for completing the initialization function of the whole environment, the reusable script library is a library formed by a series of scripts which are realized based on Python and have expandable, reusable and support dynamic parameters, and the stimulus library is a basic test set developed under different environments. As shown in fig. 1, the method comprises the steps of:

the first step is as follows: and defining an excitation generation rule under the whole chip, realizing an excitation resource management and allocation mechanism, and uniformly managing and allocating resource space.

For a module level environment, uniform resource management logic needs to be used for consistent resource allocation and management, so that adaptive test excitation can be generated conveniently. Such as: for multi-core processors, unified management of address space is required. Address spaces corresponding to respective cores can be managed in a real PE (Processor Element) module level environment and a VPE (Virtual Processor Element) module level environment respectively, and test sequences corresponding to core bits are developed.

For the chip level environment, VPE and PE can be configured to be in place at the same time, and the space addresses of respective core access are different due to the reason of uniform resource allocation management based on the sequence developed by the two module level environments, so that the automatic compatibility can be stimulated. Even if the address space is the same, the Cache block pseudo sharing is realized due to the access granularity, and the self-adaption is also satisfied, as shown in FIG. 2.

The second step is as follows: and defining an external unified interface parameter list of the script tool library to realize the analysis support of various input parameters and commands.

Step 2.1: detecting whether a design module in an input command needs to be in place or not, and if so, using a real model; if not, whether a dummy pattern is needed. The dummy model in this embodiment is an empty design module, which has no specific function and is used only for reducing the design scale. The real model in the present embodiment is an autonomously implemented module level environment or VIP (Verification intelligent Property) model.

Step 2.2: and analyzing the design codes, splitting the design instantiation array module needing to be related into a plurality of single instantiation modules, and checking the grammar rules such as line width, splitting width, sign bit and the like.

The third step: if the environment requires a virtual model, the virtual model modeling of the design module, i.e., the virtual model is generated, is automatically generated by the script. If the environment requires a real model, the corresponding real model needs to be found in the VIP library.

The fifth step: and (3) using a virtual model or a real model to realize the cutting or replacement of the design module and finish the change of the environment topological structure.

A sixth step: design code and environment code based on the newly generated topology results, run test validation with the test sequence provided by the command line.

The invention can realize the replacement of the design module by the virtual-real model on line according to the user command parameters, thereby being capable of quickly generating various required environments, dynamically adjusting the environment topological structure under the condition that the environment supports various parameter configuration, quickly generating the environment and further directly running the test. The invention realizes a unified management and distribution mechanism of the excitation resources, and the excitation developed in different environments can be subjected to self-adaptive test in other environments, thereby reducing the redevelopment cost; because the environment topological structure can be dynamically adjusted, the environment scale can be reduced as required, the use of test resources can be obviously reduced, and the verification progress is accelerated.

Claims (4)

1. A method for constructing a polymorphic simulation verification environment is characterized by comprising the following steps:

(1) Defining excitation generation rules under a full chip, realizing an excitation resource management and allocation mechanism, and managing and allocating resource spaces in a unified manner;

(2) Defining an external unified interface parameter list of a script tool library to realize the analysis support of various input parameters and commands;

(3) When the environment needs the virtual model, the script library automatically generates a virtual model modeling for the design module; when the environment needs the real model, finding the corresponding real model in the verification model library; the virtual model is an empty design module and is only used for reducing the design scale; the real model is an autonomously implemented module level environment or VIP model;

(4) The virtual model or the real model is used for realizing the cutting or the replacement of the design module, and the change of the environment topological structure is completed;

(5) Based on the newly generated environment topology design code and environment code, test validation is run with a test sequence provided by the command line.

2. The method according to claim 1, wherein in step (1), the uniform resource management logic is used for consistent resource allocation and management of the module-level environment, and the address spaces corresponding to the cores of the real module-level environment and the virtual module-level environment are managed respectively.

3. The method for constructing a polymorphic simulation verification environment according to claim 1, wherein in step (1), the real module-level environment and the virtual module-level environment are configured to be in place at the same time for the chip-level environment, and when the spatial addresses of the core accesses of the real module-level environment and the virtual module-level environment are different, an automatic compatibility can be realized, and when the spatial addresses of the core accesses of the real module-level environment and the virtual module-level environment are the same, the Cache block pseudo-sharing is realized due to the access granularity.

4. The method for building a polymorphic simulation verification environment according to claim 1, wherein the step (2) specifically comprises the steps of:

(21) Detecting whether a design module needs to be in place in an input command, and if so, judging whether a real model needs to be used;

if not, judging whether a virtual model needs to be used;

(22) And analyzing the design codes, splitting the design instantiation array module needing to be related into a plurality of single instantiation modules, and checking the grammar rules of line width, splitting width and sign bit.

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