CN108255736B - Quality evaluation method and device for circuit test platform - Google Patents
Quality evaluation method and device for circuit test platform Download PDFInfo
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- CN108255736B CN108255736B CN201810146803.6A CN201810146803A CN108255736B CN 108255736 B CN108255736 B CN 108255736B CN 201810146803 A CN201810146803 A CN 201810146803A CN 108255736 B CN108255736 B CN 108255736B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3684—Test management for test design, e.g. generating new test cases
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
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- G06F11/3676—Test management for coverage analysis
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Abstract
The invention discloses a quality evaluation method and a quality evaluation device for a circuit test platform, wherein the method comprises the following steps: establishing a fault library for classifying faults and defining RTL level insertion modes corresponding to the faults; and inserting the faults in the fault library into the tested unit of the circuit test platform according to the corresponding RTL level insertion mode, operating the circuit test platform, and evaluating the quality of the circuit test platform according to whether the circuit test platform can detect the faults or not. According to the invention, some random faults are inserted into the RTL level by setting the fault rule base, so that the integrity and reliability evaluation work of the circuit test platform is advanced, the evaluation work is completed more efficiently and more pertinently, and a good auxiliary effect is provided for the traditional evaluation method.
Description
Technical Field
The present invention relates to an evaluation technique for a circuit test platform, and more particularly, to a quality evaluation method and apparatus for a circuit test platform.
Background
The traditional method for evaluating the completeness and reliability of the circuit test platform is mainly used for evaluating the coverage rate of design codes obtained by all test cases finally, the method has the advantages of large required data sample amount, long evaluation period and late feedback result, and once the defects of the test platform are found, regression test needs to be carried out again to influence the test progress.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a more efficient and more targeted quality evaluation method and device for a circuit test platform.
In order to achieve the purpose, the invention provides the following technical scheme: a quality evaluation method of a circuit test platform comprises the following steps:
s1, establishing a fault library, wherein the fault library is used for classifying faults and defining RTL level insertion modes corresponding to the faults;
and S2, inserting the fault in the fault library into the tested unit of the circuit test platform according to the corresponding RTL level insertion mode, operating the circuit test platform, and evaluating the quality of the circuit test platform according to whether the circuit test platform can detect the fault.
Preferably, the method further comprises: creating the circuit testing platform to be evaluated.
Preferably, the circuit test platform comprises a stimulus generator, the unit under test, a reference model for simulating the function of the unit under test and a comparator, wherein,
the excitation generator is connected with the tested unit and the reference model and is used for sending random test excitation of the test case to the tested unit and the reference model;
and the tested unit and the reference model are both connected with the comparator, the outputs of the two are respectively sent to the comparator to complete result comparison, and if the comparison is passed, the test case passes and the tested unit is free of defects.
Preferably, if the comparison fails, it indicates that the detected unit has a defect, and the defect needs to be further located.
Preferably, the fault library classifies faults into regular faults, abnormal faults, and boundary faults in S1.
Preferably, the S2 includes:
s21, randomly selecting one or more faults of different categories from the fault library, and inserting the faults into tested units of the circuit test platform according to the RTL level insertion mode corresponding to the selected faults;
s22, operating the circuit testing platform, if the circuit testing platform locates the fault, then entering step S23, if the fault is not located, then entering step S24;
s23, judging whether the fault library needs to be traversed continuously, if yes, circularly entering the step S21, and if not, finishing the evaluation of the circuit testing platform;
s24, the circuit testing platform is corrected, and the step S22 is re-entered after the correction is completed.
Preferably, in S24, modifying the circuit test platform includes: adjusting the reference model and/or adjusting the constraints of the test case.
The invention also provides another technical scheme: a quality assessment apparatus for a circuit test platform, comprising: a fault library establishing module, a fault inserting module and a quality evaluating module, wherein,
the fault library establishing module is used for establishing a fault library, and the fault library is used for classifying faults and defining an RTL level insertion mode corresponding to the faults;
the fault insertion module is used for inserting the fault in the fault library into a tested unit of the circuit testing platform according to the corresponding RTL level insertion mode;
the quality evaluation module is used for evaluating the quality of the circuit test platform according to whether the circuit test platform can detect the fault when the circuit test platform runs.
Preferably, the fault insertion module comprises: a fault selection unit and a fault insertion unit connected to the fault selection unit, wherein,
the fault selection unit is used for randomly selecting one or more different types of faults from a fault library;
and the fault insertion unit is used for inserting the fault selected by the fault selection unit into the tested unit of the circuit test platform according to the RTL level insertion mode corresponding to the selected fault.
Preferably, the quality assessment module comprises: a platform operation unit, a fault detection and judgment unit, a platform correction unit, a traversal fault library judgment unit and an evaluation completion unit, wherein,
the platform operation unit is connected with the fault insertion unit and used for operating the circuit test platform;
the fault detection judging unit is connected with the platform operation unit, the traversal fault library judging unit and the platform correcting unit and is used for judging whether the circuit testing platform locates the fault when the circuit testing platform operates;
the platform correction unit is connected with the circuit test platform and used for correcting the circuit test platform after the fault detection judgment unit judges that the circuit test platform is not positioned with the fault, and the platform correction unit enters the platform operation unit after the correction is finished;
the traversal fault library judging unit is connected with the fault detection judging unit, the fault selecting unit and the evaluation finishing unit and is used for judging whether to continue traversing the fault library or not after the fault detection judging unit judges that the circuit testing platform locates the fault, and if so, entering the fault selecting unit; if not, entering an evaluation completion unit.
The invention has the beneficial effects that: the invention utilizes the fault library which sets the fault category and the fault RTL level insertion mode to insert some random faults in the tested and designed RTL level, and evaluates whether the circuit test platform is complete and reliable in advance by judging whether the faults can be positioned efficiently and accurately in the regression test process, namely, the evaluation work of the completeness and reliability of the circuit test platform is advanced, so that the invention is more efficient, completes the evaluation work in a more targeted manner and provides a good auxiliary action for the traditional evaluation method.
Drawings
FIG. 1 is a block diagram of the structure of a circuit test platform created by the present invention;
FIG. 2 is a schematic flow diagram of the process of the present invention;
FIG. 3 is a schematic flow chart of step A3 in FIG. 2;
FIG. 4 is a block diagram of the apparatus of the present invention;
FIG. 5 is a functional block diagram of the quality assessment module of FIG. 4.
Detailed Description
The technical solution of the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention.
According to the quality evaluation method and device for the circuit test platform, disclosed by the invention, random faults are inserted into the RTL level by setting the fault rule base, and whether the faults can be efficiently and accurately positioned in the regression test process is judged so as to evaluate whether the circuit test platform is complete and reliable in advance.
Referring to fig. 1 to fig. 3, a method for evaluating the quality of a circuit testing platform according to an embodiment of the present invention includes:
a1, a circuit test platform to be evaluated is created.
Specifically, as shown in fig. 1, the circuit test platform created in the present embodiment includes: the device comprises an excitation Generator (Driver Generator), a unit under test (DUT), a Reference Model (Reference Model) and a Comparator (Comparator), wherein the excitation Generator is connected with the input ends of the unit under test and the Reference Model and is used for sending random test excitation of test cases to the unit under test and the Reference Model; the tested unit is a circuit to be tested; the reference model is used for simulating the functions of the tested unit; the output ends of the tested unit and the reference model are connected with the comparator, the outputs of the tested unit and the reference model are respectively sent to the comparator to complete result comparison, if the comparison is passed, the test case passes and the tested unit is free of defects; if the comparison fails, the detected unit is determined to have a defect, and the defect needs to be further positioned.
A2, establishing a fault library, wherein the fault library is used for classifying faults and defining RTL level insertion modes corresponding to the faults.
Specifically, in this embodiment, the faults are divided into normal faults, abnormal faults, and boundary faults in the fault library, and an RTL level insertion manner corresponding to each type of fault is defined. Wherein, the conventional failure: generally refers to a logical operation error, such as: the original AND logic is modified into OR logic, the original equal operation is modified into unequal operation, the original condition judgment logic is deleted, and the like. Abnormal failure: generally refers to faults in error exception handling, such as: adding an exception generating logic, generating an overflow or underflow fault of FIFO (First Input First Output), generating a memory error correction fault, generating a logic exception interrupt fault, generating an information disorder fault and the like.
A3, inserting the fault in the fault library into the tested unit of the circuit test platform according to the corresponding RTL level insertion mode, operating the circuit test platform, and evaluating the quality of the circuit test platform according to whether the circuit test platform can detect the fault.
Specifically, as shown in fig. 3, step a3 specifically includes:
a31, before testing, randomly selecting one or more faults of different categories from a fault library, and inserting the faults into a tested unit of a circuit testing platform according to an RTL level insertion mode corresponding to the selected faults.
And A32, setting effective test cases for evaluating the fault positioning capability of the circuit test platform, and operating the circuit test platform, namely operating the circuit test platform according to the working principle in A1. If the circuit test platform can prepare to locate the corresponding fault inserted in the tested unit within the limited test case time, the detection of the fault by the circuit test platform is better detective, and the step A33 is carried out; if the corresponding fault is not located, indicating that the circuit test platform has a defect in detecting the fault, the following step a34 is performed.
And A33, judging whether the fault library needs to be traversed continuously, namely judging whether the fault library needs to be selected continuously, and inserting the fault library into the tested unit of the circuit testing platform for fault detection. If so, circularly entering the step A31 until the fault which is effective for the tested unit in the fault library is traversed; if not, the fault library indicates that all faults in the fault library are completely inserted into the unit under test and positioning detection is completed, so that the evaluation of the circuit test platform is completed.
And A34, modifying the circuit test platform, and re-entering the step A32 after the modification is completed.
Specifically, the reference model is adjusted and/or the constraint conditions of the test case are adjusted to overcome the defect of the circuit test platform in detecting the undetected faults. After the circuit testing platform is corrected, that is, after the circuit testing platform can position and detect the fault, the process re-enters step a32 to operate the circuit testing platform to position and detect the fault.
Therefore, after the circuit test platform finishes evaluation, namely after the effective faults aiming at the tested unit in the fault library are traversed, the detection success rate of the circuit test platform for the three types of faults can be obtained, and the completeness and the reliability degree of the circuit test platform can be judged.
Referring to fig. 4 and 5, a quality evaluation apparatus for a circuit testing platform according to an embodiment of the present invention includes: the fault database establishing module is used for establishing a fault database, the fault database is used for classifying faults and defining RTL level insertion modes corresponding to the faults, and the specific classification types can be described with reference to the step A2.
And the fault insertion module is used for inserting the faults in the fault library into the tested unit of the circuit test platform according to the corresponding RTL level insertion mode. In the embodiment, the fault detection device specifically comprises a fault selection unit and a fault insertion unit connected with the fault selection unit, wherein the fault selection unit is used for randomly selecting one or more faults of different categories from a fault library; and the fault insertion unit is used for inserting the fault selected by the fault selection unit into the tested unit of the circuit test platform according to the RTL level insertion mode corresponding to the selected fault.
And the quality evaluation module is used for evaluating the quality of the circuit test platform according to whether the circuit test platform can detect the fault when the circuit test platform runs. In this embodiment, as shown in fig. 5, the system specifically includes a platform operating unit, a fault detection and determination unit, a platform modification unit, a traversal fault library determination unit, and an evaluation completion unit, wherein,
and the platform operation unit is connected with the fault insertion unit and is used for operating the circuit test platform.
The fault detection and judgment unit is connected with the platform operation unit, the traversal fault library judgment unit and the platform correction unit and is used for judging whether the circuit test platform locates the fault when the circuit test platform operates.
The platform correction unit is connected with the circuit test platform and used for correcting the circuit test platform after the fault detection judgment unit judges that the circuit test platform is not positioned with the fault, and the corrected circuit test platform enters the platform operation unit after the correction is completed.
The traversal fault library judging unit is connected with the fault detection judging unit, the fault selecting unit and the evaluation finishing unit and is used for judging whether to continue traversing the fault library or not after the fault detection judging unit judges that the circuit testing platform locates the fault, and if so, entering the fault selecting unit; if not, entering an evaluation completion unit.
Therefore, the scope of the present invention should not be limited to the disclosure of the embodiments, but includes various alternatives and modifications without departing from the scope of the present invention, which is defined by the claims of the present patent application.
Claims (8)
1. A quality evaluation method of a circuit test platform is characterized by comprising the following steps:
s1, establishing a fault library, wherein the fault library is used for classifying faults and defining RTL level insertion modes corresponding to the faults;
s2, inserting the fault in the fault library into the unit under test of the circuit test platform according to the corresponding RTL level insertion manner, operating the circuit test platform, and evaluating the quality of the circuit test platform according to whether the circuit test platform can detect the fault, where S2 includes:
s21, randomly selecting one or more faults of different categories from the fault library, and inserting the faults into tested units of the circuit test platform according to the RTL level insertion mode corresponding to the selected faults;
s22, operating the circuit testing platform, if the circuit testing platform locates the fault, then entering step S23, if the fault is not located, then entering step S24;
s23, judging whether the fault library needs to be traversed continuously, if yes, circularly entering the step S21, and if not, finishing the evaluation of the circuit testing platform;
s24, the circuit testing platform is corrected, and the step S22 is re-entered after the correction is completed.
2. The method of claim 1, further comprising: creating the circuit testing platform to be evaluated.
3. The method of claim 2, wherein the circuit test platform comprises a stimulus generator, the unit under test, a reference model for simulating the function of the unit under test, and a comparator, wherein,
the excitation generator is connected with the tested unit and the reference model and is used for sending random test excitation of the test case to the tested unit and the reference model;
and the tested unit and the reference model are both connected with the comparator, the outputs of the two are respectively sent to the comparator to complete result comparison, and if the comparison is passed, the test case passes and the tested unit is free of defects.
4. The method as claimed in claim 3, wherein if the comparison fails, it indicates that the unit under test has a defect, and the defect needs to be further located.
5. The method for quality evaluation of a circuit testing platform of claim 1, wherein in S1, said fault library classifies faults into regular faults, abnormal faults, and boundary faults.
6. The method for quality evaluation of a circuit testing platform according to claim 1, wherein in S24, modifying the circuit testing platform comprises: adjusting the reference model and/or adjusting the constraints of the test case.
7. A quality evaluation apparatus for a circuit test platform, comprising: a fault library establishing module, a fault inserting module and a quality evaluating module, wherein,
the fault library establishing module is used for establishing a fault library, and the fault library is used for classifying faults and defining an RTL level insertion mode corresponding to the faults;
the fault insertion module is used for inserting the fault in the fault library into a tested unit of the circuit testing platform according to the corresponding RTL level insertion mode;
the quality evaluation module is used for evaluating the quality of the circuit test platform by judging whether the circuit test platform can detect the fault or not when the circuit test platform runs, and comprises a platform running unit, a fault detection judging unit, a platform correcting unit, a traversal fault base judging unit and an evaluation finishing unit, wherein,
the platform operation unit is connected with the fault insertion module and used for operating the circuit test platform;
the fault detection judging unit is connected with the platform operation unit, the traversal fault library judging unit and the platform correcting unit and is used for judging whether the circuit testing platform locates the fault when the circuit testing platform operates;
the platform correction unit is connected with the circuit test platform and used for correcting the circuit test platform after the fault detection judgment unit judges that the circuit test platform is not positioned with the fault, and entering the platform operation unit after the correction is finished;
the traversal fault library judging unit is connected with the fault detection judging unit, the fault insertion module and the evaluation completing unit and is used for judging whether to continue traversing the fault library or not after the fault detection judging unit judges that the circuit testing platform locates the fault, and if so, entering the fault selection unit; if not, entering an evaluation completion unit.
8. The quality evaluation apparatus of the circuit test platform according to claim 7,
the fault insertion module comprises: a fault selection unit and a fault insertion unit connected to the fault selection unit, wherein,
the fault selection unit is used for randomly selecting one or more different types of faults from a fault library;
and the fault insertion unit is used for inserting the fault selected by the fault selection unit into the tested unit of the circuit test platform according to the RTL level insertion mode corresponding to the selected fault.
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