CN117290254A - Chip verification method based on component automation - Google Patents
Chip verification method based on component automation Download PDFInfo
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- CN117290254A CN117290254A CN202311576555.6A CN202311576555A CN117290254A CN 117290254 A CN117290254 A CN 117290254A CN 202311576555 A CN202311576555 A CN 202311576555A CN 117290254 A CN117290254 A CN 117290254A
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- 238000012795 verification Methods 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000005284 excitation Effects 0.000 claims description 19
- 125000004122 cyclic group Chemical group 0.000 claims description 9
- 238000012544 monitoring process Methods 0.000 claims description 4
- 238000004088 simulation Methods 0.000 claims description 3
- 238000013461 design Methods 0.000 description 10
- 239000003795 chemical substances by application Substances 0.000 description 5
- 238000013459 approach Methods 0.000 description 3
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000003607 modifier Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3696—Methods or tools to render software testable
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3684—Test management for test design, e.g. generating new test cases
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/36—Software reuse
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Abstract
The invention provides a chip verification method based on component automation, and belongs to the technical field of chip verification. According to the scheme, the components required by the verification platform are defined in the text file, then the verification platform reads the text file, dynamically instantiates the corresponding components, and automatically completes component interconnection, so that the flexibility of the verification platform is greatly expanded, and the coding efficiency and accuracy of the chip verification platform are improved.
Description
Technical Field
The invention belongs to the technical field of chip verification, and particularly relates to a chip verification method based on component automation.
Background
As chip scale increases, the variety and number of interfaces between modules or chip subsystems (hereinafter referred to as designs under test or DUTs) increases. Each interface of the DUT should be connected to a component as a driving unit or a monitoring unit, so that the structure of the verification platform is more and more complex.
Existing platform creation approaches typically connect platform components one by one across each set of interfaces. The method comprises the following steps: step S1, writing verification platform component codes (agents or subenvs), or using existing component codes (VIP or UVC); step S2, instantiating a component in the verification platform, and carrying out necessary configuration on the component; step S3, connecting the components with interfaces to be designed one by one; step S4, connecting a data driving port of the component to an excitation generating unit of the verification platform; step S5, connecting a data sampling port of the component to an expected value generating unit or an output value comparing unit of the verification platform; s6, repeating the steps S2-S5 until all interfaces of the design to be tested are connected to the platform assembly; step S7, generating excitation, selecting a proper driving port for the excitation, and then sending the excitation to the design to be tested.
The platform creation mode has the advantages of simple code writing, each interface corresponding to instantiates one component, and each component is explicitly declared. But has the following problems:
1. the efficiency is low. The more interfaces of the design to be tested are, the more components are connected, so that a plurality of similar codes exist in the platform, the code writing efficiency is low, and writing errors are easy to occur.
2. The flexibility is low, and the code is difficult to multiplex and expand. If the type or number of interfaces is changed during the project execution or migration, the code to be rewritten will be much, which is equivalent to rewriting the connection relationship of the platform assembly once, and much work is needed.
3. Code readability is poor. Because there are many similar codes in the platform, it is inconvenient to read.
Disclosure of Invention
Aiming at the technical problems, the invention provides a chip verification method based on component automation, which is used for expanding the flexibility of a verification platform and improving the coding efficiency and accuracy of the chip verification platform.
The first aspect of the invention provides a chip verification method based on component automation, which comprises the following steps:
s1, writing agents or subenvs of interface components required by an authentication platform according to the type of an interface to be designed, or acquiring the existing VIP or UVC;
s2, creating a text, and listing necessary parameters of the interface component in the text;
s3, in the simulation starting stage, the simulator reads text content in the text, instantiates the interface component according to the text content and completes configuration;
s4, connecting the interface component and the module to be tested according to a defined connection rule by adopting a cyclic traversal method;
s5, connecting a driving unit of the interface assembly to an excitation generation unit of the verification platform by adopting a cyclic traversal method, and connecting a monitoring unit of the interface assembly to an expected value generation unit or an output value comparison unit of the verification platform;
s6, generating excitation, selecting a driving port for excitation through the index of the array or the queue, and sending the driving port to the module to be tested.
Further, the necessary parameters in step S2 include a component type, a component name, a data bit width, and a connection rule between the interface of the module to be tested.
Further, in step S3, the instantiating component according to the text content includes: instantiating the platform assembly using a plurality of data types; the data comprises a fixed-width array, a dynamic array, an associated array and a queue.
Further, the text in step S2 is text in a form of a table.
Further, the text in step S2 is a json-form text.
According to the scheme, the components required by the verification platform are defined in the text file, then the verification platform reads the text file, dynamically instantiates the corresponding components, and automatically completes component interconnection, so that the flexibility of the verification platform is greatly expanded, and the coding efficiency and accuracy of the chip verification platform are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a component automation-based chip verification method in the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second, third, etc. or module a, module B, module C and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order, and it is to be understood that the specific order or sequence may be interchanged if permitted to implement embodiments of the invention described herein in other than those illustrated or described.
In the following description, reference numerals indicating steps such as S110, S120, … …, etc. do not necessarily indicate that the steps are performed in this order, and the order of the steps may be interchanged or performed simultaneously as allowed.
The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Thus, it should be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the expression "a device comprising means a and B" should not be limited to a device consisting of only components a and B.
Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments as would be apparent to one of ordinary skill in the art from this disclosure.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. If there is a discrepancy, the meaning described in the present specification or the meaning obtained from the content described in the present specification is used. In addition, the terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to be limiting of the invention.
Referring to fig. 1, the embodiment of the invention discloses a chip verification method based on component automation, which comprises the following steps:
s1, writing agents or subenvs of interface components required by an authentication platform according to the type of an interface to be designed, or acquiring the existing VIP or UVC;
wherein the interface type may be obtained according to design requirements or verification requirements, including but not limited to AXI/APB/AHB, etc. And the VIP or UVC is a component possibly used in the verification platform, is a verification code provided (verified and adopted for multiple times) by a third party, and can generate correct circuit behavior according to a protocol, so that the agent or subenv of the interface component can be directly obtained. Thus, the invention can be incorporated into the scheme of the invention whether the verifier writes a code meeting the protocol requirements (i.e., the agent or the subenv) by himself or purchases the code provided by the third party.
S2, creating a text, and listing necessary parameters of the interface component in the text;
s3, in the simulation starting stage, the simulator reads text content in the text, instantiates the interface component according to the text content and completes configuration;
and writing a verification platform, reading text contents by the simulator, instantiating components according to the text contents, wherein different components can correspond to different component types, have different names or data bit widths and the like, and the components of the same type form a data structure.
S4, connecting the interface component and the module to be tested according to a defined connection rule by adopting a cyclic traversal method;
s5, connecting a driving unit of the interface assembly to an excitation generation unit of the verification platform by adopting a cyclic traversal method, and connecting a monitoring unit of the interface assembly to an expected value generation unit or an output value comparison unit of the verification platform;
s6, generating excitation, selecting a driving port for excitation through the index of the array or the queue, and sending the driving port to the module to be tested.
Further, the necessary parameters in step S2 include, but are not limited to, component type, component name, data bit width, connection rule between the interface with the module under test, etc.
The interface components to be used are listed in the text, and the corresponding names, types, data bit widths, etc. are specified.
Further, in step S3, the instantiating component according to the text content includes: instantiating the platform assembly using a plurality of data types; wherein the data includes, but is not limited to, a fixed width array, a dynamic array, an associative array, a queue, and the like.
Further, the text in step S2 is text in a form of a table.
The interface components may be listed in tabular form text, with the contents of each column being fixed, for example:
| component name | Component type | Data bit width |
| PortA | AXI | 64 |
| PortB | AXI | 32 |
| PortC | AXI | 256 |
The data bit widths of the components in the above table may each be unequal. In addition, other columns may be added to define other data content on the interface.
Based on the above example table, the scheme of the invention is as follows:
writing a verification platform, reading definitions of the interface components one by one, and instantiating the interface components. In the above example, portA is created using an AXI type component, setting the data bit width of the component to 64; creating a PortB by using an AXI type component, and setting the data bit width of the component to be 32; portC is created using an AXI type component, setting the data bit width of the component to 256. The instantiated components are all stored in a queue.
And connecting the components and the design to be tested in a cyclic traversal mode.
The components and platform are connected using a loop traversal approach.
Generating excitation, namely finding PortA, portB, portC components by using indexes 0, 1 and 2 respectively, and sending out the excitation; the component receives the excitation to complete the driving of the design interface to be tested.
Further, the text in step S2 is a json-form text.
Based on the example table above, interface components are listed in json format text, such as:
{
“PortA”: {
“type”: “APB”,
“width”: “64”
},
“PortB”: {
“type”: “APB”,
“width”: “32”
},
“PortC”: {
“type”: “APB”,
“width”: “256”
}
}
at this time, the scheme of the invention becomes:
and writing a verification platform, reading and analyzing the text, instantiating an interface component according to the text content, and storing the instantiated interface component in an associated array, wherein indexes of the associated array are PortA, portB and PortC respectively.
And connecting the components and the design to be tested in a cyclic traversal mode.
The components and platform are connected using a loop traversal approach.
Generating excitation, using the component name as an index, finding PortA, portB, portC components in the associated array, and sending out the excitation; the component receives the excitation to complete the driving of the design interface to be tested.
Compared with the prior art, the invention has the following advantages:
1. and the code writing efficiency is improved. Compared with a mode of listing interfaces one by one, the method creates the interface components by using a cyclic traversal mode, reduces the code quantity and reduces the error rate of code writing.
2. The code flexibility is high, and the expandability is strong. Any change or migration of the project can be realized by only changing text content, so that the related change of the platform is completed, the code modifier is less, and the working efficiency is improved.
3. Code readability is improved. The platform design of the scheme removes a plurality of similar codes, and the codes are easier to understand.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the above embodiments, but may include many other equivalent embodiments without departing from the spirit of the invention, which fall within the scope of the invention.
Claims (5)
1. The chip verification method based on the component automation is characterized by comprising the following steps of:
s1, writing agents or subenvs of interface components required by an authentication platform according to the type of an interface to be designed, or acquiring the existing VIP or UVC;
s2, creating a text, and listing necessary parameters of the interface component in the text;
s3, in the simulation starting stage, the simulator reads text content in the text, instantiates the interface component according to the text content and completes configuration;
s4, connecting the interface component and the module to be tested according to a defined connection rule by adopting a cyclic traversal method;
s5, connecting a driving unit of the interface assembly to an excitation generation unit of the verification platform by adopting a cyclic traversal method, and connecting a monitoring unit of the interface assembly to an expected value generation unit or an output value comparison unit of the verification platform;
s6, generating excitation, selecting a driving port for excitation through the index of the array or the queue, and sending the driving port to the module to be tested.
2. The component automation based chip verification method according to claim 1, wherein: the necessary parameters in step S2 include a component type, a component name, a data bit width, and a connection rule between the interface of the module to be tested.
3. The component automation based chip verification method according to claim 1, wherein: in step S3, the instantiating a component according to the text content includes: instantiating the platform assembly using a plurality of data types; the data comprises a fixed-width array, a dynamic array, an associated array and a queue.
4. The component automation based chip verification method according to claim 1, wherein: the text in step S2 is text in tabular form.
5. The component automation based chip verification method according to claim 1, wherein: the text in step S2 is a json-form text.
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