CN111190786A

CN111190786A - UVM-based test framework, test platform and test method

Info

Publication number: CN111190786A
Application number: CN201911422845.9A
Authority: CN
Inventors: 陈岩; 薛江
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2020-05-22

Abstract

The embodiment of the application provides a test framework, a test platform and a test method based on UVM, wherein the test framework comprises a software case, an input unit and an output unit, the software case comprises a first test instruction, the input unit is in communication connection with the software case, and the input unit is used for acquiring the first test instruction from the software case, generating a first instruction packet according to the first test instruction and transmitting a first binary instruction to a module to be tested; the output unit is used for being in communication connection with the module to be tested and used for receiving a first test result obtained by the module to be tested running a first binary instruction. Based on this, the input unit can acquire the first test instruction with the application scene and the first test instruction sequence from the software case, and due to the constraint of the application scene, the random space of the first test instruction sequence can be reduced, the length of the first test instruction sequence acquired by the input unit is reduced, and finally the test efficiency can be improved.

Description

UVM-based test framework, test platform and test method

Technical Field

The present disclosure relates to the field of chip verification technologies, and in particular, to a test framework, a test platform, and a test method based on a Universal Verification Methodology (UVM).

Background

With the continuous abundance of computer functions, in the design of computer chips, test verification becomes the most expensive work in the whole chip development process, and the proportion of the test verification in the whole design cycle is larger and larger. Therefore, it has become critical to improve the efficiency of chip test verification. How to efficiently test the functions of the computer core is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

The embodiment of the application provides a verification framework, a test platform and a test method based on UVM, and verification efficiency can be improved.

In a first aspect, an embodiment of the present application provides a UVM-based test framework, including:

the software use case comprises a first test instruction;

the input unit is in communication connection with the software case, and is used for acquiring the first test instruction from the software case and generating a first instruction packet according to the first test instruction, wherein the first instruction packet at least comprises a first binary instruction, and the input unit is also used for transmitting the first binary instruction to a module to be tested;

and the output unit is used for being in communication connection with the module to be tested and receiving a first test result obtained by the module to be tested running the first binary instruction.

In a second aspect, an embodiment of the present application further provides a UVM-based test framework, including:

an instruction library, the instruction library comprising second test instructions;

the input unit is in communication connection with the instruction library, and is used for acquiring the second test instruction from the instruction library and generating a second instruction packet according to the second test instruction, wherein the second instruction packet at least comprises a second binary instruction, and the input unit is also used for transmitting the second binary instruction to a module to be tested;

and the output unit is used for being in communication connection with the module to be tested and receiving a second test result obtained by the module to be tested running the second binary instruction.

In a third aspect, an embodiment of the present application further provides a test platform based on UVM, including:

a module to be tested;

a test framework comprising a test framework as defined in any of the above, the module to be tested being for testing by the test framework.

In a fourth aspect, an embodiment of the present application further provides a test method based on UVM, which is applied to a test platform and a test framework, where the test platform includes a module to be tested and the test framework, the test framework includes a software use case, an input unit, and an output unit, the input unit is in communication connection with the software use case, the output unit is in communication connection with the module to be tested, and the software use case includes a first test instruction;

the UVM-based testing method comprises the following steps:

the input unit acquires the first test instruction from the software case and generates a first instruction packet according to the first test instruction, wherein the first instruction packet at least comprises a first binary instruction;

the input unit transmits the first binary instruction to the module to be tested;

the module to be tested runs the first binary instruction and obtains a first test result;

and the module to be tested transmits the first test result to the output unit.

In a fifth aspect, an embodiment of the present application further provides a test method based on UVM, which is applied to a test platform and a test framework, where the test platform includes a module to be tested and the test framework, the test framework includes an instruction library, an input unit and an output unit, the input unit is in communication connection with the instruction library, the output unit is in communication connection with the module to be tested, and the instruction library includes a second test instruction;

the UVM-based testing method comprises the following steps:

the input unit acquires the second test instruction from the instruction library and generates a second instruction packet according to the second test instruction, wherein the second instruction packet at least comprises a second binary instruction;

the input unit transmits the second binary instruction to the module to be tested;

the module to be tested runs the second binary instruction and obtains a second test result;

and the module to be tested transmits the second test result to the output unit.

According to the test platform, the test framework and the test method, the input unit obtains the first test instruction from the software case, the input unit can directly obtain the first test instruction with the application scene and the first test instruction sequence, due to the constraint of the application scene, the random space of the first test instruction sequence can be reduced, the length of the first test instruction sequence obtained by the input unit is reduced, and finally the test efficiency can be improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

Fig. 1 is a schematic structural diagram of a test platform according to an embodiment of the present disclosure.

Fig. 2 is an application diagram of a first test framework provided in the embodiment of the present application.

Fig. 3 is an application diagram of a second test framework provided in the embodiment of the present application.

Fig. 4 is a schematic application diagram of a third test framework provided in the embodiment of the present application.

FIG. 5 is a schematic diagram of an application of a fourth test framework provided in the embodiment of the present application.

FIG. 6 is a schematic diagram of an application of a fifth test framework provided in the embodiment of the present application.

FIG. 7 is a schematic flow chart illustrating the verification of the module under test according to the test framework in FIG. 6.

Fig. 8 is an application diagram of a sixth test framework provided in the embodiment of the present application.

Fig. 9 is an application diagram of a seventh test framework provided in the embodiment of the present application.

Fig. 10 is a schematic application diagram of an eighth test framework provided in the embodiment of the present application.

FIG. 11 is a flow chart illustrating the verification of a module under test according to the test framework of FIG. 10.

Fig. 12 is an application diagram of a ninth test framework provided in the embodiment of the present application.

Fig. 13 is an application diagram of a tenth test framework provided in the embodiment of the present application.

Fig. 14 is an application diagram of an eleventh test framework provided in the embodiment of the present application.

FIG. 15 is a flow chart illustrating the verification of a module under test according to the test framework of FIG. 14.

Fig. 16 is an application diagram of a twelfth test framework provided in the embodiment of the present application.

Fig. 17 is a schematic application diagram of a thirteenth test framework provided in the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The embodiment of the application provides a test platform 100 and a test framework 200 based on UVM. Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a test platform according to an embodiment of the present disclosure, and fig. 2 is a schematic application diagram of a first test framework according to an embodiment of the present disclosure. The test platform 100 includes a test framework 200 and a module under test 300, the module under test 300 being used for testing through the test framework 200. The test framework 200 may include test cases 210, input units 220, and output units 230; the test case 210 may be communicatively coupled to the input unit 220, the input unit 220 may be communicatively coupled to the module under test 300, and the module under test 300 may be communicatively coupled to the output unit 230.

The test case 210 may be used to instantiate the test platform 100 and the test framework 200, and complete information configuration of the test platform 100 and the test framework 200, so that the test platform 100 and the test framework 200 may test the module 300 to be tested. The test cases 210 may also be used to build test scenarios according to test requirements. The test case 210 may include a test instruction, and the module under test 300 may execute the test instruction and perform a test. The input unit 220 may be configured to obtain a test instruction from the test case 210, and the input unit 220 may also be configured to randomly generate the test instruction according to an instruction of the test case 210. After randomly obtaining or randomly generating the test instruction, the input unit 220 may be configured to analyze the module to be tested 300 or the sub-module of the module to be tested 300 where the test instruction is used for testing, so that the module to be tested 300 or the sub-module of the module to be tested 300 runs the test instruction to perform testing. The module to be tested 300 may obtain a first test result by running the test instruction, and the output unit 230 may be configured to receive the first test result transmitted by the module to be tested 300. Thus, the test case 210, the input unit 220 and the output unit 230 cooperate with each other to test the module to be tested 300 or the sub-modules of the module to be tested 300.

It is understood that in actual testing, in order to complete a certain test, the input unit 220 needs to continuously obtain a plurality of test instructions, which may form a test instruction sequence. The input unit 220 may sequentially transmit each test instruction to the module to be tested 300 according to the obtained sequence, and the module to be tested 300 sequentially runs each test instruction, thereby finally completing the test.

Referring to fig. 3, fig. 3 is a schematic application diagram of a second test framework according to an embodiment of the present application. The input unit 220 of the test framework 200 of the embodiment of the present application may include components such as an excitation generator 221, a driving module 223, a monitoring module 224, and an interface module 225; the output unit 230 may include a reference model 231 and a scoreboard 232. The input end of the excitation generator 221 may be communicatively connected to the test case 210, the output end of the excitation generator 221 may be communicatively connected to the input end of the driving module 223, the output end of the driving module 223 may be communicatively connected to the input end of the interface module 225, the output end of the interface module 225 may be communicatively connected to the input end of the module 300 to be tested, and the output end of the module 300 to be tested may be communicatively connected to the scoreboard 232. Meanwhile, the input terminal of the monitoring module 224 may be communicatively connected to the input terminal of the interface module 225, the output terminal of the monitoring module 224 may be communicatively connected to the input terminal of the reference model 231, and the output terminal of the reference model 231 may be communicatively connected to the score calculating board 232.

As shown in FIG. 3, the stimulus generator 221 may be configured to randomly select test instructions from the test cases 210, and the stimulus generator 221 may also be configured to randomly generate test instructions according to the instructions of the test cases 210. The randomly selected or randomly generated test instructions by the stimulus generator 221 may be binary instructions, and the stimulus generator 221 transmits the binary form of the test instructions to the driver module 223. The driving module 223 may be configured to transmit the test instruction to the module to be tested 300 through the interface module 225, the interface module 225 may transmit the test instruction to the module to be tested 300 and the corresponding sub-module thereof, the module to be tested 300 and the corresponding sub-module thereof run the test instruction and obtain a first test result, and the module to be tested 300 may transmit the first test result to the score board 232. Meanwhile, the monitoring module 224 is used for obtaining the test instruction from the interface module 225 and sending the test instruction to the reference model 231. The reference model 231 may be used to run the test instructions and obtain a second test result, and the score board 232 may be used to receive the first test result and the second test result and compare the first test result and the second test result.

It can be understood that, when the first test result is the same as the second test result, it indicates that the module to be tested 300 is operating normally in the above-mentioned operation process, and when the first test result is different from the second test result, it indicates that the module to be tested 300 has an abnormal operation problem in the above-mentioned operation process. And then, the tester can perform subsequent troubleshooting and analysis work according to the first test result and the second test result. According to the test framework 200 of the embodiment of the application, through the mutual cooperation of the excitation generator 221, the driving module 223, the interface module 225, the monitoring module 224, the reference model 231 and the scoring board 232, the scoring board 232 can compare and judge the accuracy of the first test result, so that the test accuracy of the test platform 100 and the test framework 200 is further improved.

When the module to be tested 300 includes a plurality of sub-modules to be tested, please refer to fig. 4, and fig. 4 is an application diagram of a third testing framework provided in the embodiment of the present application. The input unit 220 of the test framework 200 may include an equal number of stimulus generators 221, driver modules 223 and monitor modules 224, and correspondingly, the interface module 225 may include a plurality of sub-interfaces. Each excitation generator 221 is in communication connection with the test case 210, one excitation generator 221 is in communication connection with one driving module 223, each driving module 223 is in communication connection with the module to be tested 300 through a sub-interface of the interface module 225, and each monitoring module 224 is in communication connection with the output unit 230, for example, the reference model 231. Furthermore, a stimulus generator 221, a driver module 223 and a monitoring module 224 form a transaction unit 240, and the transaction unit 240 is communicatively connected to a submodule of the module under test 300 via a subinterface of the module under test 300, so that a submodule can be tested via the transaction unit 240.

As shown in fig. 4, each stimulus generator 221 is configured to identify and analyze a test instruction of the test case 210, and transmit the test instruction (which refers to a test instruction that needs to test a target sub-module, where the target sub-module refers to a sub-module of the module to be tested 300 that is communicatively connected to the stimulus generator 221 through the corresponding driver module 223 and the interface module 225) that belongs to the stimulus generator 221 to one driver module 223 that belongs to the same transaction unit 240. A driver module 223 transmits the test case 210 to a target sub-module of the module to be tested 300 communicatively connected to the driver module through a sub-interface of the interface module 225, the target sub-module runs the test case 210 and obtains a first test result, and the target sub-module may transmit the first test result to the output unit 230, for example, the score counting board 232. Meanwhile, each monitoring module 224 obtains a test instruction from a subinterface connected to the module to be tested 300 belonging to the same transaction unit 240, and transmits the test instruction to the output unit 230, for example, the reference model 231 runs the test instruction and obtains a second test result, the reference model 231 may transmit the second test result to the score board 232, and the score board 232 may be configured to receive the first test result and the second test result, and compare the first test result and the second test result, so that the submodules of the module to be tested 300 may be tested.

Based on the test framework 200 shown in fig. 1 to fig. 4, please refer to fig. 5 for improving the test accuracy, and fig. 5 is a schematic application diagram of a fourth test framework according to an embodiment of the present application. The input unit 220 of the test framework 200 of the present embodiment may also include a virtual stimulus generator 222. The virtual stimulus generator 222 may be communicatively connected to the test case 210, and the virtual stimulus generator 222 is configured to obtain a test instruction from the test case 210 according to a random scenario and transmit the test instruction to the module 300 to be tested. The output unit 230 may be configured to be in communication connection with the module to be tested 300, and the output unit 230 may be configured to receive a first test result obtained by the module to be tested 300 running the test instruction.

It can be understood that, the virtual stimulus generator 222 is configured to obtain the test instruction from the test case 210 according to a random scenario, which may mean that the virtual stimulus generator 222 randomly generates the test instruction according to the random scenario and the constraint of the test case 210; it may also mean that the virtual stimulus generator 222 obtains test instructions from the test cases 210 according to the constraints of the random scenario.

The module to be tested 300 can be tested based on the test framework 200 shown in fig. 5, and based on this, the embodiment of the present application provides a test method based on UVM, which includes: the virtual excitation generator 222 acquires a test instruction from the test case 210 according to the random scene, and transmits the test instruction to the module to be tested 300; the module to be tested 300 runs the test instruction and obtains a first test result; the module under test 300 transmits the first test result to the output unit 230.

In the test platform 100, the test framework 200 and the test method according to the embodiment of the application, the virtual stimulus generator 222 may be configured to create different random scenes, and according to the different random scenes, the virtual stimulus generator 222 may randomly obtain a test instruction from the test case 210, and the virtual stimulus generator 222 may also randomly generate the test instruction according to the different random scenes. Compared to the excitation generator 221 randomly acquiring/generating the test commands, the module under test 300 performs the test according to the different test commands, so as to improve the accuracy of the test.

Based on the foregoing test framework 200, the input unit 220 of the test framework 200 may further include modules such as an excitation generator 221, a driving module 223, a monitoring module 224, and an interface module 225; the output unit 230 may include a reference model 231 and a scoreboard 232. An input of the virtual stimulus generator 222 may be communicatively coupled to the test case 210, and an output of the virtual stimulus generator 222 may be communicatively coupled to an input of the stimulus generator 221. When the module to be tested 300 includes a plurality of sub-modules to be tested, the input unit 220 of the test framework 200 of the embodiment of the present application may further include a plurality of stimulus generators 221, a driving module 223, a monitoring module 224, an interface module 225, and the like. The input of each stimulus generator 221 is communicatively coupled to a virtual stimulus generator 222, and the output of each stimulus generator 221 is communicatively coupled to a driver module 223. The connection between the excitation generator 221, the driving module 223, the monitoring module 224, the interface module 225, the scoreboard 232 and the reference model 231 may be as described above in relation to, for example, fig. 3.

The virtual excitation generator 222 may sequentially obtain test instructions from the test case 210 according to a random scene, the virtual excitation generator 222 may analyze each test instruction, and determine a target sub-module of the module to be tested 300 indicated by the test instruction, then the virtual excitation generator 222 transmits the test instruction to a target excitation generator 221 (the target excitation generator 221 belongs to one of the excitation transmitters) in communication connection with the target sub-module, so that the target excitation generator 221 may transmit the test instruction to the driver module 223, the driver module 223 may transmit the test instruction to the target sub-module through the interface module 225, and the target sub-module may perform a test according to the test instruction and obtain a first test result; the target sub-module may transmit the first test result to scoreboard 232. Meanwhile, the monitoring module 224 may obtain the test instruction from the interface module 225 and transmit the test instruction to the reference model 231; the reference model 231 tests according to the test instruction and obtains a second test result, and the reference model 231 transmits the second test result to the score board 232; scoreboard 232 may be used to receive and compare the first test result and the second test result. Thus, the testing of the module 300 to be tested can be completed by the mutual cooperation of the above modules.

It is understood that in the test framework 200, only one virtual stimulus generator 222, one driver module 223 and one monitor module 224 may be provided, and a test instruction is sequentially transmitted in the order of one virtual stimulus generator 222, one stimulus generator 221, one driver module 223 and one module under test 300 at the same time.

Based on the above framework, the test framework 200 and the test platform 100 of the embodiment of the present application utilize the virtual excitation generator 222 to analyze the test instruction, on one hand, the whole test framework 200 only needs to be provided with one virtual excitation generator 222, one driving module 223 and one monitoring module 224, compared with the foregoing scheme, the number of the driving modules 223 and the monitoring modules 224 is greatly reduced, and the structure of the test framework 200 is simplified; on the other hand, only the virtual stimulus generator 222 is used to analyze the test command, which greatly saves the time for analyzing the test command and further improves the test efficiency compared to the case where each stimulus generator 221 needs to analyze the test command in the foregoing scheme.

Based on the test framework 200 shown in fig. 1 to fig. 5, please refer to fig. 6 for improving the test efficiency, and fig. 6 is an application diagram of a fifth test framework according to an embodiment of the present application. The input unit 220 of the test framework 200 of the embodiment of the present application may include a software use case 250, a test use case 210, an input unit 220, and an output unit 230. The input end of the input unit 220 is in communication connection with both the test case 210 and the software case 250, the output end of the input unit 220 is in communication connection with the module 300 to be tested, and the module 300 to be tested is in communication connection with the output unit 230.

The software use case 250 is a combination of a series of instructions, and the combination of instructions can describe a certain function point or a certain business process of the module to be tested 300, and can indicate a specific application scenario of the module to be tested 300, so as to instruct the module to be tested 300 to perform testing from the perspective of the application scenario. The software case 250 may include a first test instruction, and after the test case 210 instantiates the test platform 100 and the test framework 200, the input unit 220 may obtain the first test instruction from the software case 250 according to the instruction of the test case 210, and generate a first instruction packet according to the first test instruction, where the first instruction packet includes at least a first binary instruction. The input unit 220 may transmit the first binary instruction to the module under test 300; the module to be tested 300 is configured to perform a test according to the first binary instruction and obtain a first test result, and the output unit 230 is configured to receive the first test result transmitted by the module to be tested 300.

It is understood that, in actual testing, to complete a certain test, the input unit 220 often needs to continuously obtain a plurality of first test instructions from the software use case 250, where the plurality of first test instructions may form a first test instruction sequence. The input unit 220 may sequentially transmit each first test instruction to the module to be tested 300 according to the obtained sequence, and the module to be tested 300 may run each first test instruction to perform a test, thereby finally completing the test.

Based on the test framework 200 shown in fig. 6, the embodiment of the present application further provides a test method based on UVM, specifically, refer to fig. 7, and fig. 7 is a schematic flow chart illustrating a process of verifying a module to be tested according to the test framework shown in fig. 6. The UVM-based test mode may include:

in 101, an input unit acquires a first test instruction from a software case and generates a first instruction packet according to the first test instruction; the first instruction packet comprises at least a first binary instruction;

at 102, the input unit transmits a first binary instruction in a first instruction packet to a module to be tested;

in 103, the module to be tested runs the first binary instruction and obtains a first test result;

at 104, the module under test transmits the first test result to the output unit.

In the test platform 100, the test framework 200, and the test method according to the embodiment of the application, the input unit 220 obtains the first test instruction from the software case 250, and the input unit 220 can directly obtain the first test instruction with the application scenario and the first test instruction sequence.

Specifically, please refer to fig. 8, and fig. 8 is an application diagram of a sixth test framework provided in the embodiment of the present application. The input unit 220 of the test framework 200 of the embodiment of the present application may include the aforementioned excitation generator 221, the driving module 223, the interface module 225, and the monitoring module 224, and the output unit 230 may include the aforementioned reference model 231 and the scoring board 232. The software use case 250 may be directly connected to the stimulus generator 221 in a communication manner, and after the test case 210 instantiates the test platform 100 and the test framework 200, the stimulus generator 221 may obtain a first test instruction from the software use case 250 and generate a first instruction packet according to the first test instruction. The stimulus generator 221 is configured to transmit the first command packet to the driver module 223. The driving module 223 is configured to transmit the first binary instruction in the first instruction packet to the module to be tested 300 through the interface module 225, the interface module 225 may transmit the first binary instruction to the module to be tested 300 and its corresponding sub-module, the module to be tested 300 and its corresponding sub-module may run the first binary instruction and obtain a first test result, and the module to be tested 300 may transmit the first test result to the score board 232. Meanwhile, the monitoring module 224 is configured to obtain a first binary instruction from the interface module 225 and send the first binary instruction to the reference model 231. Reference model 231 may be used to run the first binary instruction and obtain a third test result, and scoreboard 232 may be used to receive the first test result and the third test result and compare the first test result and the third test result. When the first test result is the same as the third test result, it indicates that the module to be tested 300 is operating normally in the above-mentioned operation process, and when the first test result is different from the third test result, it indicates that the module to be tested 300 is operating abnormally in the above-mentioned operation process. And then, the tester can perform subsequent troubleshooting and analysis work according to the first test result and the third test result.

When the module to be tested 300 includes a plurality of sub-modules to be tested, the test framework 200 of the embodiment of the present application may include a plurality of excitation generators 221, a plurality of driving modules 223, a plurality of monitoring modules 224, a reference model 231, and a scoreboard 232, which are equal in number. Each stimulus generator 221 is communicatively coupled to both test cases 210 and software cases 250. It is understood that each stimulus generator 221 obtains the first test instruction from the software case 250, and each stimulus generator 221 is configured to identify and parse the test instruction of the test case 210 and transmit the first test instruction transmitted by the stimulus generator 221 to one driver module 223 belonging to the same transaction unit 240. Subsequently, the driving module 223, the plurality of monitoring modules 224, the reference model 231, and the score counting board 232 may operate as in the foregoing embodiment of fig. 4 to implement the test of the module to be tested 300, and detailed steps are not repeated herein.

Of course, please refer to fig. 9, fig. 9 is an application diagram of a seventh test framework provided in the embodiment of the present application. The input unit 220 may also include the aforementioned virtual stimulus generator 222, stimulus generator 221, driver module 223, interface module 225, and monitoring module 224. When the module under test 300 includes a plurality of sub-modules to be tested, the test framework 200 may include a plurality of stimulus generators 221. Wherein the virtual stimulus generator 222 is communicatively coupled to both the test cases 210 and the software cases 250. The input end of each excitation generator 221 is in communication connection with the virtual excitation generator 222, and the output end of each excitation generator 221 is in communication connection with the driving module 223; the interface module 225 is used for being in communication connection with the module to be tested 300; the input end of the driving module 223 is communicatively connected with the output end of each excitation generator 221, and the output end of the driving module 223 is communicatively connected with the input end of the interface module 225; the input end of the monitoring module 224 is communicatively connected with the input end of the interface module 225, the output end of the monitoring module 224 is communicatively connected with the output unit 230, such as the reference model 231, and both the reference model 231 and the module to be tested 300 are communicatively connected with the score counting board 232. Further, a stimulus generator 221 may be communicatively coupled to a sub-module of the module under test 300 via the driver module 223, the interface module 225, and the like.

In the test framework 200, only one virtual stimulus generator 222, one drive module 223 and one monitoring module 224 need to be arranged, and at the same time, one first test instruction is transmitted in sequence in one virtual stimulus generator 222, one stimulus generator 221, one drive module 223 and one module to be tested 300.

The virtual stimulus generator 222 may obtain a first test instruction from the software use case 250 and generate a first instruction packet according to the first test instruction; the virtual stimulus generator 222 may parse the target stimulus generator 221 corresponding to the first instruction packet and transmit the first instruction packet to the target stimulus generator 221; the target excitation generator 221 belongs to one of the plurality of excitation generators 221; the target excitation generator 221 receives the first command packet and transmits the first command packet to the driving module 223; the driving module 223 transmits the first binary instruction in the first instruction packet to the module to be tested 300 through the interface module 225; the module to be tested 300 runs the first binary instruction to obtain a first test result, and the module to be tested 300 transmits the first test result to the score counting board 232; the monitoring module 224 obtains the first binary instruction from the interface module 225 and transmits the first binary instruction to the reference model 231; the reference model 231 is used for running the first binary instruction to perform a test and obtain a third test result, and the reference model 231 transmits the third test result to the score board 232; scoreboard 232 receives and compares the first test result and the third test result.

In the test platform 100, the test framework 200, and the test method according to the embodiment of the application, the stimulus generator 221 or the virtual stimulus generator 222 obtains the first test instruction from the software case 250, and the stimulus generator 221 or the virtual stimulus generator 222 can directly obtain the test instruction with the application scenario to generate the test instruction sequence with the application scenario.

Based on the test framework 200 shown in fig. 1 to 9, please refer to fig. 10 for improving the test efficiency, and fig. 10 is a schematic application diagram of an eighth test framework according to an embodiment of the present application. The test framework 200 of the embodiment of the present application may include an instruction library 260, test cases 210, an input unit 220, and an output unit 230. The input end of the input unit 220 is connected to the instruction library 260 and the test case 210 in a communication manner; the output of the input unit 220 may be used for communication connection with the module under test 300, and the module under test 300 may be used for communication connection with the output unit 230.

The instruction library 260 may be manufactured according to a digital signal instruction set, all test instructions to be tested of the module to be tested 300 may be included in the instruction library 260, and the random test of the module to be tested 300 may be implemented by performing the test according to the instructions in the instruction library 260. The instruction library 260 may include a second test instruction, and the input unit 220 may randomly obtain the second test instruction from the instruction library 260 and generate a second instruction packet according to the second test instruction, where the second instruction packet includes at least a second binary instruction. The input unit 220 may transmit the second binary instruction to the module under test 300; the module to be tested 300 may be configured to run the second binary instruction and obtain a second test result, and the output unit 230 may be configured to receive the second test result transmitted by the module to be tested 300.

It is understood that, in actual testing, to complete a certain test, the input unit 220 needs to continuously obtain a plurality of second test instructions from the instruction library 260, where the plurality of second test instructions may form a second test instruction sequence. The input unit 220 may sequentially transmit each second test instruction to the module to be tested 300 according to the obtained sequence, and the module to be tested 300 may run each second test instruction, thereby finally completing the test.

Based on the test framework 200 shown in fig. 11, the module to be tested 300 may perform a test, and an embodiment of the present application further provides a test method based on UVM, specifically, refer to fig. 11, where fig. 11 is a schematic flow diagram illustrating a verification process performed by the module to be tested according to the test framework shown in fig. 10. The UVM-based test mode may include:

in 201, the input unit obtains a second test instruction from the instruction library, and generates a second instruction packet according to the second test instruction; the second instruction packet comprises at least a second binary instruction;

at 202, the input unit transmits the second binary instruction in the second instruction packet to the module under test 300;

in 203, the module to be tested runs the second binary instruction and obtains a second test result;

in 204, the module to be tested transmits the second test result to the output unit.

In the test platform 100, the test framework 200 and the test method according to the embodiment of the application, the input unit 220 obtains the second test instruction from the instruction library 260, and compared with randomly obtaining the test instruction directly from the test instruction, the instruction library 260 restricts the random range of the test instruction, so that the generation of invalid random test instructions can be reduced, the convergence of verification is accelerated, and the test efficiency can be improved.

Specifically, please refer to fig. 12, and fig. 12 is an application diagram of a ninth test framework according to an embodiment of the present application. The input unit 220 of the test framework 200 of the embodiment of the present application may include the aforementioned excitation generator 221, the driving module 223, the interface module 225, and the monitoring module 224, and the output unit 230 may include the aforementioned reference model 231 and the scoring board 232. The instruction library 260 may be directly connected to the stimulus generator 221 in a communication manner, and after the test case 210 instantiates the test platform 100 and the test framework 200, the stimulus generator 221 may randomly obtain a second test instruction from the instruction library 260 and generate a second instruction packet according to the second test instruction. The stimulus generator 221 is used to transmit the second packet of instructions into the driver module 223. The driving module 223 is configured to transmit the second binary instruction in the second instruction packet to the module to be tested 300 through the interface module 225, the interface module 225 may transmit the second binary instruction to the module to be tested 300 and its corresponding sub-module, the module to be tested 300 and its corresponding sub-module may run the second binary instruction and obtain the first test result, and the module to be tested 300 may transmit the second test result to the score board 232. Meanwhile, the monitoring module 224 is configured to obtain a second binary instruction from the interface module 225 and send the second binary instruction to the reference model 231. Reference model 231 may be configured to run the second binary instruction and obtain a fourth test result, and scoreboard 232 may be configured to receive the second test result and the fourth test result and compare the second test result and the fourth test result. When the second test result is the same as the fourth test result, it indicates that the module to be tested 300 is operating normally in the above-mentioned operation process, and when the second test result is different from the fourth test result, it indicates that the module to be tested 300 is operating abnormally in the above-mentioned operation process. And then, the tester can perform subsequent troubleshooting and analysis work according to the second test result and the fourth test result.

When the module to be tested 300 includes a plurality of sub-modules to be tested, the test framework 200 of the embodiment of the present application may include a plurality of excitation generators 221, a plurality of driving modules 223, a plurality of monitoring modules 224, a reference model 231, and a scoreboard 232, which are equal in number. Each stimulus generator 221 is communicatively coupled to both the test case 210 and the library of commands 260. It is understood that each stimulus generator 221 obtains the second test instruction from the instruction library 260, and each stimulus generator 221 is configured to identify and parse the test instruction of the test case 210 and transmit the test instruction transmitted by the stimulus generator 221 to one driver module 223 belonging to the same transaction unit 240. Subsequently, the driving module 223, the plurality of monitoring modules 224, the reference model 231, and the score counting board 232 may operate as in the foregoing embodiment of fig. 4 to implement the test of the module to be tested 300, and detailed steps are not repeated herein.

Of course, please refer to fig. 13, fig. 13 is an application diagram of a tenth test framework provided in the embodiment of the present application. The input unit 220 may also include the aforementioned virtual stimulus generator 222, stimulus generator 221, driver module 223, interface module 225, and monitoring module 224. When the module under test 300 includes a plurality of sub-modules to be tested, the test framework 200 may include a plurality of stimulus generators 221. The virtual stimulus generator 222 is communicatively coupled to both the test case 210 and the command library 260. The input end of each excitation generator 221 is in communication connection with the virtual excitation generator 222, and the output end of each excitation generator 221 is in communication connection with the driving module 223; the interface module 225 is used for being in communication connection with the module to be tested 300; the input end of the driving module 223 is communicatively connected with the output end of each excitation generator 221, and the output end of the driving module 223 is communicatively connected with the input end of the interface module 225; the input end of the monitoring module 224 is communicatively connected with the input end of the interface module 225, the output end of the monitoring module 224 is communicatively connected with the output unit 230, such as the reference model 231, and both the reference model 231 and the module to be tested 300 are communicatively connected with the score counting board 232. Further, a stimulus generator 221 may be communicatively coupled to a sub-module of the module under test 300 via the driver module 223, the interface module 225, and the like.

In the test framework 200, only one virtual stimulus generator 222, one drive module 223 and one monitor module 224 are provided, and at the same time, one second test instruction is sequentially transmitted in sequence in one virtual stimulus generator 222, one stimulus generator 221, one drive module 223 and one module to be tested 300.

The virtual stimulus generator 222 may obtain a second test instruction from the instruction library 260 and generate a second instruction packet according to the second test instruction; the virtual stimulus generator 222 parses the target stimulus generator 221 corresponding to the second instruction packet and transmits the second instruction packet to the target stimulus generator 221. the target stimulus generator 221 belongs to one of the plurality of stimulus generators 221; the target excitation generator 221 receives the second instruction packet and transmits the second instruction packet to the driving module 223; the driving module 223 transmits the second binary instruction in the second instruction packet to the module to be tested 300 through the interface module 225; the module to be tested 300 runs the second binary instruction to obtain a second test result, and the module to be tested 300 transmits the second test result to the score counting board 232; the monitoring module 224 obtains the second binary instruction from the interface module 225 and transmits the second binary instruction to the reference model 231; the reference model 231 runs the second binary instruction to perform a test and obtain a fourth test result, and the reference model 231 transmits the fourth test result to the score board 232; scoreboard 232 receives and compares the second test result and the fourth test result.

In the test platform 100, the test framework 200 and the test method according to the embodiment of the application, the excitation generator 221 or the virtual excitation generator 222 acquires the second test instruction from the instruction library 260, and compared with randomly acquiring the test instruction directly from the test instruction, the instruction library 260 restricts the random range of the test instruction, so that the generation of invalid random test instructions can be reduced, the convergence of verification is accelerated, and the test efficiency can be improved.

Based on the test framework 200 shown in fig. 1 to 13, please refer to fig. 14 for further improving the test accuracy, and fig. 14 is a schematic application diagram of an eleventh test framework according to an embodiment of the present application. The test framework 200 of the embodiment of the application may simultaneously include a software case 250, an instruction library 260, a test case 210, an input unit 220, and an output unit 230, wherein an input end of the input unit 220 is simultaneously connected in communication with the software case 250 and the instruction library 260, an output end of the input unit 220 may be connected in communication with a module to be tested 300, and the module to be tested 300 may be used for being connected in communication with the output unit 230.

After the test case 210 instantiates the test platform 100 and the test framework 200, the input unit 220 may obtain the first test instruction from the software case 250 according to the instruction of the test case 210, and generate a first instruction packet according to the first test instruction, where the first instruction packet includes at least a first binary instruction. The input unit 220 may transmit the first binary instruction to the module under test 300; the input unit 220 may transmit the first binary instruction to the module under test 300; the module to be tested 300 is configured to perform a test according to the first binary instruction and obtain a first test result, and the output unit 230 is configured to receive the first test result transmitted by the module to be tested 300.

The input unit 220 may also randomly obtain a second test instruction from the instruction library 260 according to the instruction of the test case 210, and generate a second instruction packet according to the second test instruction, where the second instruction packet includes at least a second binary instruction. The input unit 220 may transmit the second binary instruction to the module under test 300; the module to be tested 300 may be configured to perform a test according to the second binary instruction and obtain a second test result, and the output unit 230 may be configured to receive the second test result transmitted by the module to be tested 300.

It can be understood that, the input unit 220 obtains the first test instruction from the software use case 250, and can test the module to be tested 300 from the perspective of the application scenario; the input unit 220 obtains the second testing instruction from the instruction library 260, and can test the module 300 to be tested from a random angle. The steps of the input unit 220 obtaining the first test instruction from the software use case 250 and completing the subsequent test according to the first test instruction, and the steps of the input unit 220 obtaining the second test instruction from the instruction library 260 and completing the subsequent test according to the second test instruction are respectively performed. That is, under the instruction of the test case 210, the input unit 220 may first test the module to be tested 300 from the perspective of an application scenario based on the first test instruction of the software case 250; the input unit 220 may then test the module under test 300 from a random angle based on the second test instruction of the instruction library 260. Of course, under the instruction of the test case 210, the input unit 220 may also test the module to be tested 300 from a random angle based on the second test instruction of the instruction library 260, and then the input unit 220 may test the module to be tested 300 from an application scenario angle based on the first test instruction of the software case 250.

Based on the test framework 200 shown in fig. 14, the embodiment of the present application further provides a test method based on UVM, specifically, refer to fig. 15, and fig. 15 is a schematic flow chart illustrating a process of verifying a module to be tested according to the test framework shown in fig. 14. The UVM-based test mode may include:

in 301, the input unit acquires a first test instruction from the software case and generates a first instruction packet according to the first test instruction; or the input unit acquires a second test instruction from the instruction library and generates a second instruction packet according to the second test instruction; the first instruction packet at least comprises a first binary instruction, and the second instruction packet at least comprises a second binary instruction;

in 302, the input unit transmits the first binary instruction or the second binary instruction to the module to be tested;

in 303, the module to be tested runs the first binary instruction and obtains a first test result, or runs the second binary instruction and obtains a second test result;

in 304, the module under test transmits the first test result or the second test result to the output unit.

In the test platform 100, the test framework 200 and the test method of the embodiment of the application, the input unit 220 may obtain the first test instruction from the software case 250, or obtain the second test instruction from the instruction library 260, on one hand, when the input unit 220 directly obtains the first test instruction with the application scenario from the software case 250, due to the constraint of the application scenario, the random space of the test instruction sequence may be reduced, the length of the test instruction sequence obtained by the virtual excitation generator 222 or the excitation generator 221 may be reduced, and the test efficiency may be improved; the input unit 220 obtains the second test instruction from the instruction library 260, and the instruction library 260 restricts the random range of the instruction, so that the generation of invalid random test instructions can be reduced, the convergence of verification is accelerated, and the test efficiency can be improved; on the other hand, when the test platform 100 and the test framework 200 include the instruction library 260 and the software use case 250 at the same time, when the first test case 210 is obtained from the software use case 250, the module to be tested 300 can be tested from the perspective of an application scenario; when the second test instruction is obtained from the instruction library 260, the module to be tested 300 can be tested from a random angle, so that the test platform 100, the test framework 200 and the test method of the embodiment of the application can test the module to be tested 300 more comprehensively and accurately, and the test accuracy can be improved.

Specifically, please refer to fig. 16, and fig. 16 is an application diagram of a twelfth testing framework according to an embodiment of the present application. The input unit 220 of the test framework 200 of the embodiment of the present application may include the aforementioned excitation generator 221, the driving module 223, the monitoring module 224, and the interface module 225, and the output unit 230 may include the aforementioned reference model 231 and the scoring board 232. The stimulus generator 221 can be communicatively coupled to the software use case 250, and the stimulus generator 221 can also be communicatively coupled to the instruction library 260. After the test case 210 instantiates the test platform 100 and the test framework 200, according to the instruction of the test case 210, the stimulus generator 221 may obtain a first test instruction from the software case 250 and generate a first instruction packet according to the first test instruction, or the stimulus generator 221 may obtain a second test instruction from the instruction library 260 and generate a second instruction packet according to the second test instruction. After the excitation generator 221 obtains the first test command or the second test command, the first test command or the second test command may be transmitted to the driving module 223. The driving module 223 may transmit the first binary instruction in the first instruction packet or the second binary instruction in the second instruction packet to the module to be tested 300 through the interface module 225, the interface module 225 may transmit the first binary instruction or the second binary instruction to the module to be tested 300 and the corresponding sub-module thereof, the module to be tested 300 and the corresponding sub-module thereof may run the first binary instruction and obtain a first test result, or run the second binary instruction and obtain a second test result, and the module to be tested 300 may transmit the first test result or the second test result to the score board 232. Meanwhile, the monitoring module 224 is configured to obtain the first binary instruction or the second binary instruction from the interface module 225, and send the first binary instruction or the second binary instruction to the reference model 231. Reference model 231 may be used to run the first binary instruction and obtain a third test result, or run the second binary instruction and obtain a fourth test result, and scoreboard 232 may be used to receive and compare the first test result and the third test result, or receive and compare the second test result and the fourth test result.

When the first test result is the same as the third test result and the second test result is the same as the fourth test result, it indicates that the module 300 to be tested is operating normally in the above-mentioned operation process; when the first test result is different from the third test result, and the second test result is different from the fourth test result, it indicates that the module to be tested 300 has an abnormal operation problem in the above operation. And then, the tester can perform subsequent troubleshooting and analysis work according to the first test result, the third test result, the second test result and the fourth test result.

When the module to be tested 300 includes a plurality of sub-modules to be tested, the test framework 200 of the embodiment of the present application may include a plurality of excitation generators 221, a plurality of driving modules 223, a plurality of monitoring modules 224, a reference model 231, and a scoreboard 232, which are equal in number. Each stimulus generator 221 is communicatively coupled to both test case 210, instruction library 260, and software case 250. It is understood that each stimulus generator 221 obtains a first test instruction from the software use case 250 or a second test instruction from the instruction library 260, and each stimulus generator 221 is configured to identify and parse the first test instruction in the software use case 250 or the second test instruction in the instruction library 260, and transmit the first test instruction or the second test instruction transmitted by the stimulus generator 221 to one driver module 223 belonging to the same transaction unit 240. Subsequently, the driving module 223, the plurality of monitoring modules 224, the reference model 231, and the score counting board 232 may operate as in the foregoing embodiments to implement the test of the module to be tested 300, and detailed steps are not repeated herein.

Of course, please refer to fig. 17, fig. 17 is an application diagram of a thirteenth test framework provided in the embodiment of the present application. The input unit 220 may also include the aforementioned virtual stimulus generator 222, stimulus generator 221, driving module 223, monitoring module 224, and the output unit 230 may include a scoreboard 232 and a reference model 231. Virtual stimulus generator 222 is communicatively coupled to both software use case 250, virtual stimulus generator 222 is communicatively coupled to instruction library 260, and virtual stimulus generator 222 is communicatively coupled to test use case 210. After the test case 210 instantiates the test platform 100 and the test framework 200, the virtual stimulus generator 222 may obtain a first test instruction from the software case 250 and generate a first instruction packet according to the first test instruction, or the virtual stimulus generator 222 may obtain a second test instruction from the instruction library 260 and generate a second instruction packet according to the second test instruction. The virtual stimulus generator 222 may transmit the first instruction packet or the second instruction packet to the stimulus generator 221 and the driver module 223. The driving module 223 is configured to transmit the first binary instruction in the first instruction packet or the second binary instruction in the second instruction packet to the module to be tested 300 through the interface module 225. The interface module 225 may transmit the first binary instruction or the second binary instruction to the module to be tested 300 and the corresponding sub-module thereof, the module to be tested 300 and the corresponding sub-module thereof may run the first binary instruction and obtain a first test result, or run the second binary instruction and obtain a second test result, and the module to be tested 300 may transmit the first test result or the second test result to the score board 232. Meanwhile, the monitoring module 224 is configured to obtain the first binary instruction or the second binary instruction from the interface module 225, and send the first binary instruction or the second binary instruction to the reference model 231. Reference model 231 may be used to run the first binary instruction and obtain a third test result, or run the second binary instruction and obtain a fourth test result, and scoreboard 232 may be used to receive and compare the first test result and the third test result, or to receive and compare the second test result and the fourth test result.

As shown in fig. 17, when the module to be tested 300 includes a plurality of sub-modules to be tested, the test framework 200 of the embodiment of the present application may include a virtual excitation generator 222, a plurality of excitation generators 221, a driving module 223, a monitoring module 224, a reference model 231, and a score plate 232. The virtual stimulus generator 222 is communicatively coupled to both the test case 210, the command library 260, and the software case 250. The input end of each excitation generator 221 is in communication connection with the virtual excitation generator 222, and the output end of each excitation generator 221 is in communication connection with the driving module 223; the interface module 225 is used for being in communication connection with the module to be tested 300; the input end of the driving module 223 is communicatively connected with the output end of each excitation generator 221, and the output end of the driving module 223 is communicatively connected with the input end of the interface module 225; the input end of the monitoring module 224 is communicatively connected with the input end of the interface module 225, the output end of the monitoring module 224 is communicatively connected with the output unit 230, such as the reference model 231, and both the reference model 231 and the module to be tested 300 are communicatively connected with the score counting board 232. Further, a stimulus generator 221 may be communicatively coupled to a sub-module of the module under test 300 via the driver module 223, the interface module 225, and the like.

After the test case 210 instantiates the test platform 100 and the test framework 200, the virtual stimulus generator 222 may obtain a first test instruction from the software case 250 and generate a first instruction packet according to the first test instruction, or the virtual stimulus generator 222 may obtain a second test instruction from the instruction library 260 and generate a second instruction packet according to the second test instruction. The virtual stimulus generator 222 may determine the target sub-module of the module under test 300 indicated by the first or second instruction packet. The virtual stimulus generator 222 then transmits the first or second command packet to the target stimulus generator 221, which is communicatively coupled to the target sub-module, so that the target stimulus generator 221 can transmit the first or second command packet to the driver module 223. The driving module 223 may transmit the first binary instruction in the first instruction packet or the second test instruction in the second instruction packet to the target sub-module through the interface module 225, and then the target sub-module may run the first binary instruction and obtain a first test result, or the target sub-module runs the second test instruction and obtain a second test result. Meanwhile, the monitoring module 224 may still obtain the first binary instruction or the second test instruction from the interface module 225, and transmit the first binary instruction or the second test instruction to the output unit 230, such as the reference model 231. The reference model 231 may run the first binary instruction and obtain a third test result, or the reference model 231 runs the second binary instruction and obtain a fourth test result, and the reference model 231 transmits the third test result or the fourth test result to the score board 232; scoreboard 232 receives and compares the first test result and the third test result, or scoreboard 232 receives and compares the second test result and the fourth test result.

In the test framework 200, only one virtual stimulus generator 222, one driver module 223 and one monitor module 224 are provided, and at the same time, one first instruction packet or one second instruction packet is transmitted in sequence in one virtual stimulus generator 222, one stimulus generator 221, one driver module 223 and one module to be tested 300.

It is to be appreciated that the software use case 250 may include assembly instructions and may also include assembly instructions and binary instructions. The first test instruction may also be an assembler instruction in the software use case 250 or a binary instruction. The first instruction packet may include a first assembly instruction and a first binary instruction, and the first assembly instruction may be decoded from the first binary instruction. The instruction library 260 may include assembler instructions, binary instructions, or both assembler instructions and binary instructions. The second test instruction may also be a assembler instruction or a binary instruction in the instruction library 260. The second instruction packet may include a second assembler instruction and a second binary instruction, and the second assembler instruction may be decoded from the second binary instruction.

When the first instruction packet or the second instruction packet includes the binary instruction and the assembly instruction, and the first instruction packet or the second instruction packet is transmitted between the excitation generator 221 and the drive module 223 or transmitted between the virtual excitation generator 222, the excitation generator 221 and the drive module 223, a tester can read the meaning of the test instruction according to the assembly instruction in the first instruction packet or the second instruction packet, so that the readability of the instruction is enhanced, and the test instruction is convenient to maintain and debug. Moreover, the driving module 223 transmits the binary instruction in the first instruction packet or the second instruction packet to the module to be tested 300, and the module to be tested 300 can also directly test according to the binary instruction.

It can be understood that, when the reference model 231 is used for test comparison in the embodiment of the present application, the reference model 231 may be calibrated first, that is, the software case 250 or the instruction library 260 may be directly connected to the reference model 231 in a communication manner, the reference model 231 may obtain a test instruction with a known expected result from the software case 250 or the instruction library 260, the reference model 231 performs a test according to the test instruction and obtains a test result, and the calibration of the reference model 231 may be completed by comparing the test result with the expected result.

It can be understood that, the monitoring module 224 according to this embodiment of the present application may decode the first binary instruction or the second binary instruction obtained from the interface module 225 to obtain a first assembly instruction corresponding to the first binary instruction or a second assembly instruction corresponding to the second binary instruction, and the monitoring module 224 is further configured to pack the first binary instruction and the second assembly instruction or pack the second binary instruction and the second assembly instruction, and transmit the packed instruction packet to the output unit 230, for example, the reference model 231, so as to enhance readability of the instruction and facilitate maintenance and debugging of the instruction.

It is understood that the interface module 225 in the embodiment of the present application may be a virtual interface module 225. It is understood that the input unit 220 of the embodiment of the present application may not include the monitoring module 224, and the output unit 230 may not include the reference model 231. That is, in the above-described test framework 200, the score plate 232 may receive only the first test result of the module to be tested 300, without receiving the second test results of the monitoring module 224 and the reference model 231. The score calculating board 232 may also determine the accuracy of the first test result of the module to be tested 300 by analyzing the first test result.

In the test platform 100, the test framework 200 and the test method of the embodiment of the application, the stimulus generator 221 or the virtual stimulus generator 222 acquires the first test instruction from the software case 250 or acquires the second test instruction from the instruction library 260, on one hand, when the stimulus generator 221 or the virtual stimulus generator 222 can directly acquire the first test instruction with the application scene from the software case 250 to generate the test instruction sequence with the application scene, the random space of the test instruction sequence can be reduced, the length of the test instruction sequence acquired by the virtual stimulus generator 222 or the stimulus generator 221 is reduced, and the test efficiency can be improved; the excitation generator 221 or the virtual excitation generator 222 acquires the second test instruction from the instruction library 260, and the instruction library 260 restricts the random range of the instruction, so that the generation of invalid random test instructions can be reduced, the convergence of verification is accelerated, and the test efficiency can be improved; on the other hand, when the test platform 100 and the test framework 200 include the instruction library 260 and the software use case 250 at the same time, when the first test case 210 is obtained from the software use case 250, the module to be tested 300 can be tested from the perspective of an application scenario; when the second test instruction is obtained from the instruction library 260, the module to be tested 300 can be tested from a random angle, so that the test platform 100 and the test framework 200 of the embodiment of the application can test the module to be tested 300 more comprehensively and accurately, and the test accuracy can be improved.

The embodiment of the present application further provides a storage medium, where a computer program is stored in the storage medium, and when the computer program runs on a computer, the computer executes the UVM-based testing method according to any one of the above embodiments.

It should be noted that, all or part of the steps in the methods of the above embodiments may be implemented by hardware related to instructions of a computer program, which may be stored in a computer-readable storage medium, which may include, but is not limited to: read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and the like.

It should be appreciated that reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Furthermore, the terms "first", "second", and "third", etc. in this application are used to distinguish different objects, and are not used to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to only those steps or modules listed, but rather, some embodiments may include other steps or modules not listed or inherent to such process, method, article, or apparatus.

The UVM-based test framework, the test platform, and the test method provided by the embodiment of the present application are described in detail above. The principles and implementations of the present application are described herein using specific examples, which are presented only to aid in understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A UVM-based test architecture, comprising:

the software use case comprises a first test instruction;

2. The UVM-based test framework of claim 1, further comprising:

the input unit is further used for being in communication connection with the instruction library, acquiring the second test instruction from the instruction library, generating a second instruction packet according to the second test instruction, wherein the second instruction packet at least comprises a second binary instruction, and transmitting the second binary instruction to a module to be tested;

the output unit is further configured to receive a second test result obtained by the module to be tested running the second binary instruction.

3. The UVM-based test framework of claim 2, wherein the input unit includes:

the virtual excitation generator is respectively in communication connection with the software use case and the instruction library, and is used for acquiring the first test instruction from the software use case and generating the first instruction packet according to the first test instruction, or is used for acquiring the second test instruction from the instruction library and generating the second instruction packet according to the second test instruction;

a plurality of stimulus generators, each of said stimulus generators being communicatively coupled to said virtual stimulus generator, one of said stimulus generators being configured to receive said first or said second command packet transmitted by said virtual stimulus generator;

the interface module is used for being in communication connection with the module to be tested;

the driving module is in communication connection with each excitation generator and the interface module, and is used for receiving the first instruction packet or the second instruction packet transmitted by the excitation generator and transmitting the first binary instruction or the second binary instruction to the module to be tested through the interface module;

the monitoring module is in communication connection with the interface module and the output unit respectively, and is used for acquiring the first binary instruction or the second binary instruction from the interface module and transmitting the first binary instruction or the second binary instruction to the output unit.

4. The UVM-based test framework of claim 3, wherein the monitor module is further configured to decode the first binary instruction into a corresponding first assembler instruction and to packetize the first binary instruction and the first assembler instruction for transmission to the output unit; or the monitoring module is further used for decoding the second binary instruction into a corresponding second assembly instruction and for packing and transmitting the second binary instruction and the second assembly instruction to the output unit.

5. The UVM based test framework of claim 3 or 4, wherein said output unit comprises:

the reference model is in communication connection with the monitoring module and is used for operating the first binary instruction and obtaining a third test result, or the reference model is used for operating the second binary instruction and obtaining a fourth test result;

the scoring board is in communication connection with the reference model and is also in communication connection with the module to be tested, and the scoring board is used for receiving and comparing the first test result and the third test result or receiving and comparing the second test result and the fourth test result so as to judge the running state of the module to be tested.

6. The UVM based test framework of claim 5, wherein said reference model is further for retrieving initial test instructions from said software use case and for running said initial test instructions for an initialization test.

7. The UVM-based test framework of claim 1, wherein the input unit includes:

the virtual excitation generator is in communication connection with the software use case, and is used for acquiring the first test instruction from the software use case and generating the first instruction packet according to the first test instruction;

a plurality of stimulus generators, each of said stimulus generators being communicatively coupled to said virtual stimulus generator, one of said stimulus generators being configured to receive said first command packet transmitted by said virtual stimulus generator;

the driving module is in communication connection with each excitation generator and the interface module, and is used for receiving the first instruction packet transmitted by the excitation generator and transmitting the first binary instruction to the module to be tested through the interface module;

and the monitoring module is in communication connection with the interface module and the output unit respectively, and is used for acquiring the first binary instruction from the interface module and transmitting the first binary instruction to the output unit.

8. A UVM-based test architecture, comprising:

9. The UVM-based test framework of claim 8, wherein the input unit includes:

the virtual excitation generator is in communication connection with the instruction library, and is used for acquiring the second test instruction from the instruction library and generating the second instruction packet according to the second test instruction;

a plurality of stimulus generators, each of said stimulus generators being communicatively coupled to said virtual stimulus generator, one of said stimulus generators being configured to receive said second instruction packet transmitted by said virtual stimulus generator;

the driving module is in communication connection with each excitation generator, is also in communication connection with the interface module, and is used for receiving the second instruction packet transmitted by the excitation generator and transmitting the second binary instruction to the module to be tested through the interface module;

and the monitoring module is respectively in communication connection with the interface module and the output unit, and is used for acquiring the second binary instruction from the interface module and transmitting the second binary instruction to the output unit.

10. A UVM-based test platform, comprising:

a module to be tested;

a test framework comprising a test framework as claimed in any one of claims 1 to 9, the module to be tested being for testing by the test framework.

11. The UVM-based testing method is characterized by being applied to a testing platform and a testing framework, wherein the testing platform comprises a module to be tested and the testing framework, the testing framework comprises a software case, an input unit and an output unit, the input unit is in communication connection with the software case, the output unit is in communication connection with the module to be tested, and the software case comprises a first testing instruction;

the UVM-based testing method comprises the following steps:

and the module to be tested transmits the first test result to the output unit.

12. The UVM-based testing method of claim 11, wherein the testing framework further includes an instruction library, the instruction library communicatively coupled to the input unit, the instruction library including a second testing instruction;

the UVM-based testing method comprises the following steps:

the input unit acquires the first test instruction from the software case and generates a first instruction packet according to the first test instruction, or acquires the second test instruction from the instruction library and generates a second instruction packet according to the second test instruction; the first instruction packet comprises at least a first binary instruction, and the second instruction packet comprises at least a second binary instruction;

the input unit transmits the first binary instruction or the second binary instruction to the module to be tested;

the module to be tested runs the first binary instruction and obtains a first test result, or runs the second binary instruction and obtains a second test result;

and the module to be tested transmits the first test result or the second test result to the output unit.

13. The UVM-based testing method is characterized by being applied to a testing platform and a testing framework, wherein the testing platform comprises a module to be tested and the testing framework, the testing framework comprises an instruction library, an input unit and an output unit, the input unit is in communication connection with the instruction library, the output unit is in communication connection with the module to be tested, and the instruction library comprises a second testing instruction;

the UVM-based testing method comprises the following steps: