CN105205249A - SOC (System on Chip) debugging validation system and software/hardware collaboration method thereof - Google Patents
SOC (System on Chip) debugging validation system and software/hardware collaboration method thereof Download PDFInfo
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Abstract
The invention discloses an SOC (System on Chip) debugging validation system. The SOC debugging validation system comprises an SOC and a validation platform, wherein the SOC comprises a processor, a memory and a software test case stored in the memory; the validation platform comprises a hardware test case. On the basis of the prior art, a debugging module is added into the SOC to be validated, a software access address of the debugging module is allocated to an address section which is not used in the system, interactive communication between the software test case and the hardware test case is achieved by reading-writing a register array in the debugging module through the software test case and writing-reading the register array in the debugging module through the hardware test case, and the validation on the SOC is completed. The invention also provides a software/hardware collaboration method of the SOC debugging validation system. According to the system and the method, mutual communication between the software test case and the hardware test case can be achieved in a debugging validation process of the SOC, the simulation frequency is reduced, and the efficiency is improved.
Description
Technical field
The present invention relates to integrated circuit verification field tests, particularly in a kind of SOC system verification, software and hardware encourages mutual method and realizes the SOC debugging verification system of the method.
Background technology
Along with the develop rapidly of IC industry, increasing chip design becomes SOC(SystemOnChip) chip, the scale along with SOC is increasing, and the checking of SOC is also more and more difficult.SOC debugging verification system is generally use electric design automation (ElectronicDesignAutomation, EDA) instrument to carry out simulating, verifying process to SOC, to guarantee the correctness that SOC designs.The excitation (test case) of SOC system verification is generally divided into two parts: software excitation (software test case) and hardware excitation (hardware testing use-case).Software excitation compiles generation executable file through compiler after being encoded by software languages such as C, C++, leave in the storer of SOC, also performed to complete the function designed by SOC by CPU (central processing unit) (CentralProcessorUnit, CPU) reading command from storer of SOC again.Hardware excitation is by the hardware description languages such as Verilog, VHDL, SystemVerilog or hardware verification speech encoding, be positioned at system verification platform, make SOC reach the condition of work of expectation for the applied environment or direct amendment SOC design internal hardware signal building SOC.Software excitation and hardware excitation collaborative work achieve system verification SOC being completed under certain applied environment to certain feature operation.
But existing software excitation and hardware are activated in collaborative processes, there is following problem:
1, artificial debugging number of times is increased: because the state of the other side is not all known in software excitation and hardware excitation, need through repeatedly debugging the scene could determining both to meet.
2, the simulation run time is increased: in order to ensure that software excitation or hardware excitation are made adequate preparation, the time delay that can be added beyond in excitation needed for reality is waited for.
3, single emulation covering function point is few: encouraged by software and hardware encourages that all not know whether the other side runs complete, and once emulate the partial function that can only cover under certain applied environment, cover greater functionality needs simulating, verifying again.
Summary of the invention
The present invention, in order to solve the problem of above-mentioned prior art, proposes a kind of SOC debugging verification system, and this system is mainly applied in and utilizes eda tool to carry out in the process of simulating, verifying SOC.It comprises SOC and verification platform, described SOC comprises processor, storer, the software test case left in storer, described verification platform comprises hardware testing use-case, also be provided with a debugging module in described SOC, described software test case and hardware testing use-case carry out by debugging module the checking that interactive correspondence come SOC in operational process.
The invention also proposes a kind of software-hardware synergism method of above-mentioned SOC debugging verification system, comprise the steps:
Step 1: software test case drives the processor of SOC to write A by the system bus of SOC in the register in debugging module, and after this step runs succeeded, the value of the register in debugging module equals A;
Step 2: the value of hardware testing use-case control register, judges whether the value of described register equals A, if be not equal to A, then continues monitoring, if equal A, then continues step 3;
Step 3: hardware testing use-case determination software test case is current ready, hardware testing use-case starts the hardware adaptations environment or the condition of work that build next step operation of SOC;
Step 4: after the hardware adaptations environment that hardware testing use-case is current or condition of work have built, the value of register is revised as B;
Step 5: software test case drives processor by the value of the register in system bus monitoring debugging module, judges whether register value equals B, if be not equal to B, then continues monitoring, if equal B, then continue step 6;
Step 6: software test case determination hardware testing use-case has got out current hardware adaptations environment or condition of work, software test case starts next step operation;
Step 7: circulation step 1 to 6, until software test case and hardware testing use-case have worked in coordination with all debugging checking work mutually.
Value A in above-mentioned steps 1-6, B are arbitrary value, and current A, B value may be the same or different with A, B value in cyclic process before, and the register that current A, B value is deposited may be the same or different with the register existing for A, B value in cyclic process before.
The application adds one in SOC can encourage the debugging module of simultaneously accessing for software excitation and hardware, software is encouraged and hardware encourage can communication mutually in collaborative processes, thus decrease the number of times of SOC system verification artificial debugging, shorten the simulation run time, add the function point that single emulation covers, contribute to improving SOC system verification efficiency, and do not increase the scale of SOC design, do not affect the design function of SOC at all.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention;
Fig. 2 is the structural representation of debugging module of the present invention;
Fig. 3 is the process flow diagram of software-hardware synergism of the present invention.
Embodiment
Below in conjunction with drawings and Examples, describe the course of work of the present invention in detail.
As shown in Figure 1, the SOC debugging verification system that one embodiment of the invention proposes, comprise SOC 101 and verification platform 106, SOC comprises processor 103, storer 104, software test case is deposited in storer 104, also make software encourage 105, software excitation 105 is encoded by software languages such as C, C++, through the executable file that compiler compiling generates.Processor 103 can from storer 104 reading command and perform drive SOC 101 to realize designed function.
Verification platform 106 by hardware encourage 107(be also hardware testing use-case) and monitor 108 form, verification platform 106 is built by hardware description language Verilog or VHDL or hardware verification language SystemVerilog, in verification platform 106, all signals of SOC 101 inside or register pair hardware excitation 107 and monitor 108 are all complete visible concrete signal or unit, therefore signal or the register value of SOC 101 inside can be directly monitored or be revised in hardware excitation 107, monitor 108 directly can monitor signal or the register value of SOC 101 inside.Hardware excitation 107 builds applied environment or the condition of work of SOC 101 by the signal of amendment SOC 101 inside or the value of register.Whether monitor 108 meets expection by the signal or register value checking SOC 101 inside judges whether SOC 101 correctly works.
SOC 101 is objects to be verified, in order to realize software and hardware test case proposed by the invention, collaborative, mutual communication is mutual mutually, the Verify in System stage, debugging module 102 is added in SOC 101, and the address area will do not used in the softward interview address assignment of debugging module 102 to SOC 101 system.Debugging module 102, only for the system verification stage, does not have in actual chips product.Software test case and hardware testing use-case carry out by debugging module the checking that interactive correspondence come SOC in operational process.
As shown in Figure 2, debugging module 201, as the submodule of in SOC 101, is integrated on the system bus of SOC 101.Debugging module 201 is made up of bus interface 202, bus access resolution unit 203 and register array 204.Bus interface 202 adopts the system bus interface of SOC 101, and bus access resolution unit 203 converts the accessing time sequence of bus interface 202 accessing time sequence of register array 204 to.Register in register array in debugging module is at least one, can arrange any number of register as required, generally all needs about 10 registers to complete the debugging checking of SOC.
Software excitation 105 drives processor 103 by the register array in the system bus read-write debugging module 102 of SOC 101, and the hardware excitation 107 in verification platform 106 can read and write the register array in debugging module 102, in view of the register in debugging module 102 can by software encourage 105 and hardware excitation 107 jointly to access, the register in debugging module 102 can be used to realize the interactive communication of software excitation 105 and hardware excitation 107.
As shown in Figure 3, the invention allows for the Synergistic method of the software and hardware of SOC debugging verification system, the debugging that its interactive cooperation mainly between hardware testing use-case and software test case completes SOC is verified, comprises the steps:
Step 1: software test case drives the processor of SOC to write A by the system bus of SOC in the register 0 in debugging module, and after this step runs succeeded, the value of the register 0 in debugging module equals A;
Step 2: the value of hardware testing use-case control register 0, judges whether the value of register 0 equals A, if be not equal to A, then continues monitoring, if equal A, then continues step 3;
Step 3: hardware testing use-case determination software test case is current ready, hardware testing use-case starts the hardware adaptations environment or the condition of work that build next step operation of SOC;
Step 4: after the hardware adaptations environment that hardware testing use-case is current or condition of work have built, the value of register 0 is revised as B;
Step 5: software test case drives processor by the value of the register 0 in system bus monitoring debugging module, judges that register 0 is worth and whether equals B, if be not equal to B, then continue monitoring, if equal B, then continue step 6;
Step 6: software test case determination hardware testing use-case has got out current hardware adaptations environment or condition of work, software test case starts next step operation;
Step 7: judge whether SOC debugs and verify, if so, then terminate; Then circulation step 1 to 6 if not, until software test case and hardware testing use-case have worked in coordination with all debugging checking work mutually.
Value A in above-mentioned steps 1-6, B are arbitrary value, and current A, B value may be the same or different with A, B value in cyclic process before, and the register that current A, B value is deposited may be the same or different with the register existing for A, B value in cyclic process before.Above-mentioned steps 1 to step 6 is that software excitation 105 encourages 107 to carry out a kind of flow process of information interaction based on the concrete some registers in debugging module 102 with hardware, if software excitation 105 and hardware have more kinds of information to need alternately between encouraging 107, other register in debugging module 102 can be used to realize, use other registers carry out mutual flow process with use register 0 time identical, checking personnel can according to software encourage 105 and hardware encourage the number needing mutual information between 107, circulation step 1 to the step 6 in implementation step 7.
Should be understood that, the above-mentioned description for specific embodiment is comparatively detailed, and therefore can not think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (7)
1. a SOC debugging verification system, comprise SOC and verification platform, described SOC comprises processor, storer, the software test case left in storer, described verification platform comprises hardware testing use-case, it is characterized in that, also be provided with a debugging module in described SOC, described software test case and hardware testing use-case carry out by debugging module the checking that interactive correspondence come SOC in operational process.
2. SOC debugging verification system as claimed in claim 1, it is characterized in that, described debugging module comprises the bus interface be connected with the system bus of SOC, the bus access resolution unit be connected with bus interface, register array for software test case and the read and write access of hardware testing use-case.
3. SOC debugging verification system as claimed in claim 2, it is characterized in that, the register number in described register array is at least one.
4. SOC debugging verification system as claimed in claim 2, it is characterized in that, read and write access is carried out to debugging module in the softward interview address after described software test case is mapped by debugging module.
5. SOC debugging verification system as claimed in claim 4, is characterized in that, the softward interview address after described debugging module maps is untapped address in the system of SOC.
6. SOC debugging verification system as claimed in claim 1, is characterized in that, described verification platform also comprises signal for checking SOC inside or whether register value mates preset value to judge the monitor whether SOC correctly works.
7. the software-hardware synergism method of the SOC debugging verification system as described in claim 1 to 6 any one claim, is characterized in that, comprise the steps:
Step 1: software test case drives the processor of SOC to write A by the system bus of SOC in the register in debugging module, and after this step runs succeeded, the value of the register in debugging module equals A;
Step 2: the value of hardware testing use-case control register, judges whether the value of described register equals A, if be not equal to A, then continues monitoring, if equal A, then continues step 3;
Step 3: hardware testing use-case determination software test case is current ready, hardware testing use-case starts the hardware adaptations environment or the condition of work that build next step operation of SOC;
Step 4: after the hardware adaptations environment that hardware testing use-case is current or condition of work have built, the value of register is revised as B;
Step 5: software test case drives processor by the value of the register in system bus monitoring debugging module, judges whether register value equals B, if be not equal to B, then continues monitoring, if equal B, then continue step 6;
Step 6: software test case determination hardware testing use-case has got out current hardware adaptations environment or condition of work, software test case starts next step operation;
Step 7: circulation step 1 to 6, until software test case and hardware testing use-case have worked in coordination with all debugging checking work mutually;
Value A in above-mentioned steps 1-6, B are arbitrary value, and current A, B value may be the same or different with A, B value in cyclic process before, and the register that current A, B value is deposited may be the same or different with the register existing for A, B value in cyclic process before.
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| CN106708023A (en) * | 2017-01-19 | 2017-05-24 | 延锋伟世通电子科技（上海）有限公司 | Multi-platform compatibility test system and working method thereof |
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| CN113010361A (en) * | 2021-02-22 | 2021-06-22 | 无锡中微亿芯有限公司 | MIO function rapid verification method of fully programmable SOC chip |
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