CN113779907A - HLS-based four-stage pipeline processor design and verification method, system and equipment - Google Patents
HLS-based four-stage pipeline processor design and verification method, system and equipment Download PDFInfo
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- CN113779907A CN113779907A CN202111057025.1A CN202111057025A CN113779907A CN 113779907 A CN113779907 A CN 113779907A CN 202111057025 A CN202111057025 A CN 202111057025A CN 113779907 A CN113779907 A CN 113779907A
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Abstract
The invention relates to the technical field of digital processing, and provides a four-stage pipeline processor design and verification method, a system and equipment based on HLS, which comprise the following steps: analyzing expected function points and test points, and constructing a four-stage pipeline processor model through a high-level language; converting the four-stage pipeline processor model into an RTL-based four-stage pipeline processor model by adopting an HLS tool; executing the test instruction by the four-stage pipeline processor model, and verifying through a UVM verification platform; when the UVM verification platform outputs an error result, analyzing and correcting a four-level pipeline processor model constructed through a high-level language layer by layer; otherwise, the design and verification of the four-stage pipeline processor are completed. According to the invention, the HLS tool is adopted to perform low-level language conversion on the four-level pipeline processor model based on the RISCV instruction set, and verification is performed through the UVM verification platform, so that the time period of processor development and verification can be effectively shortened.
Description
Technical Field
The invention relates to the technical field of digital processing, in particular to a four-stage pipeline processor design and verification method, a four-stage pipeline processor design and verification system and four-stage pipeline processor design and verification equipment based on HLS.
Background
A program written in a high-level language needs to be translated into instructions recognized by a corresponding processor according to a corresponding instruction set architecture through a corresponding compiler. The conventional processor basically adopts two instruction set architectures of x86 and ARM, but because the instruction set is too complex and the cost is high, the free-source RISC-V instruction set architecture is put into development and use. RISC-V is an open Instruction Set Architecture (ISA) built based on Reduced Instruction Set Computing (RISC) principles, which, in contrast to most ISAs, can be used freely in all desired devices, allowing anyone to design, manufacture, and market RISC-V chips and software. Based on RISC-V instruction set architecture, server CPU, household appliance CPU, industrial control CPU and CPU used in sensor smaller than finger can be designed.
However, many open source implementations exist for the CPU designed based on the RISCV, but most of them are implemented by using RTL (register transfer level) code. The CPU designed by using the RTL code alone has a long time period, which has a certain limitation.
Disclosure of Invention
The invention provides a method, a system and equipment for designing and verifying a four-level pipeline processor based on HLS (high-level synthesis) in order to overcome the defect that a CPU (central processing unit) designed by independently using RTL (real time language) codes consumes a longer time period in the prior art.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a HLS-based four-stage pipeline processor design and verification method comprises the following steps:
s1, analyzing the expected function points and test points, and constructing a four-level pipeline processor model based on a RISCV instruction set through a high-level language;
s2, converting the four-stage pipeline processor model into an RTL-based four-stage pipeline processor model by adopting an HLS tool;
s3, executing the test instruction by the RTL-based four-stage pipeline processor model, and verifying through a UVM verification platform;
when the UVM verification platform outputs an error result, after analyzing and correcting the four-level pipeline processor model constructed by the high-level language layer by layer, skipping to execute the step S2; otherwise, the design and verification of the four-stage pipeline processor are completed.
Preferably, the four-level pipeline processor model based on the RISCV instruction set comprises four-level pipeline operations, wherein:
the first stage of pipelining operation: reading instructions from a memory or from an interface; the memory stores instructions to be executed;
and (3) second-stage flow operation: decoding the read instruction;
and (3) third-stage flow operation: distributing the decoded instruction to different operation units for execution according to the specific operation type of the decoded instruction;
fourth-stage flow operation: returning the execution result executed by the arithmetic unit or the data read by accessing the memory to the register or sending the result through the interface; and jumps to the first stage pipelining.
Preferably, the first stage of pipelining further comprises the following steps: acquiring a PC value of the read instruction, and when the PC value is within a preset reading range, taking the instruction out of an instruction memory, otherwise, reading the instruction from an input interface; and the PC value and the read instruction are sent to the second-stage pipeline operation for decoding.
Preferably, in the second-stage pipeline operation, the step of decoding the read instruction includes: assigning the first seven bits in the read instruction to an opcode value for judging the operation type of the executed instruction; the read instruction is translated to generate an immediate, an operand, and a register index.
In the third-stage pipeline operation, according to the judgment of the opcode value obtained by decoding in the second-stage pipeline operation, the decoded instruction is distributed to a corresponding operation unit for execution; when the instruction is a branch jump instruction, calculating a jump address according to a corresponding operand; and when the instruction is a memory access instruction, accessing the corresponding data memory according to the calculated address to store or read data.
Preferably, the fourth stage of the flow operation further comprises the following steps: and when the instruction is a branch jump instruction, calculating the PC value of the next instruction and jumping to the first-stage pipeline operation.
Preferably, in the step S3, when the UVM verification platform is used to verify the four-stage pipeline processor model processed by the HLS tool, the correctness of the four-stage pipeline processor model function is determined by comparing the operation result with the collected coverage, and the completeness of the instruction verification is measured.
Furthermore, the invention also provides a four-stage pipeline processor design and verification system based on HLS, which comprises:
the four-stage pipeline processor design unit is used for analyzing the expected function points and test points and designing a four-stage pipeline processor model;
the construction unit is used for constructing the four-level pipeline processor model through a high-level language;
an HLS tool for converting the four-level pipeline processor model to a four-level pipeline processor model represented by RTL code;
and the UVM verification unit is used for verifying the functional correctness of the four-stage pipeline processor model and measuring the completeness of instruction verification.
Preferably, the UVM verification unit includes:
the test excitation generation and constraint module is used for generating data to be tested;
the data driving module is used for adjusting the time sequence of the data transmission to be tested and then transmitting the data to be tested into the design module to be tested;
the design module to be tested is used for carrying out design processing to be tested on the input data to be tested;
the register model testing module is used for configuring the design module to be tested by using the register model;
the test result collection module is used for collecting the test result output by the design module to be tested;
and the comparison module is used for judging the functional correctness and measuring the completeness of instruction verification by comparing the operation result with the collection coverage rate.
Furthermore, the present invention also provides an apparatus, which includes a memory and a processor, where the memory stores a computer program, and the processor implements the steps of the method according to any of the above technical solutions when executing the computer program.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that: according to the invention, the HLS tool is adopted to perform low-level language conversion on the four-level pipeline processor model based on the RISCV instruction set, and verification is performed through the UVM verification platform, so that the time period of processor development and verification can be effectively shortened, and the labor cost is reduced.
Drawings
FIG. 1 is a flowchart of the HLS based four-stage pipeline processor design and verification method of embodiment 1.
Fig. 2 is an architecture diagram of a four-stage pipeline processor model of example 1.
Fig. 3 is an architecture diagram of a UVM verification platform.
FIG. 4 is a diagram illustrating the coverage of LUI, AUIPC, LOAD, STORE, and branch jump instructions in embodiment 2.
FIG. 5 is a diagram illustrating an I/R instruction override condition according to embodiment 2.
Fig. 6 is a diagram illustrating the coverage of the multiply-divide instruction in embodiment 2.
FIG. 7 is an architecture diagram of the HLS based four-stage pipeline processor design and verification system of embodiment 3.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the patent;
for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product;
it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
Example 1
The present embodiment provides a design and verification method for an HLS-based four-stage pipeline processor, and as shown in fig. 1, the design and verification method is a flowchart of the design and verification method for an HLS-based four-stage pipeline processor of the present embodiment.
The method for designing and verifying the HLS-based four-stage pipeline processor provided by the embodiment comprises the following steps of:
step 1: and analyzing the expected functional points and test points, and constructing a four-level pipeline processor model based on the RISCV instruction set through a high-level language.
In this embodiment, the C language is used to implement the construction of the four-level pipeline processor model based on the RISCV instruction set.
The four-level pipeline processor model in the embodiment comprises four levels of pipeline operations, namely instruction fetching, instruction decoding, instruction execution, memory access, result write-back and the like. Fig. 2 is an architecture diagram of the four-stage pipeline processor model of the present embodiment. The PC is an address of an instruction, and the Port and the Memory respectively correspond to an instruction to read the instruction from an interface and a Memory, IF (instruction fetch unit), ID (instruction decode unit), EX (execution unit), MEM (Memory, access unit), WB (write back unit).
The first stage of pipelining implements the function of reading instructions. The PC (program counter) value of the instruction, i.e., the address where the instruction is located in the memory, reads the instruction from the memory or reads the instruction from the interface by determining the range of the PC value of the instruction. In this embodiment, the memory of the four-stage pipeline processor model adopts a harvard structure, that is, the instruction memory and the data memory are two separate memories, and are respectively used for storing an operating instruction and data to be stored in a Random Access Memory (RAM). The instruction to be executed can be stored in the instruction register in advance, the PC value of the instruction is judged first, when the PC value of the instruction is in the preset reading range, the instruction is taken out from the instruction register, otherwise, the instruction is read from the interface.
The second stage of pipelining implements the function of decoding the read instruction. The instruction and the PC address corresponding to the instruction which are fetched through the first-stage pipeline operation are sent to the second-stage pipeline, so that the decoding operation is realized, namely the fetched instruction is translated, and the generation of immediate, operand, register index and the like is completed. And assigning the first seven bits of the instruction to opcode for judging the operation type of the executed instruction. Furthermore, the index of the corresponding register can be obtained according to the decoded result, so that the value of the operand is obtained. And judging whether the current instruction is a branch jump instruction or not according to the decoding result, if so, returning the PC value of the next instruction (the PC value of the current instruction +4) to the first-stage pipeline operation, and thus, fetching the next instruction.
The third-stage pipeline operation realizes that the decoded instruction is distributed to different operation units to be executed, or the storage or the data reading are carried out on the storage. In the current operation, according to the judgment of the opcode value obtained by decoding, the decoded instruction is distributed to different arithmetic units for control, and the instruction in the embodiment is a 32-bit basic integer instruction set, which includes instructions such as addition, subtraction, shift, size comparison, branch jump, multiplication and division. And if the current instruction is a branch jump instruction, calculating a jump address according to a corresponding operand. And if the current instruction is a memory access instruction, accessing the corresponding data memory according to the calculated address to store or read data.
The fourth-stage pipelining operation realizes that the execution result executed by the arithmetic unit or the data read by accessing the memory is returned to the register or is sent through an interface; and jumps to the first stage pipelining. If the current instruction is a branch jump instruction, calculating a PC value corresponding to the next instruction, jumping to the first-stage pipeline operation, and fetching the next instruction.
Step 2: and converting the four-stage pipeline processor model into an RTL-based four-stage pipeline processor model by adopting an HLS tool.
The HLS tool employed in the present embodiment refers to a tool for automatically converting a logical structure described in a high-level language into a circuit model described in a low-abstraction-level language. Specifically, this embodiment uses Xilinx's vitas HLS tool for conversion.
And step 3: executing a test instruction by the RTL-based four-stage pipeline processor model, and verifying through a UVM verification platform; when the UVM verification platform outputs an error result, analyzing and correcting a four-level pipeline processor model constructed through a high-level language layer by layer, and then jumping to execute the step S2; otherwise, the design and verification of the four-stage pipeline processor are completed.
In the step, when the UVM verification platform is used for verifying the four-stage assembly line processor model processed by the HLS tool, the correctness of the four-stage assembly line processor model function is judged by comparing the operation result with the collection coverage rate, and the completeness of instruction verification is measured. Fig. 3 is an architecture diagram of the UVM verification platform of this embodiment, and a data flow is shown by an arrow in the diagram.
Data to be tested is generated in a test stimulus generation and constraint module (seq _ item), then the timing sequence of stimulus transmission is adjusted through a data driving module (driver), and then the data is transmitted into a design to be tested (DUT) through a top interface (interface), if the design to be tested needs to be configured by using a register model (RAL), the configuration can be completed by developing the register model testing module (RAL _ regblock) through configuration parameters at the top layer of testbench. After the input excitation is processed by the design to be tested, the data is transmitted into a test result collection module (monitor) through an interface module (interface), and then is further transmitted into a comparison model to judge the correctness of the function and measure the completeness of the instruction verification through comparing the operation result with the collection coverage rate.
The embodiment designs a four-level pipeline processor by using a C language through a function description document to realize the function of the function description document, and then converts the C language into RTL code by using an HLS tool. In addition, functional point analysis is carried out through the functional description document, so that test points needing to be tested are obtained, wherein the test points are corresponding functional points for testing. And after obtaining the corresponding test point, verifying the RTL code transferred from the HLS by constructing a UVM verification platform, if the verification fails, analyzing the reason why the verification fails, then modifying the C code, and converting the modified C code into the RTL code by using an HLS tool again. If the UVM passes the verification, the subsequent FPGA can be further subjected to verification analysis.
The four-level pipeline processor design and verification method provided by the embodiment of the invention can effectively shorten the time period of processor development and design by adopting the HLS tool to convert the low-level language of the four-level pipeline processor model based on the RISCV instruction set instead of singly adopting the RTL code to design the processor. In addition, the embodiment also adopts a UVM verification platform for verification, judges the correctness of the function and measures the completeness of the instruction verification by comparing the operation result with the collection coverage rate, has strong object-oriented capability and high reusability, and greatly improves the development efficiency of the verification engineering.
Example 2
This example tests the HLS-based four-stage pipeline processor design and verification method proposed in example 1.
The present embodiment tested 25743 instructions and by comparison with the reference model, eventually 25743 instructions all executed correctly. The specific instruction types are shown in table 1 below.
TABLE 1 test instruction types and quantities
The AUIPC/LUI command performs some operations and operations on the decoded immediate and the PC address of the corresponding command, and returns the result to the corresponding general register set. The BRANCH instruction and the JUMP instruction are respectively a conditional JUMP instruction and an unconditional JUMP instruction, the conditional JUMP instruction can JUMP when meeting a certain condition, and the unconditional JUMP instruction can JUMP without a condition. The STORE and LOAD instructions are STORE and read instructions to the data memory. As shown in FIG. 4, the collected LUI, AUIPC, LOAD, STORE, and branch jump instructions are covered, and it can be seen that each instruction is covered.
I/R instructions, namely ALU (Arithmetic logic Unit) instructions, are used to perform some basic operations, such as: addition, subtraction, shift, and, or, xor, etc. As shown in FIG. 5, in order to collect the I/R instruction coverage conditions through the UVM verification platform, and obtain the execution conditions of different types of I/R instructions, it can be known that each type of I/R instruction is covered.
The multv instruction is a multiply-divide instruction that is used to perform various types of multiply and divide, and remainder operations. As shown in fig. 6, the multiplication-division instruction coverage of this embodiment shows that various operations of multiplication and division are covered.
Example 3
The present embodiment provides a design and verification system for a four-stage pipeline processor based on HLS, and is an architecture diagram of the design and verification system for a four-stage pipeline processor of the present embodiment, as shown in fig. 7.
The four-stage pipeline processor design and verification system provided by this embodiment includes a four-stage pipeline processor design unit, a construction unit, an HLS tool, and a UVM verification unit, which are connected in sequence.
In this embodiment, the four-stage pipeline processor design unit is configured to analyze expected function points and test points and design a four-stage pipeline processor model, the construction unit is configured to construct the four-stage pipeline processor model through a high-level language, the HLS tool is configured to convert the four-stage pipeline processor model into the four-stage pipeline processor model represented by an RTL code, and the UVM verification unit is configured to verify functional correctness of the four-stage pipeline processor model and measure completeness of instruction verification.
Further, the four-stage pipeline processor model designed in this embodiment includes:
the memory is used for storing the instruction to be read;
the input interface is used for transmitting an input instruction;
the instruction fetching module is used for reading instructions from a memory or an input interface;
the decoding module is used for decoding the read instruction;
an arithmetic unit for executing the read instruction;
and the general register group is used for caching the instructions.
Based on the four-stage pipeline processor model structure, the four-stage pipeline processor model of the embodiment executes four-stage pipeline operations.
The first-stage pipeline operation realizes the function of reading the instruction, the instruction PC (namely the address of the instruction in the memory) is input into the instruction fetching module, the instruction fetching module judges the range of the instruction PC, and according to the judgment result, the instruction fetching module reads the instruction from the memory or reads the instruction from the interface. The memory in this embodiment adopts a harvard structure, that is, the instruction memory and the data memory are two separate memories, and are respectively used for storing the executed instructions and the data to be stored in the RAM. The instruction to be executed can be stored in the instruction register in advance, the instruction fetching module can firstly judge the PC value of the instruction fetching, when the PC value of the instruction fetching is within a certain range, the instruction fetching module can fetch the instruction from the instruction memory, otherwise, the instruction fetching module fetches the instruction through the module input port.
The second stage of pipelining implements the function of decoding the read instruction. The instruction taken out from the finger-fetching module and the PC address corresponding to the instruction are sent to the second-stage pipeline to realize decoding operation, namely, the decoding is to translate the taken instruction to complete the generation of immediate, operand, register index and the like. The first seven bits of the instruction are assigned to opcode to determine the type of operation to be performed. According to the decoded result, the index of the corresponding register can be obtained, and therefore the value of the operand can be obtained. And judging whether the instruction is a branch jump instruction or not according to the decoding result, returning the PC value of the next instruction (the PC value of the current instruction +4) to the instruction fetching module, and enabling the instruction fetching module to fetch the next instruction.
The third-stage pipeline operation realizes that the decoded instruction is distributed to different operation units to be executed, or the storage or the data reading are carried out on the storage. According to the judgment of the decoded value of opcode, the decoded value is distributed to different arithmetic units for control, and the currently implemented 32-bit basic integer instruction set comprises: instruction sets such as addition, subtraction, shift, size comparison, branch jump, and multiplication-division. In the case of a branch jump instruction, the address of the jump is calculated from the corresponding operand. And the memory access instruction accesses the corresponding data memory according to the calculated address to store or read data.
The fourth stage of pipelining implements returning the execution results executed by the arithmetic unit or data read by accessing the memory to the register or sending through the interface. The execution result of the third-stage pipeline or the data obtained by accessing the memory is written back to the module return register through the fourth-stage pipeline, and meanwhile, if the instruction is a branch jump instruction, the calculated PC value corresponding to the next instruction is returned to the instruction fetching module to fetch the next instruction.
Further, the UVM verification unit in this embodiment includes:
the test excitation generation and constraint module is used for generating data to be tested;
the data driving module is used for adjusting the time sequence of the data transmission to be tested and then transmitting the data to be tested into the design module to be tested;
the design module to be tested is used for carrying out design processing to be tested on the input data to be tested;
the register model testing module is used for configuring the design module to be tested by using the register model;
the test result collection module is used for collecting the test result output by the design module to be tested;
and the comparison module is used for judging the functional correctness and measuring the completeness of instruction verification by comparing the operation result with the collection coverage rate.
The structure and data flow of the UVM verification unit of this embodiment are shown in fig. 3. Data to be tested is generated in a test stimulus generation and constraint module (seq _ item), then the timing sequence of stimulus transmission is adjusted through a data driving module (driver), and then the data is transmitted into a design to be tested (DUT) through a top interface (interface), if the design to be tested needs to be configured by using a register model (RAL), the configuration can be completed by developing the register model testing module (RAL _ regblock) through configuration parameters at the top layer of testbench. After the input excitation is processed by the design to be tested, the data is transmitted into a test result collection module (monitor) through an interface module (interface), and then is further transmitted into a comparison model to judge the correctness of the function and measure the completeness of the instruction verification through comparing the operation result with the collection coverage rate.
Example 4
This embodiment proposes an apparatus, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the HLS-based four-stage pipeline processor design and verification method proposed in embodiment 1 when executing the computer program.
The terms describing positional relationships in the drawings are for illustrative purposes only and are not to be construed as limiting the patent;
it should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A HLS-based four-stage pipeline processor design and verification method is characterized by comprising the following steps:
s1, analyzing the expected function points and test points, and constructing a four-level pipeline processor model based on a RISCV instruction set through a high-level language;
s2, converting the four-stage pipeline processor model into an RTL-based four-stage pipeline processor model by adopting an HLS tool;
s3, executing the test instruction by the RTL-based four-stage pipeline processor model, and verifying through a UVM verification platform;
when the UVM verification platform outputs an error result, after analyzing and correcting the four-level pipeline processor model constructed by the high-level language layer by layer, skipping to execute the step S2; otherwise, the design and verification of the four-stage pipeline processor are completed.
2. The four-stage pipeline processor design and validation method of claim 1, wherein the RISCV instruction set based four-stage pipeline processor model includes four-stage pipelining operations, wherein:
the first stage of pipelining operation: reading instructions from a memory or from an interface; the memory stores instructions to be executed;
and (3) second-stage flow operation: decoding the read instruction;
and (3) third-stage flow operation: distributing the decoded instruction to different operation units for execution according to the specific operation type of the decoded instruction;
fourth-stage flow operation: returning the execution result executed by the arithmetic unit or the data read by accessing the memory to the register or sending the result through the interface; and jumps to the first stage pipelining.
3. The four-stage pipeline processor design and validation method of claim 2, wherein the first stage pipeline operation further comprises the steps of: acquiring a PC value of the read instruction, and when the PC value is within a preset reading range, taking the instruction out of an instruction memory, otherwise, reading the instruction from an input interface; and the PC value and the read instruction are sent to the second-stage pipeline operation for decoding.
4. The four-stage pipeline processor design and validation method of claim 3, wherein the step of decoding the fetched instructions in the second stage pipeline operation comprises:
assigning the first seven bits in the read instruction to an opcode value for judging the operation type of the executed instruction;
the read instruction is translated to generate an immediate, an operand, and a register index.
5. The design and verification method of four-stage pipeline processor according to claim 4, wherein in the third stage pipeline operation, the decoded instruction is distributed to corresponding arithmetic unit for execution according to the judgment of opcode value decoded in the second stage pipeline operation; when the instruction is a branch jump instruction, calculating a jump address according to a corresponding operand; and when the instruction is a memory access instruction, accessing the corresponding data memory according to the calculated address to store or read data.
6. The four-stage pipeline processor design and validation method of claim 5, wherein the fourth stage pipeline operation further comprises the steps of: and when the instruction is a branch jump instruction, calculating the PC value of the next instruction and jumping to the first-stage pipeline operation.
7. The four-stage pipeline processor design and verification method according to any one of claims 1 to 6, wherein in the step S3, when a UVM verification platform is used for verifying the four-stage pipeline processor model processed by the HLS tool, the correctness of the four-stage pipeline processor model function is judged by comparing the operation result with the collected coverage rate, and the completeness of instruction verification is measured.
8. An HLS-based four-stage pipeline processor design and verification system applying the HLS-based four-stage pipeline processor design and verification method of any one of claims 1-7, comprising:
the four-stage pipeline processor design unit is used for analyzing the expected function points and test points and designing a four-stage pipeline processor model;
the construction unit is used for constructing the four-level pipeline processor model through a high-level language;
an HLS tool for converting the four-level pipeline processor model to a four-level pipeline processor model represented by RTL code;
and the UVM verification unit is used for verifying the functional correctness of the four-stage pipeline processor model and measuring the completeness of instruction verification.
9. The four-stage pipeline processor design and verification system of claim 8, wherein the UVM verification unit comprises:
the test excitation generation and constraint module is used for generating data to be tested;
the data driving module is used for adjusting the time sequence of the data transmission to be tested and then transmitting the data to be tested into the design module to be tested;
the design module to be tested is used for carrying out design processing to be tested on the input data to be tested;
the register model testing module is used for configuring the design module to be tested by using the register model;
the test result collection module is used for collecting the test result output by the design module to be tested;
and the comparison module is used for judging the functional correctness and measuring the completeness of instruction verification by comparing the operation result with the collection coverage rate.
10. An apparatus comprising a memory storing a computer program and a processor implementing the steps of the method of any one of claims 1 to 7 when the computer program is executed by the processor.
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| 蔡红艳等: "基于高层次综合工具的BIST控制器设计", 《电子技术应用》, pages 27 - 30 * |
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