CN117056157B - Register hierarchy verification method, storage medium and electronic equipment - Google Patents
Register hierarchy verification method, storage medium and electronic equipment Download PDFInfo
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- CN117056157B CN117056157B CN202311309239.2A CN202311309239A CN117056157B CN 117056157 B CN117056157 B CN 117056157B CN 202311309239 A CN202311309239 A CN 202311309239A CN 117056157 B CN117056157 B CN 117056157B
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- 238000012795 verification Methods 0.000 title claims abstract description 97
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000013507 mapping Methods 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the field of chip verification, in particular to a register level verification method, a storage medium and electronic equipment, which are used for acquiring mode selection signals of N verification levels according to specified S uvc_i Acquisition of hk i The physical bus interface proxy list of (2) obtains the destination address to be accessed, and according to hk in the destination address i Base address lookup hk for physical bus interface of (a) i Is to obtain the phy_agent from the physical bus interface agent list i,m By phy i,m And IF (IF) i,k Accessing hk i The method comprises the steps of carrying out a first treatment on the surface of the Finding hk from destination address i Accessing a next authentication level; sequentially accessing authentication hierarchy to S uvc_1 At this time, S is accessed according to the offset address of the register uvc_1 The verification of the t-th register is completed. The invention does not need to separately configure and separately verify, simplifies the verification process, improves the verification efficiency and keeps the uniformity of verification.
Description
Technical Field
The present invention relates to the field of chip verification, and in particular, to a register hierarchy verification method, a storage medium, and an electronic device.
Background
A plurality of registers, such as a status register, a control register and the like, are defined in the design under test (design under test, DUT), and during the verification process, whether the configuration of the registers is correct is verified first, and the correct behavior of the design under test can be ensured when the configuration of the registers is correct. In the process of verifying whether the configuration of the register is correct, the register needs to be frequently read and written, for example, a verification platform needs to acquire the parameter value of the designated register. Registers are typically accessed through a register model that builds a hierarchical register model by abstracting out registers in the design under test. In the register model, a plurality of registers form a block, a plurality of blocks form a subsystem, and a plurality of subsystems form a system (top), wherein the block, the subsystem and the system form different verification levels, the different verification levels are independently verified during verification, each verification level needs to be independently configured and independently verified, and the verification process is complex.
Disclosure of Invention
Aiming at the technical problems, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a register level verification method, the method comprising the steps of:
s100, obtaining mode selection signals { S } of N verification levels uvc_1 ,S uvc_2 ,…,S uvc_i ,…,S uvc_N }，S uvc_i For the ith verification level hk in the chip i The value range of i is 1 to N; wherein S is uvc_1 For a mode select signal comprising the lowest verification level of a register, S uvc_N A mode select signal for a top verification level comprising N verification levels.
S200, according to the specified S uvc_i Acquisition of hk i Is a virtual bus agent, hk i Corresponds to a physical bus interface agent list { phy_agent ] i,1 ,phy_agent i,2 ,…,phy_agent i,m ,…,phy_agent i,M(i) }，phy_agent i,m Is hk i M is in the range of 1 to M (i), M (i) is hk i The number of physical bus interface agents; phy_agent i,m And hk i Is the kth physical bus interface IF i,k There is a one-to-one mapping relationship between them.
S300, obtaining a destination address to be accessed, wherein the destination address comprises an offset address of a t-th register and a base address of a physical bus interface of i verification levels, the i verification levels are from the i-th verification level S uvc_i To S uvc_1 。
S400, according to hk in destination address i Base address lookup hk for physical bus interface of (a) i Is to obtain the phy_agent from the physical bus interface agent list i,m Through the phy_agent i,m And IF (IF) i,k Accessing hk i 。
S500, searching hk according to the destination address i Is accessed for the next level of authentication.
S600, sequentially accessing the verification level to S uvc_1 At this time, S is accessed according to the offset address of the register uvc_1 The verification of the t-th register is completed.
The present invention also provides a non-transitory computer readable storage medium having stored therein at least one instruction or at least one program loaded and executed by a processor to implement the above-described method.
Furthermore, the invention also provides an electronic device comprising a processor and the non-transitory computer readable storage medium.
The invention has at least the following beneficial effects:
the invention saves all maps of the lookup register in each physical bus interface, controls the verification level by controlling the mode selection signal during verification, does not need to separately configure and separately verify, simplifies the verification process, improves the verification efficiency and keeps the uniformity of the verification.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a register level verification method according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
Referring to fig. 1, a flowchart of a register level verification method is shown, the method comprising the steps of:
s100, obtaining mode selection signals { S } of N verification levels uvc_1 ,S uvc_2 ,…,S uvc_i ,…,S uvc_N }，S uvc_i For the ith verification level hk in the chip i The value range of i is 1 to N; wherein S is uvc_1 Verification level hk, which is the lowest level comprising registers 1 Mode selection signal of S uvc_N For a top level authentication level hk comprising N authentication levels N Is provided.
Wherein the mode select signal is used to select any one of the authentication levels. Optionally, the step of acquiring the mode selection signal includes: configuring one-bit binary code for each verification level to obtain N-bit binary codes; each verification level has both valid and invalid states, when the ith verification level hk i When effective, hk is determined i The binary coded position of the configuration is 1, otherwise it is set to 0.
Wherein the low one of the authentication levels is a subset of the high authentication level, i.e. the i-1 st authentication level hk i-1 Is hk i Is a subset of the set of (c).
Wherein the bottom verification level hk in the verification levels 1 For verifying registers, at hk 1 Including a plurality of registers. hk (hk) 2 To include hk 1 Higher level of verification level, hk 3 To include hk 2 Higher level of verification hierarchy of (a), and so on, hk N Is a verification hierarchy that includes all verification hierarchies. At each level of the verification hierarchy, a layer is more abstract at the module level, such as at the register level, functional module level, subsystem level, system level, and the like. A plurality of units to be verified may be included in each verification hierarchy, each unit to be verified including a plurality of physical bus interfaces.
S200, according to the specified S uvc_i Acquisition of hk i Is a virtual bus agent, hk i Corresponds to a physical bus interface agent list { phy_agent ] i,1 ,phy_agent i,2 ,…,phy_agent i,m ,…,phy_agent i,M(i) }，phy_agent i,m Is hk i M is in the range of 1 to M (i), M (i) is hk i The number of physical bus interface agents; phy_agent i,m And hk i Is the kth physical bus interface IF i,k Has a mapping relation. Note that, the phy_agent i,m And IF (intermediate frequency) i,k Has a one-to-one mapping relationship, and the data signal passes through the phy_agent i,m And IF (IF) i,k The ith authentication level hk in the access chip i 。
Each verification level is provided with a virtual bus agent, each virtual bus agent corresponds to a physical bus interface agent list, and each physical bus interface agent corresponds to a physical bus interface one by one. Ith authentication level hk in chip i The number of physical bus interfaces and hk i The number of physical bus interface agents M (i) in the list of physical bus interface agents is equal.
S300, obtaining a destination address to be accessed, wherein the destination address comprises an offset address of a t-th register and a base address of a physical bus interface of i verification levels, the i verification levels are from the i-th verification level S uvc_i To S uvc_1 。
Wherein each authentication hierarchy includes a plurality of physical bus interfaces. The base addresses of different physical bus interfaces are different.
Wherein the base address of the authentication level is the entry address of the interface of the authentication level. The t-th register reg t Is set to reg t At the bottom verification level hk 1 Middle relative to hk 1 An address offset of a base address of (a).
Optionally, the destination address is the address { addr of the concatenation of the offset address of the t-th register and the base address of the physical bus interface of the i verification levels i ,bladdr i-1 ,…,bladdr f ,…,bladdr 1 ,regaddr t }, wherein the addr is a blader f For the f-th authentication level hk f The value of f ranges from 1 to i, regaddr t Is the offset address of the t-th register. According to the offset address of the t register in the spliced destination address and the base address of the physical bus interface of the i verification levels, the t register can be accessed layer by layer.
S400, according to hk in destination address i Base address lookup hk for physical bus interface of (a) i Is to obtain the phy_agent from the physical bus interface agent list i,m Through the phy_agent i,m And IF (IF) i,k Accessing hk i 。
Wherein, the physical bus interface is proxy agent i,m And physical bus interface IF i,k Mapping and associating, and enabling access request to proxy phy_agent through physical bus interface i,m And physical bus interface IF i,k Accessing the ith authentication level hk i 。
S500, searching hk according to the destination address i Is accessed for the next level of authentication.
As a preferred embodiment, hk i The system comprises G (i) parallel units to be verified, wherein all physical bus interfaces in the parallel units to be verified have the same map.
As a preferred embodiment, the hk i The construction step of the map of the physical bus interface comprises the following steps:
s10, obtaining hk 1 Register information of G (1) units to be verified. It should be noted that a plurality of different verification units may be included in each verification hierarchy. Wherein for hk 1 G (1) units to be verified, each unit to be verified comprising a plurality of registers. Each unit to be verified comprises a plurality of physical bus interfaces.
S20, respectively acquiring hk 1 G (1) registers of units to be verified to obtain G (1) offset address sequences; wherein hk 1 The configuration step of the j-th unit to be verified comprises the following steps: separately configuring hk 1 The offset address of each register of the j-th unit to be verified in the (b) is obtained to obtain an offset address sequence addr j The value of j ranges from 1 to G (1). It should be noted that the configuration of the register includes offset address, read-only or read-write operation, and the like.
S30, respectively acquiring hk 1 The base address of all physical bus interfaces in each unit to be verified.
S40, hk is processed 1 G (1) offset address sequences of (1) are bound to each base address to obtain hk 1 Is a map of each physical interface. It should be noted that since each base address binds hk 1 G (1) offset address sequences, i.e. access to each physical bus interface, can reach any one register.
S50, hk is respectively carried out 1 Map of all physical interfaces in (a) is sent to hk 2 Obtaining hk 2 Is a map of (a).
S60, hk is taken 2 The map of the upper verification level is synchronized from the lower verification level to the upper verification level step by step through the physical bus interfaces of the verification levels, and the base address of the physical bus interface of each passed verification level is sequentially bound with the map of the physical bus interface to obtain hk i Is a map of the physical bus interface of (c).
S60 further includes:
s61, respectively obtaining hk 2 The base address of all physical bus interfaces in each unit to be verified.
S62, respectively hk 2 Map of (c) and hk 2 Binding the base address of each physical bus interface to obtain hk 2 A map of each physical bus interface.
S63, hk is respectively 2 Map of all physical bus interfaces in (a) is sent to hk 3 Obtaining hk 3 Is a map of (a).
S64, and so on, to obtain hk i Is a map of the physical bus interface of (c).
Alternatively, hk i The step of constructing the map of the physical bus interface of (c) may be any step prior to the execution of S500.
S600, according toSecondary access authentication hierarchy to S uvc_1 At this time, S is accessed according to the offset address of the register uvc_1 The verification of the t-th register is completed.
As a preferred embodiment, S40 further includes marking M (1) offset address sequences as different identifiers, respectively, and establishing an association relationship between the identifiers and the offset address sequences of the register; hk is set 1 Binding an identifier of M (1) offset address sequences with each base address to obtain hk 1 Intra-cell maps of each physical bus interface. By associating M (1) offset address sequences with identifiers in each map, hardware storage resources can be conserved.
By the method, the map of each physical bus interface in each verification level can be obtained, and the target register can be quickly accessed by inquiring the map through the destination address during each verification. Compared with the prior art that a set of verification maps are required to be configured for each verification level separately and each verification level is required to be verified separately, the embodiment of the invention enables all maps for searching the target register to be stored in each physical bus interface by configuring the maps for each physical bus interface in all verification levels, and can control the verification levels through controlling the mode selection signal during verification without separately configuring and verifying separately, thereby simplifying the verification process, improving the verification efficiency and keeping uniformity through verification.
Embodiments of the present invention also provide a non-transitory computer readable storage medium that may be disposed in an electronic device to store at least one instruction or at least one program for implementing one of the methods embodiments, the at least one instruction or the at least one program being loaded and executed by the processor to implement the methods provided by the embodiments described above.
Embodiments of the present invention also provide an electronic device comprising a processor and the aforementioned non-transitory computer-readable storage medium.
Embodiments of the present invention also provide a computer program product comprising program code for causing an electronic device to carry out the steps of the method according to the various exemplary embodiments of the invention as described in the specification, when said program product is run on the electronic device.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. Those skilled in the art will also appreciate that many modifications may be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (8)
1. A method of register level verification, the method comprising the steps of:
s100, obtaining mode selection signals { S } of N verification levels uvc_1 ,S uvc_2 ,…,S uvc_i ,…,S uvc_N }，S uvc_i For the ith verification level hk in the chip i The value range of i is 1 to N; wherein S is uvc_1 For a mode select signal comprising the lowest verification level of a register, S uvc_N A mode select signal for a top verification level comprising N verification levels;
s200, according to the specified S uvc_i Acquisition of hk i Is a virtual bus agent, hk i Corresponds to a physical bus interface agent list { phy_agent ] i,1 ,phy_agent i,2 ,…,phy_agent i,m ,…,phy_agent i,M(i) }，phy_agent i,m Is hk i M is in the range of 1 to M (i), M (i) is hk i The number of physical bus interface agents; phy_agent i,m And hk i Is the kth physical bus interface IF i,k A one-to-one mapping relation exists between the two;
s300, obtaining a destination address to be accessed, wherein the destination address comprises an offset address of a t-th register and a base address of a physical bus interface of i verification levels, the i verification levels are from the i-th verification level S uvc_i To S uvc_1 ；
S400, according to hk in destination address i Base address lookup hk for physical bus interface of (a) i Is to obtain the phy_agent from the physical bus interface agent list i,m Through the phy_agent i,m And IF (IF) i,k Accessing hk i ；
S500, searching hk according to the destination address i Accessing a next authentication level;
s600, sequentially accessing the verification level to S uvc_1 At this time, S is accessed according to the offset address of the register uvc_1 Finishing the verification of the t register;
wherein hk i The method comprises the steps that G (i) parallel units to be verified are included, and all physical bus interfaces in the parallel units to be verified have the same map; s500 also includes the hk i The construction step of the map of the physical bus interface:
s10, obtaining hk 1 Register information of G (1) units to be verified;
s20, respectively acquiring hk 1 G (1) registers of units to be verified to obtain G (1) offset address sequences;
s30, respectively acquiring hk 1 Base addresses of all physical bus interfaces in each unit to be verified;
s40, hk is processed 1 G (1) offset address sequences of (1) are bound to each base address to obtain hk 1 A map of each physical interface in the database;
s50, hk is respectively carried out 1 Map of all physical interfaces in (a) is sent to hk 2 Obtaining hk 2 Is a map of (2);
s60, hk is taken 2 The map of the upper verification level is synchronized from the lower verification level to the upper verification level step by step through the physical bus interfaces of the verification levels, and the base address of the physical bus interface of each passed verification level is sequentially bound with the map of the physical bus interface to obtain hk i Is a map of the physical bus interface;
wherein S60 further comprises:
s61, respectively obtaining hk 2 Each of which is to be testedThe base addresses of all physical bus interfaces in the certificate unit;
s62, respectively hk 2 Map of (c) and hk 2 Binding the base address of each physical bus interface to obtain hk 2 A map of each physical bus interface;
s63, hk is respectively 2 Map of all physical bus interfaces in (a) is sent to hk 3 Obtaining hk 3 Is a map of (2);
s64, and so on, to obtain hk i Is a map of the physical bus interface of (c).
2. The method of claim 1, wherein the destination address in S300 is an address { bladdr for a concatenation of an offset address of a t-th register and a base address of a physical bus interface of i verification levels i ,bladdr i-1 ,…,bladdr f ,…,bladdr 1 ,regaddr t }, wherein the addr is a blader f For the f-th authentication level hk f The value of f ranges from 1 to i, regaddr t Is the offset address of the t-th register.
3. The method of claim 1, wherein S40 further comprises marking M (1) offset address sequences as different identifiers, respectively, and establishing an association between the identifiers and the offset address sequences of the registers; hk is set 1 Binding an identifier of M (1) offset address sequences with each base address to obtain hk 1 Intra-cell maps of each physical bus interface.
4. The method according to claim 1, wherein the step of acquiring the mode selection signal in S100 includes: configuring one-bit binary code for each verification level to obtain N-bit binary codes; each verification level has both valid and invalid states, when the ith verification level hk i When effective, hk is determined i The binary coded position of the configuration is 1, otherwise it is set to 0.
5. According to claimThe method of claim 1, wherein the i-1 th authentication level hk i-1 Is hk i Is a subset of the set of (c).
6. The method of claim 1, wherein in S200, an ith verification level hk in the chip i The number of physical bus interfaces and hk i The number of physical bus interface agents M (i) in the list of physical bus interface agents is equal.
7. A non-transitory computer readable storage medium having stored therein at least one instruction or at least one program loaded and executed by a processor to implement the method of any one of claims 1-6.
8. An electronic device comprising a processor and the non-transitory computer readable storage medium of claim 7.
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