CN117033003B - Memory management method, electronic equipment and medium based on SystemVerilog - Google Patents
Memory management method, electronic equipment and medium based on SystemVerilog Download PDFInfo
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- CN117033003B CN117033003B CN202311303206.7A CN202311303206A CN117033003B CN 117033003 B CN117033003 B CN 117033003B CN 202311303206 A CN202311303206 A CN 202311303206A CN 117033003 B CN117033003 B CN 117033003B
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- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
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Abstract
The invention relates to the technical field of chip verification, in particular to a memory management method, electronic equipment and medium based on SystemVerilog, which comprises the following steps of S1, obtaining a process list { B ] of chip design to be tested 1 ,B 2 ,…,B m ,…,B M -a }; step S2, instantiating a memory space on a verification platform based on SystemVerilog language, and dividing the memory space into M independent memory areas { A } 1 ,A 2 ,…,A m ,…,A M -the verification platform is generated based on the SystemVerilog language; step S3, A is carried out m Set as B m A corresponding memory region; step S4, the verification platform first and B m When interaction is carried out, application A is applied for in the memory space m The verification platform and B m At A m Data is written or read. The invention is convenient for the memory management of the verification platform and improves the simulation speed of chip verification.
Description
Technical Field
The present invention relates to the field of chip verification technologies, and in particular, to a memory management method, an electronic device, and a medium based on SystemVerilog.
Background
In the chip verification process, a verification platform (Testbench) needs to interact with a design under test (Design Under Test, DUT for short), and in the interaction process, memory management needs to be performed on the storage space of the verification platform. In the prior art, a dynamic memory allocation function (Malloc) is generally used for memory management. However, the dynamic memory allocation function is implemented based on the C language, and the verification platform is implemented based on the SystemVerilog, and in addition, the dynamic memory allocation function usually needs to apply and release memory frequently, if the dynamic memory allocation function is applied to the verification platform in a memory management manner, on one hand, the problem of cross-language needs to be solved, and the complexity and the cost are high, on the other hand, a large amount of storage is consumed, so that the simulation speed of chip verification is affected, and the system performance is affected. Therefore, how to provide a memory management technology suitable for a verification platform used in a chip verification process, and to improve the simulation speed of chip verification is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a memory management method, electronic equipment and medium based on SystemVerilog, which are convenient for the memory management of a verification platform and improve the simulation speed of chip verification.
According to a first aspect of the present invention, there is provided a memory management method based on SystemVerilog, including:
step S1, obtaining a process list { B } of the chip design to be tested 1 ,B 2 ,…,B m ,…,B M }，B m The M-th process designed for the chip to be tested, wherein the value range of M is 1 to M, and M is the total number of processes designed for the chip to be tested;
step S2, instantiating a memory space on a verification platform based on SystemVerilog language, and dividing the memory space into M independent memory areas { A } 1 ,A 2 ,…,A m ,…,A M },A m The verification platform is generated based on the SystemVerilog language for the mth memory area;
step S3, A is carried out m Set as B m A corresponding memory region;
step S4, the verification platform first and B m When interaction is carried out, application A is applied for in the memory space m The verification platform and B m At A m Data is written or read.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium having computer instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the memory management method, the electronic equipment and the medium based on the SystemVerilog can achieve quite technical progress and practicality, have wide industrial application value, and have at least the following beneficial effects:
according to the embodiment of the invention, the memory space is instantiated on the verification platform based on the SystemVerilog, an independent memory space is allocated for each process of the chip design to be tested, and when the verification platform interacts with the process of the chip design to be tested for the first time, the process of the chip design to be tested for the first time in the memory space applies for the corresponding memory, so that the independence of each process of the chip design to be tested is ensured, and memory conflict is avoided. The memory management is directly performed on the verification platform based on the SystemVerilog, so that the complexity of the memory management of the chip verification platform is reduced, the simulation speed of chip verification is improved, and the system performance is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a memory management method based on systmeverilog according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a memory management method based on SystemVerilog, which is applied to a chip verification scene, and in the chip verification process, a verification platform is required to be arranged, and chip verification is realized through interaction of the verification platform and a chip design to be tested. As shown in fig. 1, the method includes:
step S1, obtaining a process list { B } of the chip design to be tested 1 ,B 2 ,…,B m ,…,B M }，B m And the M-th process designed for the chip to be tested, wherein the value range of M is 1 to M, and M is the total number of processes designed for the chip to be tested.
It should be noted that, in the chip verification scenario, the chip design to be tested includes M independent processes, and in the process of interaction between the chip design to be tested and the verification platform, an independent memory needs to be applied for each process, so that memories between different processes do not conflict, and the chip verification process can be completed, and frequent application and release are not needed.
Step S2, instantiating a memory space on a verification platform based on SystemVerilog language, and dividing the memory space into M independent memory areas { A } 1 ,A 2 ,…,A m ,…,A M },A m And generating the verification platform for the mth memory area based on the SystemVerilog language.
It should be noted that, the verification platform is generated based on the SystemVerilog language, and the memory management of the embodiment of the invention is also directly realized based on the SystemVerilog language, so that a dynamic memory allocation function realized by a C language is not required to be adopted to manage the memory, and the system performance is improved.
Step S3, A is carried out m Set as B m A corresponding memory region.
It will be appreciated that A is established by step S3 m And B m Is realized as each B m An independent memory space is allocated.
Step S4, the verification platform first and B m When interaction is carried out, application A is applied for in the memory space m The verification platform and B m At A m Data is written or read.
It is noted that build A m And B m After the mapping of (a), not all B are directly given m Applying for memory in the authentication platform, but rather in the authentication platformStage and B m Based on A again when the first interaction is carried out m And B m Is B m The corresponding memory is applied, so that the space consumption is reduced, and the simulation speed of chip verification is improved.
As an embodiment, the step S2 includes:
step S21, instantiating a memory space on the verification platform, wherein the memory space comprises N addresses, and the bit number of each address is W.
Step S22, dividing the same address of the high S bits into a memory space to obtain M independent memory areas { A } 1 ,A 2 ,…,A m ,…,A M S, where S<W, S, M satisfies: 2 S =m, each a m Comprises 2 of W-S Address, M x 2 W-S =N。
It should be noted that, the memory space is grouped by the high S bits, so that the memory area can be quickly and accurately grouped, and the data can be conveniently read or written in each independent memory area.
As an embodiment, in the step S4, the verification platform and B m At A m Data is written or read in, including:
step S41, the verification platform or B m Generating a read or write B m Request for data.
It will be appreciated that during the process of verifying the platform and chip design under test interaction, B m The reading or writing of the data can be initiated by the verification platform or by the chip design to be tested.
Step S42, the verification platform writes B from the writing m Resolving the target write address and target write data in the request of the data, at A m Target write data is written in the target write address of (a).
Step S43, the verification platform reads B from the computer m Resolving target read address from request of data, slave A m The read target read data in the target read address is returned to the verification platform or B m 。
The positions of step S42 and step S43 may be interchanged, or one of them may be executed.
As an example, A m Is provided with a writing state mark, when A m When the middle is empty, the writing state identifier is set as a first state identifier, when A m When not empty, the writing state identifier is set to a second state identifier, and before executing the step S42, the method includes:
step S420, detect A m If the write status is the first status, an error indication is generated, and if the write status is the second status, step S42 is executed.
In the case where the program is running normally, if the program is to be executed in the program a m With the need to read data, then A m Should store the corresponding written data, thus, if A needs to be read m When A is m If empty, then it is stated that the procedure is problematic, and should be timed out, step S420 is performed by comparing A with A m Setting writing state mark in the pair A m When reading data, firstly judging A by writing state identification m If the read operation is empty, generating an error prompt in time, and if the read operation is not empty, executing the corresponding read operation.
When the memory space to be instantiated on the verification platform is very large, the corresponding independent memory area A is usually m Also very large, the verification platform is first with B m When interaction is carried out, application A is applied for in the memory space m The simulation speed is also affected, so when the memory space to be instantiated on the verification platform is greater than a certain threshold, the memory management manner of step S2-step S4 may not reach the memory management expectation, and based on this, as an embodiment, the following steps in step S1 include:
step S10, if the Memory space to be instantiated on the verification platform is smaller than a preset space threshold, executing step S2, otherwise, allocating Memory for the process designed by the chip to be tested based on a Hash Memory mode, wherein the Hash Memory mode is that when the process designed by the chip to be tested needs to allocate Memory, the Memory with the corresponding size is allocated, and when the Memory is not needed to be allocated, the Memory is not allocated.
The preset spatial threshold is set according to a specific application scene.
Both the verification platform and the chip design to be tested can directly access B m Corresponding A m Other processes cannot directly access B m Corresponding A m If other processes have access B based on the specific scene of the design to be tested m Corresponding A m If the requirement is met, the corresponding access setting information is required to be set, so that the access can be realized, and the independence of the memory corresponding to each process is ensured.
For other process pairs B m Corresponding A m In the case of having a read requirement, as an embodiment, the step S3 further includes:
step S301, build A m Corresponding readable Process set { B } 1 m1 ,B 2 m1 ,…,B x m1 ,…,B f(m) m1 }，B x m1 Is A m The corresponding x-th readable process, wherein the value range of x is 1 to f (m), and f (m) is A m Corresponding total number of readable processes, f (m) is more than or equal to 0, B x m1 {B 1 ,B 2 ,…,B m ,…,B M And B (V) x m1 ≠B m 。
Step S302, if the jth process B j Sending a read B to the verification platform m Data request, judge B j Whether or not to { B 1 m1 ,B 2 m1 ,…,B x m1 ,…,B f(m) m1 If it belongs to, the verification platform reads B from m Resolving target read address from data request of A m Target read data corresponding to the target read address is read, if the target read data does not belong to the target read address, the jth process B is not executed j Read B sent to the verification platform m Is a function of the data of the (c). Thereby ensuring B m Corresponding A of (2) m Is independent of the (c).
For other process pairs B m Corresponding A m In the case of having a write requirement, as an embodiment, the step S3 further includes:
step S311, build A m Corresponding writable Process information set { C 1 m2 ,C 2 m2 ,…,C y m2 ,…,C g(m) m2 }，C y m2 Is A m Corresponding y-th writable progress information, wherein the value range of y is 1 to g (m), and g (m) is A m Corresponding total number of writable processes, g (m) is more than or equal to 0, C y m2 =（B y m2 ,D y m2 ），B y m2 Is C y m2 Corresponding process, D y m2 Is C y m2 Corresponding writable Address, B y m2 {B 1 ,B 2 ,…,B m ,…,B M And B (V) y m2 ≠B m 。
In order to ensure B m Corresponding A of (2) m Is not normally allowed to go to B m Corresponding A of (2) m Write data, but in some cases some other process needs to go to B m Corresponding A of (2) m Data is written to the partial address in (b), so step S311 sets a m Corresponding writable Process information set { C 1 m2 ,C 2 m2 ,…,C y m2 ,…,C g(m) m2 Clearly set to write A m Is associated with the address of the corresponding writable address.
Step S312, if the ith process B i Sending write B to the verification platform m Data request, judge B i Whether or not to { C 1 m2 ,C 2 m2 ,…,C y m2 ,…,C g(m) m2 Some C in } y m2 Corresponding B y m2 If yes, executing the steps ofS313, otherwise, not execute B i Sending write B to the verification platform m Manipulation of data.
Step S313, the verification platform writes B from the m Resolving a target write address from a request of data, and acquiring B i In { C 1 m2 ,C 2 m2 ,…,C y m2 ,…,C g(m) m2 Corresponding target D in } y m2 If the target write address is at the target D y m2 Then execute the ith process B i Sending write B to the verification platform m Request of data, otherwise, not execute B i Sending write B to the verification platform m Manipulation of data.
Setting through step S311-step S313 can be done to a m A process of writing data, and corresponding writable address, when other processes are directed to A m When writing data, the data needs to be written through { C 1 m2 ,C 2 m2 ,…,C y m2 ,…,C g(m) m2 Check of } can be directed to A m Write data, ensure B m Corresponding A of (2) m Is independent of the (c).
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.
According to the embodiment of the invention, the memory space is instantiated on the verification platform based on the SystemVerilog, an independent memory space is allocated for each process of the chip design to be tested, and when the verification platform interacts with the process of the chip design to be tested for the first time, the process of the chip design to be tested for the first time in the memory space applies for the corresponding memory, so that the independence of each process of the chip design to be tested is ensured, and memory conflict is avoided. The memory management is directly performed on the verification platform based on the SystemVerilog, so that the complexity of the memory management of the chip verification platform is reduced, the simulation speed of chip verification is improved, and the system performance is improved.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (8)
1. The memory management method based on SystemVerilog is characterized by comprising the following steps:
step S1, obtaining a process list { B } of the chip design to be tested 1 ,B 2 ,…,B m ,…,B M }，B m The M-th process designed for the chip to be tested, wherein the value range of M is 1 to M, and M is the total number of processes designed for the chip to be tested;
step S2, instantiating a memory space on a verification platform based on SystemVerilog language, and dividing the memory space into M independent memory areas { A } 1 ,A 2 ,…,A m ,…,A M },A m The verification platform is generated based on the SystemVerilog language for the mth memory area;
step S3, A is carried out m Set as B m A corresponding memory region;
step S4, the verification platform first and B m When interaction is carried out, application A is applied for in the memory space m The verification platform and B m At A m Write or read data in;
the step S3 further includes:
step S301, build A m Corresponding readable Process set { B } 1 m1 ,B 2 m1 ,…,B x m1 ,…,B f(m) m1 }，B x m1 Is A m The corresponding x-th readable process, wherein the value range of x is 1 to f (m), and f (m) is A m Corresponding total number of readable processes, f (m) is more than or equal to 0, B x m1 {B 1 ,B 2 ,…,B m ,…,B M And B (V) x m1 ≠B m ；
Step S302, if the jth process B j Sending a read B to the verification platform m Data request, judge B j Whether or not to { B 1 m1 ,B 2 m1 ,…,B x m1 ,…,B f(m) m1 If it belongs to, the verification platform reads B from m Resolving target read address from data request, slave A m Target read data corresponding to the target read address is read, if the target read data does not belong to the target read address, the jth process B is not executed j Read B sent to the verification platform m Manipulation of data.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S2 includes:
step S21, instantiating a memory space on a verification platform, wherein the memory space comprises N addresses, and the bit number of each address is W;
step S22, dividing the same address of the high S bits into a memory space to obtain M independent memory areas { A } 1 ,A 2 ,…,A m ,…,A M S, where S<W, S, M satisfies: 2 S =m, each a m Comprises 2 of W-S Address, M x 2 W-S =N。
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the saidIn step S4, the verification platform and B m At A m Data is written or read in, including:
step S41, the verification platform or B m Generating a read B m Request or write of data B m A request for data;
step S42, the verification platform writes B from the write m Resolving the target write address and target write data in the request of the data, at A m Writing target write data in a target write address of (a);
step S43, the verification platform reads B from the reader m Resolving target read address from request of data, slave A m The read target read data in the target read address is returned to the verification platform or B m 。
4. The method of claim 3, wherein the step of,
A m is provided with a writing state mark, when A m When the middle is empty, the writing state identifier is set as a first state identifier, when A m When not empty, the writing state identifier is set to a second state identifier, and before executing the step S42, the method includes:
step S420, detect A m If the write status is the first status, an error indication is generated, and if the write status is the second status, step S42 is executed.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S1 includes:
step S10, if the memory space which is needed to be instantiated on the verification platform is smaller than a preset space threshold, executing step S2, otherwise, distributing the memory for the process designed by the chip to be tested based on a hash storage mode, wherein the hash storage mode is that when the process designed by the chip to be tested needs to distribute the memory, the memory with the corresponding size is distributed, and when the memory does not need to be distributed, the memory is not distributed.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S3 further includes:
step S311, build A m Corresponding writable Process information set { C 1 m2 ,C 2 m2 ,…,C y m2 ,…,C g(m) m2 }，C y m2 Is A m Corresponding y-th writable progress information, wherein the value range of y is 1 to g (m), and g (m) is A m Corresponding total number of writable processes, g (m) is more than or equal to 0, C y m2 =（B y m2 ,D y m2 ），B y m2 Is C y m2 Corresponding process, D y m2 Is C y m2 Corresponding writable Address, B y m2 {B 1 ,B 2 ,…,B m ,…,B M And B (V) y m2 ≠B m ；
Step S312, if the ith process B i Sending write B to the verification platform m Data request, judge B i Whether or not to { C 1 m2 ,C 2 m2 ,…,C y m2 ,…,C g(m) m2 Some C in } y m2 Corresponding B y m2 If yes, go to step S313, otherwise, do not perform B i Sending write B to the verification platform m Manipulation of the data;
step S313, the verification platform writes B from the m Resolving a target write address from a request of data, and acquiring B i In { C 1 m2 ,C 2 m2 ,…,C y m2 ,…,C g(m) m2 Corresponding target D in } y m2 If the target write address is at the target D y m2 Then execute the ith process B i Sending write B to the verification platform m Request of data, otherwise, not execute B i Issue to the verification platformWrite B m Manipulation of data.
7. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-6.
8. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-6.
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| CN113850036A (en) * | 2021-08-27 | 2021-12-28 | 山东云海国创云计算装备产业创新中心有限公司 | Information enumeration method, device, equipment and readable storage medium |
| CN114707453A (en) * | 2022-03-29 | 2022-07-05 | 上海阵量智能科技有限公司 | Chip function verification method and device, electronic equipment and storage medium |
| CN114997101A (en) * | 2022-05-27 | 2022-09-02 | 山东云海国创云计算装备产业创新中心有限公司 | Signal control method, system, medium and device based on chip verification system |
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