CN116306400B

CN116306400B - Integrated circuit verification method, system, device, equipment and medium

Info

Publication number: CN116306400B
Application number: CN202310552444.5A
Authority: CN
Inventors: 杨兵; 丁鹤群; 毕金琼
Original assignee: Beijing Suiyuan Intelligent Technology Co ltd
Current assignee: Beijing Suiyuan Intelligent Technology Co ltd
Priority date: 2023-05-17
Filing date: 2023-05-17
Publication date: 2023-07-28
Anticipated expiration: 2043-05-17
Also published as: CN116306400A

Abstract

The present invention relates to the field of electronic digital data processing technology, and in particular, to a method, a system, a device, equipment and a medium for verifying an integrated circuit. The method comprises the following steps: generating a transaction conversion component and an observation component corresponding to at least one interface to be tested; if the verification mode is an active mode, generating corresponding to-be-transferred transactions of each interface to be tested through the corresponding transaction conversion assembly and sending the to-be-transferred transactions to the verification assembly; the method comprises the steps that a to-be-transferred transaction corresponding to each interface to be tested is sent to each interface to be tested through a verification component, and a response transaction fed back is received; receiving to-be-transferred transactions corresponding to each to-be-tested interface sent by each to-be-tested interface through a verification component; determining protocol transactions corresponding to each interface to be tested according to the transactions to be transferred corresponding to each interface to be tested through the corresponding transaction conversion assembly; and displaying the circuit signals of each interface to be tested through the corresponding observation assembly. The embodiment of the invention can reduce the verification cost, shorten the verification period and improve the verification efficiency.

Description

Integrated circuit verification method, system, device, equipment and medium

Technical Field

The present invention relates to the field of electronic digital data processing technology, and in particular, to a method, a system, a device, equipment and a medium for verifying an integrated circuit.

Background

To accommodate various data transfers, a plurality of interfaces are provided in the integrated circuit for transferring data of a specified type. In the verification process of the integrated circuit, transaction transmission is required to be carried out with the interfaces to be tested according to the transmission data types and the interface communication protocols of the interfaces to be tested for each interface to be tested.

In the related art, the common integrated circuit verification scheme is: the tester writes a corresponding verification system for each interface to be tested of the integrated circuit. And generating a transaction to be transferred corresponding to the interface to be tested through the verification system, sending the transaction to be transferred to the interface to be tested, and receiving a response transaction fed back by the interface to be tested and the transaction to be transferred corresponding to the interface to be tested, which is sent by the interface to be tested. Or directly receiving the transaction to be transferred corresponding to the interface to be tested, which is sent by the interface to be tested, through the verification system. The transaction to be transferred corresponding to the interface to be tested is a data signal for carrying a protocol transaction corresponding to the interface to be tested based on a communication protocol used by the interface to be tested. The protocol transaction corresponding to the interface to be tested is the appointed type data which the interface to be tested needs to transmit according to the communication protocol used by the interface to be tested. The integrated circuit verification scheme in the related art requires a tester to write a corresponding verification system for each interface to be tested of the integrated circuit, and consumes a great deal of labor cost and time cost, so that the verification period of the integrated circuit is longer, and the verification efficiency is lower.

Disclosure of Invention

The invention provides an integrated circuit verification method, an integrated circuit verification system, an integrated circuit verification device and an integrated circuit verification medium, which are used for solving the problems that a tester needs to write a corresponding verification system for each interface to be tested of an integrated circuit, a large amount of labor cost and time cost are consumed, the verification period of the integrated circuit is long, and the verification efficiency is low in the related art.

According to an aspect of the present invention, there is provided an integrated circuit verification method including:

acquiring an interface specification of a tested circuit, and generating a transaction conversion assembly and an observation assembly corresponding to at least one interface to be tested of the tested circuit according to the interface specification of the tested circuit;

detecting a verification mode corresponding to the tested circuit;

if the verification mode corresponding to the tested circuit is detected to be an active mode, generating a transaction to be transferred corresponding to each interface to be tested according to a protocol transaction corresponding to each interface to be tested through a transaction conversion component corresponding to each interface to be tested, and sending the transaction to be transferred corresponding to each interface to be tested to the verification component;

the verification component is used for respectively sending the transaction to be transferred corresponding to each interface to be tested and receiving the response transaction fed back by each interface to be tested;

Receiving to-be-transferred transactions corresponding to the to-be-tested interfaces sent by the to-be-tested interfaces through the verification assembly, and sending to-be-transferred transactions corresponding to the to-be-tested interfaces sent by the to-be-tested interfaces to the transaction conversion assembly corresponding to the to-be-tested interfaces;

determining a protocol transaction corresponding to each interface to be tested according to the transaction to be transferred corresponding to each interface to be tested through a transaction conversion component corresponding to each interface to be tested;

and in the transaction transmission process between the verification component and each interface to be tested, displaying the circuit signals of each interface to be tested through the observation component corresponding to each interface to be tested.

Optionally, after detecting the verification mode corresponding to the tested circuit, the method further includes:

if the verification mode corresponding to the tested circuit is detected to be a passive mode, receiving to-be-transferred transactions corresponding to the interfaces to be tested, which are sent by the interfaces to be tested, through a verification component, and sending to-be-transferred transactions corresponding to the interfaces to be tested, which are sent by the interfaces to be tested, to a transaction conversion component corresponding to the interfaces to be tested;

According to another aspect of the present invention, there is provided an integrated circuit verification system comprising: the system comprises a tested circuit, a verification component, a transaction conversion component and an observation component, wherein the transaction conversion component and the observation component correspond to at least one interface to be tested of the tested circuit;

the transaction conversion assembly and the observation assembly corresponding to each interface to be tested are generated according to the interface specification of the tested circuit;

each transaction conversion component is used for generating a transaction to be transferred corresponding to each interface to be tested according to a protocol transaction corresponding to each interface to be tested when the verification mode corresponding to the tested circuit is an active mode, and sending the transaction to be transferred corresponding to each interface to be tested to the verification component; after receiving the transaction to be transferred corresponding to each interface to be tested sent by the verification component, determining a protocol transaction corresponding to each interface to be tested according to the transaction to be transferred corresponding to each interface to be tested;

the verification component is used for respectively sending the transaction to be transmitted corresponding to each interface to be tested and receiving the response transaction fed back by each interface to be tested when the verification mode corresponding to the tested circuit is an active mode; receiving to-be-transferred transactions corresponding to the to-be-transferred interfaces and sent by the to-be-transferred interfaces, and sending to-be-transferred transactions corresponding to the to-be-transferred interfaces and sent by the to-be-transferred interfaces to transaction conversion components corresponding to the to-be-transferred interfaces;

And each observation component is used for displaying the circuit signals of each interface to be tested in the transaction transmission process between the verification component and each interface to be tested.

According to another aspect of the present invention, there is provided an integrated circuit verification apparatus comprising:

the module generating module is used for acquiring an interface specification of the tested circuit and generating a transaction conversion module and an observation module corresponding to at least one interface to be tested of the tested circuit according to the interface specification of the tested circuit;

the mode detection module is used for detecting a verification mode corresponding to the tested circuit;

the transaction generating module is used for generating a transaction to be transferred corresponding to each interface to be tested according to a protocol transaction corresponding to each interface to be tested through the transaction conversion assembly corresponding to each interface to be tested if the verification mode corresponding to the tested circuit is detected to be an active mode, and sending the transaction to be transferred corresponding to each interface to be tested to the verification assembly;

the transaction sending module is used for respectively sending the transaction to be transferred corresponding to each interface to be tested through the verification component and receiving the response transaction fed back by each interface to be tested;

The transaction receiving module is used for receiving to-be-transferred transactions corresponding to the to-be-transferred interfaces and sent by the to-be-transferred interfaces through the verification assembly, and sending to-be-transferred transactions corresponding to the to-be-transferred interfaces and sent by the to-be-transferred interfaces to the transaction conversion assembly corresponding to the to-be-transferred interfaces;

the transaction determining module is used for determining protocol transactions corresponding to the interfaces to be tested according to the transactions to be transferred corresponding to the interfaces to be tested through transaction conversion components corresponding to the interfaces to be tested;

and the signal observation module is used for displaying the circuit signals of the interfaces to be tested through the observation assemblies corresponding to the interfaces to be tested in the transaction transmission process between the verification assemblies and the interfaces to be tested.

Optionally, the transaction receiving module is further configured to receive, through the verification component, a transaction to be transferred corresponding to each interface to be tested sent by each interface to be tested, and send the transaction to be transferred corresponding to each interface to be tested sent by each interface to be tested to the transaction conversion component corresponding to each interface to be tested, where the verification mode corresponding to the tested circuit is a passive mode; the transaction determining module is further configured to determine, by using a transaction conversion component corresponding to each interface to be tested, a protocol transaction corresponding to each interface to be tested according to a transaction to be transferred corresponding to each interface to be tested, where a verification mode corresponding to the tested circuit is a passive mode; and the signal observation module is also used for displaying the circuit signals of the interfaces to be tested through the observation assemblies corresponding to the interfaces to be tested in the transaction transmission process between the verification assemblies and the interfaces to be tested under the condition that the verification mode corresponding to the tested circuit is a passive mode.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor;

and a memory communicatively coupled to the at least one processor;

wherein the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the integrated circuit verification method of any one of the embodiments of the present invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute an integrated circuit verification method according to any one of the embodiments of the present invention.

According to the technical scheme, the transaction conversion assembly and the observation assembly corresponding to at least one interface to be tested of the tested circuit are generated according to the interface specification of the tested circuit by acquiring the interface specification of the tested circuit; then detecting a verification mode corresponding to the tested circuit; if the verification mode corresponding to the tested circuit is detected to be an active mode, generating a transaction to be transferred corresponding to each interface to be tested according to the protocol transaction corresponding to each interface to be tested through the transaction conversion assembly corresponding to each interface to be tested, and sending the transaction to be transferred corresponding to each interface to be tested to the verification assembly; the method comprises the steps that a verification component is used for respectively sending to-be-transferred transactions corresponding to each interface to be tested, and receiving response transactions fed back by each interface to be tested; receiving to-be-transferred transactions corresponding to the to-be-tested interfaces sent by the to-be-tested interfaces through the verification assembly, and sending to-be-transferred transactions corresponding to the to-be-tested interfaces sent by the to-be-tested interfaces to the transaction conversion assembly corresponding to the to-be-tested interfaces; determining a protocol transaction corresponding to each interface to be tested according to the transaction to be transferred corresponding to each interface to be tested through a transaction conversion component corresponding to each interface to be tested; in the transaction transfer process between the verification component and each interface to be tested, the observation component corresponding to each interface to be tested is used for displaying the circuit signals of each interface to be tested, so that the problems that in the related art, a test staff needs to write a corresponding verification system for each interface to be tested of the integrated circuit, a large amount of labor cost and time cost are consumed, the verification period of the integrated circuit is long, and the verification efficiency is relatively low are solved, the problem that the transaction transfer can be carried out with each interface to be tested through the automatically generated transaction conversion component corresponding to each interface to be tested, the automatically generated observation component corresponding to each interface to be tested and the preset verification component is solved, the verification system for carrying out transaction transfer with each interface to be tested of the integrated circuit to be tested can be formed, the response transaction corresponding to each interface to be tested can be generated, the mode of the transaction to be transferred corresponding to each interface to be tested of the integrated circuit to be tested is sent to each interface to be tested, the response transaction and the feedback of each interface to be tested is received, the transaction transfer with each interface to be tested is carried out with each interface to be tested, the user interface to be tested is convenient, the verification process of the integrated circuit to be tested is convenient, the cost of each interface to be tested is not required to be verified, and the cost of the integrated circuit to be tested is reduced, and the integrated circuit to be tested is required to be tested, the test process is not has the verification process is reduced.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of an integrated circuit verification method according to an embodiment of the invention.

Fig. 2 is a flowchart of an integrated circuit verification method according to a second embodiment of the present invention.

Fig. 3 is a schematic structural diagram of an integrated circuit verification system according to a third embodiment of the present invention.

Fig. 4 is a schematic structural diagram of an integrated circuit verification device according to a fourth embodiment of the present invention.

Fig. 5 is a schematic structural diagram of an electronic device implementing an integrated circuit verification method according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "object," "first," "second," and the like in the description and the claims of the present invention and the above drawings are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1 is a flowchart of an integrated circuit verification method according to an embodiment of the invention. The embodiment is applicable to the case of transaction transfer with each interface to be tested of an integrated circuit, and the method can be executed by an integrated circuit verification device which can be implemented in the form of hardware and/or software and can be configured in an electronic device. As shown in fig. 1, the method includes:

step 101, obtaining an interface specification of a tested circuit, and generating a transaction conversion assembly and an observation assembly corresponding to at least one interface to be tested of the tested circuit according to the interface specification of the tested circuit.

Optionally, the circuit under test is an integrated circuit that requires verification. At least one interface under test of the circuit under test is one or more interfaces in the circuit under test that need to be verified. Each interface to be tested is used for transmitting the data of the appointed type according to the appointed communication protocol.

Optionally, the interface specification of the circuit under test is a file for storing information related to the respective interfaces under test of the circuit under test. Information related to each interface under test of the circuit under test includes, but is not limited to: the method comprises the steps of identifying information of each interface to be tested, interface types of each interface to be tested, parameter names and parameter values of various parameters of a communication protocol used by each interface to be tested, and protocol transactions corresponding to each interface to be tested. The protocol transaction corresponding to the interface to be tested is the appointed type data which the interface to be tested needs to transmit according to the communication protocol used by the interface to be tested.

Optionally, the obtaining the interface specification of the tested circuit includes: and obtaining the interface specification of the tested circuit according to the interface specification template and the interface information input by the target user. The interface specification template is a template for generating an interface specification of the circuit under test. The interface specification template contains filling positions of information related to each interface to be tested of the tested circuit. The target user may be a tester responsible for managing the verification process of the circuit under test. The interface information input by the target user is information related to each interface to be tested of the tested circuit, which is filled in an interface specification template.

Optionally, obtaining the interface specification of the tested circuit according to the interface specification template and the interface information input by the target user, including: and providing the interface specification template for the target user through the verification management page, so that the target user fills in the information related to each interface to be tested of the tested circuit in the filling position of the information related to each interface to be tested of the tested circuit in the interface specification template, and the interface specification of the tested circuit is obtained. The verification management page is a page which is arranged in the electronic equipment and used for interacting with a user, providing information related to the verification process of the tested circuit for the user, or acquiring information related to the verification process of the tested circuit, which is input by the user. Providing the interface specification template to the target user through the verification management page, comprising: and displaying the interface specification template on the verification management page.

Optionally, the obtaining the interface specification of the tested circuit includes: and acquiring an interface specification of the tested circuit uploaded by the target user. The target user can upload the interface specification of the tested circuit to the electronic device through the terminal device, so that the electronic device obtains the interface specification of the tested circuit.

Optionally, the transaction conversion component corresponding to the interface to be tested is a component for generating a transaction to be transferred corresponding to the interface to be tested, and sending the transaction to be transferred corresponding to the interface to be tested to the verification component, or processing the transaction to be transferred corresponding to the interface to be tested, which is sent by the interface to be tested, and determining a protocol transaction corresponding to the interface to be tested according to the transaction to be transferred corresponding to the interface to be tested.

Optionally, the transaction to be transferred corresponding to the interface to be tested is a data signal for carrying a protocol transaction corresponding to the interface to be tested based on a communication protocol used by the interface to be tested. The protocol transaction corresponding to the interface to be tested is the appointed type data which the interface to be tested needs to transmit according to the communication protocol used by the interface to be tested.

Optionally, the transaction conversion component corresponding to the interface to be tested may generate the transaction to be transferred corresponding to the interface to be tested according to the protocol transaction corresponding to the interface to be tested. Generating a transaction to be transferred corresponding to the interface to be tested according to the protocol transaction corresponding to the interface to be tested, comprising: and converting the protocol transaction corresponding to the interface to be tested into the transaction to be transferred corresponding to the interface to be tested according to the communication protocol used by the interface to be tested.

Optionally, the transaction conversion component corresponding to the interface to be tested may further process a transaction to be transferred corresponding to the interface to be tested, where the transaction to be transferred is sent by the interface to be tested, and determine a protocol transaction corresponding to the interface to be tested according to the transaction to be transferred corresponding to the interface to be tested. Determining a protocol transaction corresponding to the interface to be tested according to the transaction to be transferred corresponding to the interface to be tested, including: and converting the transaction to be transferred corresponding to the interface to be tested into a protocol transaction corresponding to the interface to be tested according to the communication protocol used by the interface to be tested.

Optionally, the observation component corresponding to the interface to be tested is a component for displaying a circuit signal of the interface to be tested in a transaction transfer process between the verification component and the interface to be tested. The circuit signal of the interface to be tested can be a data signal received by the interface to be tested or a data signal sent by the interface to be tested. In the transaction transfer process between the verification component and the interface to be tested, displaying the circuit signal of the interface to be tested, comprising: acquiring a data signal sent to an interface to be tested by a verification component, generating a visual chart for displaying the data signal, and providing the visual chart for displaying the data signal to a target user through a verification management page; or, the data signal sent by the interface to be tested and received by the verification component is obtained, a visual chart for displaying the data signal is generated, and the visual chart for displaying the data signal is provided for the target user through the verification management page. Providing a visual chart for presenting the data signal to the target user through the authentication management page, comprising: a visual chart for presenting the data signal is displayed on the verification management page.

Optionally, the generating, according to the interface specification of the tested circuit, a transaction conversion component and an observation component corresponding to at least one interface to be tested of the tested circuit includes: generating a script through a transaction conversion assembly, and generating a transaction conversion assembly corresponding to each interface to be tested of the tested circuit according to an interface specification of the tested circuit; and generating a script through an observation component, and generating the observation component corresponding to each interface to be tested of the tested circuit according to the interface specification of the tested circuit.

Optionally, the transaction conversion component generation script is a script written by a tester for generating the transaction conversion component corresponding to the interface to be tested of each interface type. The transaction conversion component generation script may be constituted by transaction conversion component generation sub-scripts corresponding to respective interface types. The transaction conversion component generation sub-script corresponding to the interface type is a script for generating the transaction conversion component corresponding to the interface to be tested of the interface type. And running the transaction conversion component corresponding to the interface type to generate a sub-script so as to generate the transaction conversion component corresponding to the interface to be tested of the interface type. For example, the interface type of the interface to be tested may be a load query, a store query, a slave load, a slave store, a host load, or a host store.

Optionally, generating, by the transaction conversion component, a script, and generating, according to an interface specification of the tested circuit, a transaction conversion component corresponding to each interface to be tested of the tested circuit, including: the following operations are executed for each interface to be tested of the tested circuit: extracting the interface type of the interface to be tested from the interface specification of the tested circuit; and running a transaction conversion component corresponding to the interface type to generate a sub-script, and generating a transaction conversion component corresponding to the interface to be tested.

Optionally, the observation component generation script is a script written by a tester for generating an observation component corresponding to the interface to be tested of each interface type. The observation component generation script may be constituted by observation component generation sub-scripts corresponding to respective interface types. The observation component generation sub-script corresponding to the interface type is a script for generating an observation component corresponding to an interface to be tested of the interface type. And running an observation component generation sub-script corresponding to the interface type to generate an observation component corresponding to the interface to be tested of the interface type.

Optionally, generating, by the observation component, a script, and generating, according to an interface specification of the tested circuit, an observation component corresponding to each interface to be tested of the tested circuit, including: the following operations are executed for each interface to be tested of the tested circuit: extracting the interface type of the interface to be tested from the interface specification of the tested circuit; and running an observation component corresponding to the interface type to generate a sub-script, and generating an observation component corresponding to the interface to be tested.

Step 102, detecting a verification mode corresponding to the tested circuit.

Optionally, the verification mode corresponding to the tested circuit is an active mode or a passive mode. The verification mode corresponding to the tested circuit is an active mode, which indicates that in the verification process of the tested circuit, a transaction to be transferred corresponding to the interface to be tested needs to be generated, the transaction to be transferred is sent to the interface to be tested, and a response transaction fed back by the interface to be tested and the transaction to be transferred corresponding to the interface to be tested, which are sent by the interface to be tested, are received. The verification mode corresponding to the tested circuit is a passive mode, which indicates that in the verification process of the tested circuit, the transaction to be transferred corresponding to the interface to be tested, which is sent by the interface to be tested, needs to be received.

Optionally, detecting a verification mode corresponding to the tested circuit includes: and reading the verification mode corresponding to the tested circuit from the verification configuration file of the tested circuit. The verification profile of the circuit under test is a file set in the electronic device for storing information related to the verification process of the circuit under test. The verification configuration file contains a verification mode corresponding to the tested circuit. The target user can upload the verification configuration file of the tested circuit to the electronic device through the terminal device.

Step 103, if the verification mode corresponding to the tested circuit is detected to be an active mode, generating a transaction to be transferred corresponding to each interface to be tested according to a protocol transaction corresponding to each interface to be tested through a transaction conversion component corresponding to each interface to be tested, and sending the transaction to be transferred corresponding to each interface to be tested to the verification component.

Optionally, if the verification mode corresponding to the tested circuit is detected to be an active mode, which indicates that in the verification process of the tested circuit, a transaction to be transferred corresponding to an interface to be tested needs to be generated, the transaction to be transferred is sent to the interface to be tested, a response transaction fed back by the interface to be tested and the transaction to be transferred corresponding to the interface to be tested sent by the interface to be tested are received, then the transaction to be transferred corresponding to the interface to be tested is generated by the transaction conversion component corresponding to the interface to be tested according to the protocol transaction corresponding to the interface to be tested, the transaction to be transferred corresponding to the interface to be tested is sent to the verification component, the transaction to be transferred corresponding to the interface to be tested is sent to the interface to be tested by the verification component, the response transaction fed back by the interface to be tested is received by the verification component, and then the transaction to be transferred corresponding to the interface to be tested is received by the verification component, so that the transaction to be transferred to each interface to be tested of the integrated circuit is respectively carried out.

Optionally, generating, by the transaction conversion component corresponding to each interface to be tested, a transaction to be transferred corresponding to each interface to be tested according to a protocol transaction corresponding to each interface to be tested, and sending the transaction to be transferred corresponding to each interface to be tested to the verification component, including: executing the following operations through the transaction conversion components corresponding to each interface to be tested: according to a communication protocol used by the interface to be tested, converting a protocol transaction corresponding to the interface to be tested into a transaction to be transferred corresponding to the interface to be tested; and sending the transaction to be transferred corresponding to the interface to be tested to the verification component.

Step 104, the verification component sends the transaction to be transferred corresponding to each interface to be tested, and receives the response transaction fed back by each interface to be tested.

Optionally, the verification component is a component for transmitting data signals to an interface of the integrated circuit or receiving data signals transmitted by an interface of the integrated circuit based on a communication connection with the interface of the integrated circuit. The verification component includes a plurality of interfaces. The respective interfaces may establish a communication connection with the interfaces of the integrated circuit based on a communication protocol used by the interfaces of the integrated circuit.

Optionally, the configuration component is a component written by a tester and used for configuring the verification component according to an interface specification of the tested circuit, and establishing communication connection between an interface of the verification component and each interface to be tested of the tested circuit.

Optionally, before detecting the verification mode corresponding to the tested circuit, the method further includes: and configuring the verification component according to the interface specification of the tested circuit by the configuration component, wherein the configuration component comprises the following steps: the following operations are performed by the configuration component: determining a communication protocol used by each interface to be tested according to information related to each interface to be tested of the tested circuit in an interface specification of the tested circuit; distributing an interface of a verification component for each interface to be tested; and establishing communication connection between the interfaces to be tested and the interfaces in the distributed verification assembly according to the communication protocol used by the interfaces to be tested for each interface to be tested.

Optionally, the verifying component sends the transaction to be transferred corresponding to each interface to be tested, and receives the response transaction fed back by each interface to be tested, including: the following operations are executed for each interface to be tested through the verification component: after receiving a transaction to be transferred corresponding to the interface to be tested, which is sent by a transaction conversion component corresponding to the interface to be tested, sending the transaction to be transferred corresponding to the interface to be tested through an interface of a verification component matched with the interface to be tested based on communication connection between the interface to be tested and the interface to be tested; and receiving a response transaction fed back by the interface to be tested through an interface of the verification component matched with the interface to be tested. The response transaction is that the interface to be tested feeds back the data signal of the sender of the transaction to be transferred corresponding to the interface to be tested after receiving the transaction to be transferred corresponding to the interface to be tested.

Step 105, receiving, by the verification component, a transaction to be transferred corresponding to each interface to be tested, where the transaction to be transferred is sent by each interface to be tested, and sending the transaction to be transferred corresponding to each interface to be tested, where the transaction to be transferred is sent by each interface to be tested, to the transaction conversion component corresponding to each interface to be tested.

And 106, determining protocol transactions corresponding to the interfaces to be tested according to the transactions to be transferred corresponding to the interfaces to be tested through transaction conversion components corresponding to the interfaces to be tested.

Step 107, in the transaction transmission process between the verification component and each interface to be tested, displaying the circuit signals of each interface to be tested through the observation component corresponding to each interface to be tested.

Optionally, in a transaction transfer process between the verification component and each interface to be tested, displaying, by using an observation component corresponding to each interface to be tested, a circuit signal of each interface to be tested, including: the following operations are executed through the observation components corresponding to each interface to be tested: acquiring a data signal sent to the interface to be tested through an interface of the verification component matched with the interface to be tested from the verification component, generating a visual chart for displaying the data signal, and providing the visual chart for displaying the data signal to a target user through a verification management page; and acquiring the data signals transmitted by the interface to be tested and received by the interface of the verification component matched with the interface to be tested from the verification component, generating a visual chart for displaying the data signals, and providing the visual chart for displaying the data signals to a target user through a verification management page.

In the process of generating the transaction to be transferred corresponding to each interface to be tested, sending the transaction to be transferred to each interface to be tested, receiving the response transaction fed back by each interface to be tested, and conducting transaction transfer with each interface to be tested of the tested circuit, displaying the circuit signals of each interface to be tested through the observation component corresponding to each interface to be tested, and facilitating a target user to observe the process of conducting transaction transfer with each interface to be tested of the integrated circuit according to the circuit signals of each interface to be tested of the tested circuit.

Optionally, after detecting the verification mode corresponding to the tested circuit, the method further includes: if the verification mode corresponding to the tested circuit is detected to be a passive mode, receiving to-be-transferred transactions corresponding to the interfaces to be tested, which are sent by the interfaces to be tested, through a verification component, and sending to-be-transferred transactions corresponding to the interfaces to be tested, which are sent by the interfaces to be tested, to a transaction conversion component corresponding to the interfaces to be tested; determining a protocol transaction corresponding to each interface to be tested according to the transaction to be transferred corresponding to each interface to be tested through a transaction conversion component corresponding to each interface to be tested; and in the transaction transmission process between the verification component and each interface to be tested, displaying the circuit signals of each interface to be tested through the observation component corresponding to each interface to be tested.

Optionally, if the verification mode corresponding to the tested circuit is detected to be a passive mode, which indicates that in the verification process of the tested circuit, a transaction to be transferred corresponding to the interface to be tested sent by the interface to be tested needs to be received, and then the transaction to be transferred corresponding to the interface to be tested sent by each interface to be tested is received through the verification component, so that transaction transfer is performed with each interface to be tested of the integrated circuit respectively.

Optionally, the receiving, by the verification component, the transaction to be transferred corresponding to each interface to be tested sent by each interface to be tested, and sending, by each interface to be tested, the transaction to be transferred corresponding to each interface to be tested to the transaction conversion component corresponding to each interface to be tested, where the transaction conversion component includes: the following operations are executed for each interface to be tested through the verification component: receiving a transaction to be transferred corresponding to the interface to be tested, which is sent by the interface to be tested, through an interface of a verification component matched with the interface to be tested; and transmitting the transaction to be transferred, which is transmitted by the interface to be tested and corresponds to the interface to be tested, to the transaction conversion component corresponding to the interface to be tested.

Optionally, determining, by the transaction conversion component corresponding to each interface to be tested, a protocol transaction corresponding to each interface to be tested according to a transaction to be transferred corresponding to each interface to be tested, including: executing the following operations through the transaction conversion components corresponding to each interface to be tested: after receiving the transaction to be transferred corresponding to the interface to be tested, which is sent by the verification component, the transaction to be transferred corresponding to the interface to be tested is converted into a protocol transaction corresponding to the interface to be tested according to a communication protocol used by the interface to be tested.

Optionally, in a transaction transfer process between the verification component and each interface to be tested, displaying, by using an observation component corresponding to each interface to be tested, a circuit signal of each interface to be tested, including: the following operations are executed through the observation components corresponding to each interface to be tested: and acquiring the data signals transmitted by the interface to be tested and received by the interface of the verification component matched with the interface to be tested from the verification component, generating a visual chart for displaying the data signals, and providing the visual chart for displaying the data signals to a target user through a verification management page.

According to the technical scheme, the transaction conversion assembly and the observation assembly corresponding to at least one interface to be tested of the tested circuit are generated according to the interface specification of the tested circuit by acquiring the interface specification of the tested circuit; then detecting a verification mode corresponding to the tested circuit; if the verification mode corresponding to the tested circuit is detected to be an active mode, generating a transaction to be transferred corresponding to each interface to be tested according to the protocol transaction corresponding to each interface to be tested through the transaction conversion assembly corresponding to each interface to be tested, and sending the transaction to be transferred corresponding to each interface to be tested to the verification assembly; the method comprises the steps that a verification component is used for respectively sending to-be-transferred transactions corresponding to each interface to be tested, and receiving response transactions fed back by each interface to be tested; receiving to-be-transferred transactions corresponding to the to-be-tested interfaces sent by the to-be-tested interfaces through the verification assembly, and sending to-be-transferred transactions corresponding to the to-be-tested interfaces sent by the to-be-tested interfaces to the transaction conversion assembly corresponding to the to-be-tested interfaces; determining a protocol transaction corresponding to each interface to be tested according to the transaction to be transferred corresponding to each interface to be tested through a transaction conversion component corresponding to each interface to be tested; in the transaction transfer process between the verification component and each interface to be tested, the observation component corresponding to each interface to be tested is used for displaying the circuit signals of each interface to be tested, thus solving the problems that in the related art, an integrated circuit verification scheme needs a tester to write a corresponding verification system for each interface to be tested of an integrated circuit, a great deal of labor cost and time cost are consumed, the verification period of the integrated circuit is longer, and the verification efficiency is lower, the problem that the transaction transfer can be carried out with each interface to be tested of the integrated circuit is obtained through the automatically generated transaction conversion component corresponding to each interface to be tested, the automatically generated observation component corresponding to each interface to be tested and the preset verification component form an integrated circuit verification system for carrying out transaction transfer with each interface to be tested of the integrated circuit to be tested respectively, the cost of the integrated circuit to be tested can be reduced by generating the transaction to be transferred corresponding to each interface to be tested, the response transaction corresponding to each interface to be tested is sent to each interface to be tested, the mode of the transaction to be tested and the interface to be tested is required to be tested is received, the cost of the integrated circuit to be tested is not to be tested by the integrated circuit to be tested is required to be tested by a tester, and the system to be tested is not written for the time for the integrated circuit to be verified by the corresponding to be tested to the interface to be tested, in the time to be tested to be written to be required for the integrated circuit to be tested, in the time is not required for the verification system to be written for the corresponding to be verified to be written for the corresponding to the integrated circuit to be tested to be required for each corresponding to be tested to be written during a corresponding to be tested to test, the verification efficiency is improved.

Example two

Fig. 2 is a flowchart of an integrated circuit verification method according to a second embodiment of the present invention. Embodiments of the invention may be combined with various alternatives to one or more of the embodiments described above. As shown in fig. 2, the method includes:

step 201, an interface specification of a tested circuit is obtained, and a transaction conversion component and an observation component corresponding to at least one interface to be tested of the tested circuit are generated according to the interface specification of the tested circuit.

Step 202, detecting a verification mode corresponding to the tested circuit.

Step 203, if the verification mode corresponding to the tested circuit is detected to be a passive mode, receiving, by the verification component, a transaction to be transferred corresponding to each interface to be tested, which is sent by each interface to be tested, and sending the transaction to be transferred corresponding to each interface to be tested, which is sent by each interface to be tested, to the transaction conversion component corresponding to each interface to be tested.

Step 204, determining, by the transaction conversion component corresponding to each interface to be tested, a protocol transaction corresponding to each interface to be tested according to the transaction to be transferred corresponding to each interface to be tested.

Step 205, in a transaction transmission process between the verification component and each interface to be tested, displaying a circuit signal of each interface to be tested through an observation component corresponding to each interface to be tested.

According to the technical scheme, the integrated circuit verification system for carrying out transaction transfer with each interface to be tested of the tested circuit can be formed by the automatically generated transaction conversion assembly corresponding to each interface to be tested, the automatically generated observation assembly corresponding to each interface to be tested and the preset verification assembly, the integrated circuit verification system is used for carrying out transaction transfer with each interface to be tested of the tested circuit respectively, transaction transfer can be carried out with each interface to be tested of the tested circuit respectively through the mode of receiving the transaction to be transferred, which is sent by each interface to be tested, of the interfaces to be tested, circuit signals of each interface to be tested can be displayed in the transaction transfer process, and a target user can observe the process of carrying out transaction transfer with each interface to be tested of the tested circuit conveniently.

Example III

Fig. 3 is a schematic structural diagram of an integrated circuit verification system according to a third embodiment of the present invention. The embodiment can be applied to the situation that transaction transmission is carried out with each interface to be tested of the integrated circuit respectively, and relevant data in the transaction transmission process is obtained. As shown in fig. 3, the integrated circuit verification system may specifically include: the structure and function of the circuit under test 301, the verification component 302, and the transaction conversion component 303 and the observation component 304 corresponding to at least one interface under test of the circuit under test 301 are described below.

The transaction conversion component 303 and the observation component 304 corresponding to each interface to be tested are generated according to the interface specification of the tested circuit 301.

Each transaction conversion component 303 is configured to generate a transaction to be transferred corresponding to each interface to be tested according to a protocol transaction corresponding to each interface to be tested when the verification mode corresponding to the tested circuit 301 is an active mode, and send the transaction to be transferred corresponding to each interface to be tested to the verification component 302; after receiving the transaction to be transferred corresponding to each interface to be tested sent by the verification component 302, determining a protocol transaction corresponding to each interface to be tested according to the transaction to be transferred corresponding to each interface to be tested.

The verification component 302 is configured to send a transaction to be transferred corresponding to each interface to be tested when a verification mode corresponding to the tested circuit is an active mode, and receive a response transaction fed back by each interface to be tested; and receiving the transaction to be transferred corresponding to each interface to be tested, which is sent by each interface to be tested, and sending the transaction to be transferred corresponding to each interface to be tested, which is sent by each interface to be tested, to the transaction conversion component 303 corresponding to each interface to be tested.

Each observation component 304 is configured to display a circuit signal of each interface to be tested in a transaction transmission process between the verification component 302 and each interface to be tested.

Optionally, the verification component 302 may be further configured to present the circuit signals of each interface under test during a transaction between the verification component 302 and each interface under test. The verification component 302 may classify the circuit signals of the interfaces to be tested according to the corresponding transactions to be transferred, and display the classification result.

Optionally, each observation component 304 may classify the circuit signals of each interface to be tested according to the corresponding protocol transaction, and display the classification result.

Optionally, the verification component 302 is further configured to receive a transaction to be transferred corresponding to each interface to be tested sent by each interface to be tested when the verification mode corresponding to the tested circuit 301 is a passive mode, and send the transaction to be transferred corresponding to each interface to be tested sent by each interface to be tested to the transaction conversion component 303 corresponding to each interface to be tested; each transaction conversion component 303 is further configured to determine a protocol transaction corresponding to each interface to be tested according to the transaction to be transferred corresponding to each interface to be tested.

According to the technical scheme, the integrated circuit verification system for carrying out transaction transfer with each interface to be tested of the integrated circuit can be formed by the automatically generated transaction conversion assembly corresponding to each interface to be tested, the automatically generated observation assembly corresponding to each interface to be tested and the preset verification assembly, the transaction to be transferred corresponding to each interface to be tested can be sent to each interface to be tested by generating the transaction to be transferred corresponding to each interface to be tested, the response transaction fed back by each interface to be tested and the mode of the transaction to be transferred corresponding to the interface to be tested, which are sent by each interface to be tested, are respectively carried out transaction transfer with each interface to be tested of the circuit to be tested, a tester is not required to write a corresponding verification system for each interface to be tested of the integrated circuit, the labor cost and the time cost of the integrated circuit verification process are reduced, the verification period of the integrated circuit is shortened, and the verification efficiency is improved.

Example IV

Fig. 4 is a schematic structural diagram of an integrated circuit verification device according to a fourth embodiment of the present invention. The apparatus may be configured in an electronic device. As shown in fig. 4, the apparatus includes: component generation module 401, pattern detection module 402, transaction generation module 403, transaction transmission module 404, transaction reception module 405, transaction determination module 406, and signal observation module 407.

The component generating module 401 is configured to obtain an interface specification of a tested circuit, and generate a transaction conversion component and an observation component corresponding to at least one interface to be tested of the tested circuit according to the interface specification of the tested circuit; a mode detection module 402, configured to detect a verification mode corresponding to the circuit under test; the transaction generating module 403 is configured to generate, by using the transaction conversion component corresponding to each interface to be tested according to the protocol transaction corresponding to each interface to be tested, a transaction to be transferred corresponding to each interface to be tested, and send the transaction to be transferred corresponding to each interface to be tested to the verification component if the verification mode corresponding to the tested circuit is detected to be an active mode; the transaction sending module 404 is configured to send, through the verification component, a transaction to be transferred corresponding to each interface to be tested, and receive a response transaction fed back by each interface to be tested; the transaction receiving module 405 is configured to receive, by using the verification component, a transaction to be transferred corresponding to each interface to be tested, where the transaction to be transferred is sent by each interface to be tested, and sends the transaction to be transferred corresponding to each interface to be tested, where the transaction to be transferred is sent by each interface to be tested, to the transaction conversion component corresponding to each interface to be tested; the transaction determining module 406 is configured to determine, by using a transaction conversion component corresponding to each interface to be tested, a protocol transaction corresponding to each interface to be tested according to a transaction to be transferred corresponding to each interface to be tested; the signal observation module 407 is configured to display, during a transaction transfer process between the verification component and each interface to be tested, a circuit signal of each interface to be tested through an observation component corresponding to each interface to be tested.

In an optional implementation manner of the embodiment of the present invention, optionally, the transaction receiving module 405 is further configured to receive, by using a verification component, a transaction to be transferred corresponding to each interface to be tested, where the verification mode corresponding to the circuit to be tested is a passive mode, and send the transaction to be transferred corresponding to each interface to be tested, where the transaction to be transferred is sent by each interface to be tested, to a transaction conversion component corresponding to each interface to be tested; the transaction determining module 406 is further configured to determine, by using a transaction conversion component corresponding to each interface to be tested, a protocol transaction corresponding to each interface to be tested according to a transaction to be transferred corresponding to each interface to be tested, where a verification mode corresponding to the tested circuit is a passive mode; the signal observation module 407 is further configured to display, when the verification mode corresponding to the tested circuit is a passive mode, a circuit signal of each interface to be tested through an observation component corresponding to each interface to be tested in a transaction transfer process between the verification component and each interface to be tested.

In an optional implementation manner of the embodiment of the present invention, optionally, the component generating module 401 is specifically configured to, when performing an operation of acquiring an interface specification of a circuit under test: and obtaining the interface specification of the tested circuit according to the interface specification template and the interface information input by the target user.

In an optional implementation manner of the embodiment of the present invention, optionally, when the component generating module 401 generates, according to an interface specification of the tested circuit, an operation of a transaction conversion component and an observation component corresponding to at least one interface to be tested of the tested circuit, the method is specifically used for: generating a script through a transaction conversion assembly, and generating a transaction conversion assembly corresponding to each interface to be tested of the tested circuit according to an interface specification of the tested circuit; and generating a script through an observation component, and generating the observation component corresponding to each interface to be tested of the tested circuit according to the interface specification of the tested circuit.

In an optional implementation manner of the embodiment of the present invention, optionally, the integrated circuit verification apparatus further includes: and the component configuration module is used for configuring the verification component according to the interface specification of the tested circuit by configuring the component.

The specific manner in which the various modules perform the operations in the apparatus of the above embodiments have been described in detail in connection with the embodiments of the method, and will not be described in detail herein.

The integrated circuit verification device can execute the integrated circuit verification method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of executing the integrated circuit verification method.

Example five

Fig. 5 shows a schematic diagram of the architecture of an electronic device 10 that may be used to implement the integrated circuit verification method of an embodiment of the present invention. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 5, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program built into the Random Access Memory (RAM) 13 from the storage unit 18. In the RAM 13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as integrated circuit verification methods.

In some embodiments, the integrated circuit verification method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. One or more of the steps of the integrated circuit verification method described above may be performed when a computer program is built into RAM 13 and executed by processor 11. Alternatively, in other embodiments, processor 11 may be configured to perform the integrated circuit verification method in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for implementing the integrated circuit verification method of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. An integrated circuit verification method, comprising:

detecting a verification mode corresponding to the tested circuit;

2. The integrated circuit verification method according to claim 1, further comprising, after detecting a verification pattern corresponding to the circuit under test:

3. The method of claim 1, wherein the obtaining an interface specification of the circuit under test comprises:

and obtaining the interface specification of the tested circuit according to the interface specification template and the interface information input by the target user.

4. The method of claim 1, wherein generating a transaction conversion component and an observation component corresponding to at least one interface under test of the circuit under test according to the interface specification of the circuit under test comprises:

generating a script through a transaction conversion assembly, and generating a transaction conversion assembly corresponding to each interface to be tested of the tested circuit according to an interface specification of the tested circuit;

and generating a script through an observation component, and generating the observation component corresponding to each interface to be tested of the tested circuit according to the interface specification of the tested circuit.

5. The integrated circuit verification method according to claim 1, further comprising, prior to detecting a verification pattern corresponding to the circuit under test:

and configuring the verification component through the configuration component according to the interface specification of the tested circuit.

6. An integrated circuit verification system, comprising: the system comprises a tested circuit, a verification component, a transaction conversion component and an observation component, wherein the transaction conversion component and the observation component correspond to at least one interface to be tested of the tested circuit;

7. The integrated circuit verification system according to claim 6, wherein the verification component is further configured to receive a transaction to be transferred corresponding to each interface to be tested sent by each interface to be tested when a verification mode corresponding to the circuit to be tested is a passive mode, and send the transaction to be transferred corresponding to each interface to be tested sent by each interface to be tested to the transaction conversion component corresponding to each interface to be tested;

And each transaction conversion component is further used for determining the protocol transaction corresponding to each interface to be tested according to the transaction to be transferred corresponding to each interface to be tested.

8. An integrated circuit verification device, comprising:

9. An electronic device, the electronic device comprising:

at least one processor;

and a memory communicatively coupled to the at least one processor network;

wherein the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the integrated circuit verification method of any one of claims 1-5.

10. A computer readable storage medium storing computer instructions for causing a processor to perform the integrated circuit verification method of any one of claims 1-5.