WO2026001070A1 - 半导体器件的终端结构及其制造方法、半导体器件、功率模块、电力电子器件和车辆 - Google Patents

半导体器件的终端结构及其制造方法、半导体器件、功率模块、电力电子器件和车辆

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Publication number
WO2026001070A1
WO2026001070A1 PCT/CN2025/081061 CN2025081061W WO2026001070A1 WO 2026001070 A1 WO2026001070 A1 WO 2026001070A1 CN 2025081061 W CN2025081061 W CN 2025081061W WO 2026001070 A1 WO2026001070 A1 WO 2026001070A1
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WIPO (PCT)
Prior art keywords
region
substrate
semiconductor device
oxide layer
away
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Pending
Application number
PCT/CN2025/081061
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English (en)
French (fr)
Inventor
赵心愿
秦博
吴海平
陈刚
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BYD Co Ltd
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BYD Co Ltd
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Publication of WO2026001070A1 publication Critical patent/WO2026001070A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers

Definitions

  • This application relates to the field of power device technology, and in particular to a terminal structure of a semiconductor device and its manufacturing method, a semiconductor device, a power module, a power electronic device, and a vehicle.
  • the PN junction in the active region which bears the voltage, approximates a planar junction and can withstand high voltages.
  • the voltage of the PN junction decreases due to the electric field concentration effect, severely limiting the voltage withstand capability of power devices. Therefore, to improve the maximum voltage withstand capability of power devices, a termination structure needs to be added to the edge of the active region to alleviate the electric field concentration effect.
  • Existing termination technologies such as field ring and field plate terminations, typically utilize field ring voltage division to allow the voltage to drop over a longer distance to withstand high voltages.
  • the first objective of this application is to propose a termination structure for a semiconductor device that can improve surface doping and surface electric field distribution, reduce electric field peak and leakage current, improve the efficiency of the termination structure, and thus maintain high breakdown voltage with a smaller termination structure size.
  • the second objective of this application is to provide a semiconductor device.
  • the third objective of this application is to propose a power module.
  • the fourth objective of this application is to provide a power electronic device.
  • the fifth objective of this application is to propose a vehicle.
  • the sixth objective of this application is to provide a method for manufacturing a terminal structure for semiconductor devices.
  • the first aspect of this application provides a semiconductor device termination structure comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type located on the substrate in a first direction; and a field-limiting ring structure located in the epitaxial layer in the first direction, the field-limiting ring structure surrounding an active region, the field-limiting ring structure including a first well region of a second conductivity type, the first well region having a plurality of doped regions of the first conductivity type, the plurality of doped regions of the first conductivity type being spaced apart along a second direction perpendicular to the first direction.
  • a first well region of the second conductivity type is combined with multiple doped regions of the first conductivity type in the epitaxial layer of the field-limiting ring structure.
  • This is equivalent to introducing alternating pillars of different conductivity types with different doping concentrations.
  • the pillars of different conductivity types can be well depleted in the blocking state, thereby improving the surface doping and surface electric field distribution, reducing electric field peak and leakage current, improving the efficiency of the termination structure, and effectively reducing the size of the termination structure.
  • This allows for higher breakdown voltage at the same termination structure size.
  • a smaller termination structure can reserve more space for the active region of the chip and reduce the proportion of chip area occupied by the termination structure.
  • the first well region can offset part of the electric field of the epitaxial layer, thereby reducing the influence of epitaxial layer doping on the charge balance of the charge compensation region and further improving the breakdown voltage of the terminal structure.
  • the plurality of doped regions of the first conductivity type are respectively ring-shaped doped regions surrounding the entire active region.
  • each doped region of the first conductivity type is disposed around the active region, and each doped region of the first conductivity type includes a plurality of sub-doped regions of the first conductivity type disposed at intervals from each other.
  • the first conductivity type sub-doped region is a cylindrical sub-doped region of the first conductivity type.
  • the distance between adjacent doped regions of the plurality of doped regions of the first conductivity type is equal; or in the second direction, the distance between adjacent doped regions of the plurality of doped regions of the first conductivity type gradually increases in the direction away from the active region; or in the second direction, the distance between adjacent doped regions of the plurality of doped regions of the first conductivity type gradually decreases in the direction away from the active region.
  • the field limiting ring structure further includes: a second well region of a second conductivity type, the second well region being located in the epitaxial layer in the first direction, the second well region being located on the side of the first well region closer to the active region, and the second well region being connected to the first well region.
  • the second well region serves as a main junction, providing a current extraction location for the terminal and a placement location for the gate of the power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the field limiting ring structure further includes a cutoff ring region, which is located at the end of the epitaxial layer away from the active region in the second direction and is spaced apart from the first well region.
  • the first well region, the second well region, each of the doped regions, and the cutoff ring region extend from their surfaces away from the substrate into the epitaxial layer in a direction close to the substrate.
  • the terminal structure of the semiconductor device further includes an oxide layer located on the side of the first well region, the second well region, the plurality of doped regions and the cutoff ring region away from the substrate in the first direction, and covering a portion of the first well region, the second well region, the plurality of doped regions and a portion of the cutoff ring region.
  • the terminal structure of the semiconductor device further includes a gate, the gate comprising a first gate portion and a second gate portion connected to each other, the first gate portion being located on the side of the oxide layer away from the substrate in the first direction.
  • the terminal structure of the semiconductor device further includes: a plurality of polycrystalline field plates, wherein the plurality of polycrystalline field plates are located on the side of the oxide layer away from the substrate in the first direction, and the plurality of polycrystalline field plates are spaced apart from and from the second gate in the second direction.
  • the oxide layer includes: a first oxide layer, which is located on the side of the first well region, the plurality of doped regions and the cutoff ring region away from the substrate in the first direction and extends continuously along the second direction; the first oxide layer has a second gate portion and the plurality of polycrystalline field plates on the side of the first oxide layer away from the substrate in the first direction; and the first oxide layer covers the first well region, the plurality of doped regions and a portion of the cutoff ring region.
  • the oxide layer further includes a second oxide layer connected to the first oxide layer.
  • the second oxide layer is located on the side of the second well region away from the substrate in the first direction and is located between the second well region and the first gate portion.
  • the thickness of the first oxide layer is greater than the thickness of the second oxide layer.
  • the terminal structure of the semiconductor device further includes a protective layer located on the side of the field limiting ring structure away from the substrate in the first direction.
  • the protective layer includes a third oxide layer, which is located on the side of the second well region, the gate, the first oxide layer, the plurality of polycrystalline field plates, and the cutoff ring region away from the substrate in the first direction and extends continuously along the second direction to cover a portion of the second well region, the gate, the first oxide layer, the plurality of polycrystalline field plates, and a portion of the cutoff ring region.
  • the protective layer further includes an active region metal, which comprises a first active region metal portion and a second active region metal portion.
  • the first active region metal portion and the second active region metal portion are connected.
  • the first active region metal portion is located on the side of the second well region away from the substrate in the first direction
  • the second active region metal portion is located on the side of the third oxide layer away from the substrate in the first direction.
  • the second active region metal portion serves as a metal field plate, which reduces the electric field at the main junction, i.e., the second well region.
  • the termination structure of the semiconductor device further includes: a stop ring metal, the stop ring metal including a first stop ring metal portion and a second stop ring metal portion, the first stop ring metal portion being connected to the second stop ring metal portion, the first stop ring metal portion being located on the side of the third oxide layer away from the substrate in the first direction, the first stop ring metal portion being spaced apart from the second active region metal portion in the second direction, the second stop ring metal portion being located on the side of the stop ring region away from the substrate in the first direction, and the side of the second stop ring metal portion away from the active region being flush with the side of the stop ring region away from the active region.
  • a semiconductor device includes: an active region; and a termination structure of the semiconductor device according to any one of the above embodiments, wherein the termination structure of the semiconductor device is disposed around the active region.
  • the semiconductor device proposed in the embodiments of this application by employing the termination structure of the semiconductor device of the above embodiment surrounding the active region, it is possible to improve surface doping and surface electric field distribution, and also reduce electric field peak and leakage current, thereby improving the efficiency of the semiconductor device.
  • the overall size of the formed termination structure is relatively small, thereby achieving higher breakdown voltage with the same termination structure size.
  • the small-sized termination structure can reserve more space for the active region of the chip, reducing the proportion of chip area occupied by the termination structure.
  • a third aspect of this application provides a power module including the semiconductor device described in the second aspect of the above embodiment.
  • the power module proposed according to the embodiments of this application includes the semiconductor device of the above embodiment.
  • the efficiency and voltage resistance of the semiconductor device are improved, thereby improving the efficiency and voltage resistance of the power module.
  • a fourth aspect of this application provides a power electronic device including the power module described in the third aspect of the above embodiment.
  • the power electronic device proposed in the embodiments of this application by adopting the power module of the above embodiment, can improve the efficiency and withstand voltage of the power module by improving the efficiency of the semiconductor device, thereby effectively improving the efficiency and performance of the power electronic device.
  • a fifth aspect of this application provides a vehicle including the semiconductor device described in the above embodiments.
  • the vehicle proposed in the embodiments of this application by employing the semiconductor devices of the above embodiments, can improve the performance of the entire vehicle and the withstand voltage of the circuit structure in the vehicle by improving the efficiency of the semiconductor devices, thereby improving the safety of the vehicle.
  • a sixth aspect of this application provides a method for manufacturing a terminal structure for a semiconductor device, comprising: forming an epitaxial layer of a first conductivity type on a substrate of a first conductivity type, the epitaxial layer being located on the substrate in a first direction; forming a field-limiting ring structure surrounding an active region in a region of the epitaxial layer away from the substrate, comprising: forming a first well region of a second conductivity type in the region of the epitaxial layer away from the substrate; and forming a plurality of doped regions of the first conductivity type spaced apart in the first well region along a second direction perpendicular to the first direction.
  • a method for manufacturing a terminal structure for a semiconductor device by preparing a combination of a first well region of a second conductivity type and multiple doped regions of the first conductivity type in a field-limiting ring structure, it is equivalent to introducing alternating pillars of different conductivity types with different doping concentrations.
  • the pillars of different conductivity types can be well depleted, thereby improving surface doping and surface electric field distribution, reducing electric field peak and leakage current, improving the efficiency of the terminal structure, and effectively reducing the size of the terminal structure. This allows for higher breakdown voltage at the same terminal structure size.
  • a smaller terminal structure can reserve more space for the active region of the chip, reducing the proportion of chip area occupied by the terminal structure.
  • the first well region can offset part of the electric field of the epitaxial layer, thereby reducing the influence of epitaxial layer doping on the charge balance of the charge compensation region and further improving the breakdown voltage of the terminal structure.
  • forming a first well region of a second conductivity type in a region of the epitaxial layer away from the substrate includes: performing ion implantation of a second conductivity type on the surface of the epitaxial layer away from the substrate in the first direction and performing high-temperature push junction to form a first well region of the second conductivity type.
  • forming a plurality of doped regions of a first conductivity type in the first well region along a second direction perpendicular to the first direction includes: performing ion implantation of the first conductivity type in a plurality of spaced implantation regions in the first well region, and performing high-temperature push junction to form a plurality of doped regions of the first conductivity type.
  • the spacing between two adjacent doped regions satisfies:
  • Na is the doping concentration of the doped region
  • Wa is the width of the doped region
  • Nd is the doping concentration of the first well region
  • Wd is the distance between two adjacent doped regions
  • i is the i-th doped region
  • n is the total number of doped regions.
  • a field limiting ring structure surrounding the active region is formed in a region of the epitaxial layer away from the substrate, and the method further includes: performing ion implantation at the end of the epitaxial layer away from the active region in the second direction to form a cutoff ring region.
  • forming a field-limiting ring structure surrounding the active region in a region of the epitaxial layer away from the substrate further includes: forming an oxide layer on the side of the first well region, the plurality of doped regions, and the cutoff ring region away from the substrate, the oxide layer covering the first well region, a portion of the epitaxial layer, the plurality of doped regions, and a portion of the cutoff ring region; forming a gate on the side of the oxide layer away from the substrate; and forming a plurality of polycrystalline field plates on the side of the oxide layer away from the substrate, the plurality of polycrystalline field plates being spaced apart from the gate and spaced apart from each other in the second direction.
  • forming an oxide layer on the side of the first well region, the plurality of doped regions, and the cutoff ring region away from the substrate includes: forming a first oxide layer that extends continuously along the second direction on the side of the plurality of doped regions and the cutoff ring region away from the substrate; and forming a second oxide layer on the side of the epitaxial layer near the active region and away from the substrate, wherein the second oxide layer is connected to the first oxide layer.
  • forming a gate on the side of the oxide layer away from the substrate includes: forming a first gate portion on the side of the second oxide layer away from the substrate; and forming a second gate portion on the side of the first oxide layer away from the substrate, wherein the first oxide layer covers the first well region, the plurality of doped regions, and a portion of the cutoff ring region, wherein the thickness of the first oxide layer is greater than the thickness of the second oxide layer.
  • a field confinement ring structure surrounding the active region is formed in a region of the epitaxial layer away from the substrate, and the method further includes forming a plurality of polycrystalline field plates on the side of the first oxide layer away from the substrate.
  • forming a field-limiting ring structure surrounding the active region in a region of the epitaxial layer away from the substrate further includes: performing ion implantation of a second conductivity type on the surface of the second oxide layer near the substrate, on the surface of the epitaxial layer away from the substrate, and on the side of the first well region near the active region to form a second well region of a second conductivity type, wherein the second well region is connected to the first well region.
  • the method for manufacturing a terminal structure for a semiconductor device further includes: forming a third oxide layer extending continuously along a second direction on the side of the second well region, the gate, the oxide layer, the plurality of polycrystalline field plates, and the cutoff ring region away from the substrate, the third oxide layer being used to cover a portion of the second well region, the gate, the oxide layer, the plurality of polycrystalline field plates, and a portion of the cutoff ring region; and forming a first active region metal portion on the side of the second well region away from the substrate, and forming a second active region metal portion on the side of the third oxide layer away from the substrate, the first active region metal portion and the second active region metal portion being connected.
  • the method for manufacturing a terminal structure for a semiconductor device further includes: forming a stop ring metal on the side of the third oxide layer away from the substrate and on the side of the stop ring region away from the substrate.
  • Figure 1 is a schematic diagram of the terminal structure of a semiconductor device according to an embodiment of this application.
  • Figure 2 is a schematic diagram of the terminal structure of a semiconductor device according to another embodiment of this application.
  • Figure 3 is a top view of a semiconductor device according to an embodiment of this application.
  • Figure 4 is a top view of a semiconductor device according to another embodiment of this application.
  • Figure 5 is a schematic diagram of the surface electric field distribution of the terminal structure extracted by simulation according to an embodiment of this application and the classic field ring plate terminal structure.
  • Figure 6 is a block diagram of a semiconductor device according to an embodiment of this application.
  • FIG. 7 is a block diagram of a power module according to an embodiment of this application.
  • Figure 8 is a block diagram of a power electronic device according to an embodiment of this application.
  • FIG. 9 is a block diagram of a vehicle according to an embodiment of this application.
  • Figure 10 is a schematic diagram of the fabrication process of the terminal structure of a semiconductor device according to an embodiment of this application.
  • Figure 11 is a schematic diagram of the fabrication process of the terminal structure of a semiconductor device according to another embodiment of this application.
  • Figure 12 is a schematic diagram of the fabrication process of the terminal structure of a semiconductor device according to another embodiment of this application.
  • embodiments of this application provide a semiconductor device termination structure and its manufacturing method, as well as a semiconductor device, a power module, a power electronic device, and a vehicle. This improves surface doping and surface electric field distribution, reduces electric field peak and leakage current, and enhances the efficiency of the termination structure, thereby maintaining high withstand voltage within a smaller termination structure size.
  • Figure 1 is a schematic diagram of a terminal structure of a semiconductor device according to an embodiment of the present application.
  • Figure 1 is only a basic schematic diagram.
  • the terminal structure 10 of the semiconductor device includes a substrate 1 of a first conductivity type, an epitaxial layer 2 of a first conductivity type, and a field confinement ring structure 3.
  • terminal structure 10 of the semiconductor device in this application embodiment can be understood with reference to Figure 2, which is a schematic diagram of the terminal structure of a semiconductor device according to another embodiment of this application.
  • epitaxial layer 2 is located on substrate 1 in the first direction; and field confinement ring structure 3 is located within epitaxial layer 2 in the first direction.
  • Epitaxial layer 2 is located on substrate 1 in the first direction.
  • the difference between epitaxial layer 2 and substrate 1 lies in their concentrations; substrate 1 is easier to dope. Additionally, epitaxial layer 2 and substrate 1 differ in price and growth rate. It is understood that substrate 1 serves as the substrate for the entire power device.
  • the field limiting ring structure 3 is arranged around the active region.
  • the field limiting ring structure 3 includes a first well region 31 of the second conductivity type.
  • the first well region 31 is provided with a plurality of doped regions 32 of the first conductivity type.
  • the plurality of doped regions 32 of the first conductivity type are arranged at intervals along a second direction perpendicular to the first direction.
  • Figure 1 only shows a cross-section of the terminal structure 10 of the semiconductor device.
  • the field limiting ring structure 3 is a closed surrounding structure disposed around the chip.
  • a first well region 31 is provided in the epitaxial layer 2 of the field limiting ring structure 3, and a plurality of doped regions 32 of the first conductivity type are arranged at intervals in the first well region 31.
  • the combination of the first well region 31 of the second conductivity type and the plurality of doped regions 32 of the first conductivity type is equivalent to introducing pillars of different conductivity types with different doping concentrations arranged alternately. Utilizing the charge compensation principle, in the blocking state, the pillars of different conductivity types can be well depleted, thereby improving the surface doping and surface electric field distribution.
  • the charges of P pillars and N pillars can be mutually depleted, which can also reduce the electric field peak and leakage current, improve the efficiency of the semiconductor device termination structure 10, and effectively reduce the size of the semiconductor device termination structure 10. This allows for higher breakdown voltage at the same semiconductor device termination structure 10 size.
  • the smaller semiconductor device termination structure 10 can reserve more space for the active region of the chip, reducing the proportion of the chip area occupied by the semiconductor device termination structure 10.
  • the first well region 31 can offset part of the electric field of the epitaxial layer 2, thereby reducing the influence of the doping of the epitaxial layer 2 on the charge balance of the charge compensation region, and further improving the breakdown voltage of the terminal structure 10 of the semiconductor device.
  • the multiple doped regions 32 of the first conductivity type are respectively ring-shaped doped regions surrounding the entire source region.
  • FIG3 which is a top view of a semiconductor device according to an embodiment of the present application, when preparing the doped regions 32 of the first conductivity type, it is necessary to make an opening in the first well region 31 and inject the first conductivity type impurities.
  • the injection openings of the multiple doped regions 32 of the first conductivity type in the terminal structure 10 of the semiconductor device can be set as strips, and each strip ultimately forms multiple ring structures around the active region 20.
  • each doped region 32 of a first conductivity type is disposed around an active region, and each doped region 32 of a first conductivity type includes a plurality of sub-doped regions of the first conductivity type disposed at intervals from each other. Further, in some embodiments, the sub-doped regions of the first conductivity type are cylindrical sub-doped regions of the first conductivity type.
  • the injection openings of the multiple doped regions 32 of the first conductivity type in the terminal structure 10 of the semiconductor device can be set to be square.
  • Figure 4 only shows a part of the doped regions 32 of the first conductivity type.
  • the multiple square doped regions 32 of the first conductivity type are arranged around the active region 20, and the multiple square doped regions 32 of the first conductivity type eventually form multiple ring structures.
  • the second conductivity type can be P-type
  • the first conductivity type is N-type
  • multiple doped regions 32 of the first conductivity type are disposed within the first well region 31. This is equivalent to the multiple doped regions 32 of the first conductivity type and the first well region 31 forming alternating columns of different conductivity types with different doping concentrations.
  • Figure 5 it is a schematic diagram of the surface electric field distribution of the terminal structure extracted by simulation according to an embodiment of this application and the classical field ring field plate terminal structure.
  • Curve A is the electric field distribution curve of the terminal structure 10 of the semiconductor device extracted by simulation according to an embodiment of this application
  • curve B is the electric field distribution curve of the classical field ring field plate terminal structure 0 extracted by simulation.
  • the terminal structure 10 of the semiconductor device in the embodiment of this application can significantly improve the surface electric field distribution.
  • the pillars of different conductivity types can be well depleted under blocking conditions.
  • the electric field distribution changes from a triangular distribution in the traditional device structure to a rectangular distribution, which improves surface doping and surface electric field distribution, reduces electric field peak and leakage current, improves termination efficiency, and reduces the size of the semiconductor device termination structure 10. Higher breakdown voltage is achieved with the same semiconductor device termination structure 10 size.
  • the distance between adjacent doped regions 32 of the plurality of first conductivity types may be equal; or in the second direction, the distance between adjacent doped regions 32 of the plurality of first conductivity types may gradually increase in the direction away from the active region; or in the second direction, the distance between adjacent doped regions 32 of the plurality of first conductivity types may gradually decrease in the direction away from the active region.
  • the alternating arrangement of P-pillars and N-pillars is achieved, thereby planning the electric field distribution and depletion in the terminal structure 10 of the semiconductor device, so as to improve the electric field distribution and reduce electric field spikes.
  • the field limiting ring structure 3 further includes a second well region 33 of a second conductivity type.
  • the second well region 33 is located in the epitaxial layer 2 in a first direction and is located on the side of the first well region 31 near the active region.
  • the second well region 33 is connected to the first well region 31.
  • the function of the second well region 33 is to act as the main junction.
  • the size of the second well region 33 can be selected according to the actual design needs, and no specific limitation is made here. Its function is to provide a current lead-out location for the terminal and a placement location for the power MOSFET gate.
  • the field limiting ring structure 3 further includes a cutoff ring region 34, which is located at the end of the epitaxial layer 2 away from the active region in the second direction and is spaced apart from the first well region 31.
  • the first well region 31, the second well region 33, each doped region 32, and the cutoff ring region 34 extend from their surfaces away from the substrate 1 into the epitaxial layer 2 in a direction close to the substrate 1.
  • the terminal structure 10 of the semiconductor device further includes an oxide layer 35, a gate 36, and a plurality of polycrystalline field plates 37.
  • the oxide layer 35 is located on the side away from the substrate 1 of the first well region 31, the second well region 33, the plurality of doped regions 32, and the cutoff ring region 34 in a first direction, and covers a portion of the first well region 31, the second well region 33, the plurality of doped regions 32, and a portion of the cutoff ring region 34.
  • the oxide layer 35 includes a first oxide layer 351 and a second oxide layer 352.
  • the first oxide layer 351 is located on the side away from the substrate 1 of the first well region 31, the plurality of doped regions 32, and the cutoff ring region 34 in a first direction and extends continuously along a second direction.
  • the first oxide layer 351 is a field oxide layer.
  • a second gate portion 362 and a plurality of polycrystalline field plates 37 are provided on the side of the first oxide layer 351 away from the substrate 1 in the first direction.
  • the first oxide layer 351 covers a portion of the first well region 31, the plurality of doped regions 32, and the cutoff ring region 34.
  • the second oxide layer 352 is gate oxide. It is located in the first direction on the side of the second well region 33 away from the substrate 1, and between the second well region 33 and the first gate portion 361.
  • the second oxide layer 352 is connected to the first oxide layer 351, wherein the thickness of the first oxide layer 351 is greater than the thickness of the second oxide layer 352. It is understood that since the first oxide layer 351 is a field oxide layer, a thicker field oxide layer can withstand a higher breakdown voltage; while the second oxide layer 352 is gate oxide, a thicker gate oxide layer would lead to an excessively high threshold voltage, and might even prevent the semiconductor device from turning on.
  • the gate 36 includes a first gate portion 361 and a second gate portion 362 interconnected with each other.
  • the first gate portion 361 is located on the side of the oxide layer 35 away from the substrate 1 in a first direction.
  • a plurality of polycrystalline field plates 37 are located on the side of the oxide layer 35 away from the substrate 1 in the first direction, and the plurality of polycrystalline field plates 37 are spaced apart from and from the second gate 36 in a second direction.
  • the plurality of polycrystalline field plates 37 are made of the same material as the gate 36.
  • the terminal structure 10 of the semiconductor device further includes a protective layer located on the side of the field-limiting ring structure 3 away from the substrate 1 in the first direction.
  • the protective layer includes a third oxide layer 41 and an active region metal 42.
  • the protective layer is not shown in Figure 2.
  • the third oxide layer 41 is located in the first direction on the side of the second well region 33, gate 36, first oxide layer 351, multiple polycrystalline field plates 37, and cutoff ring region 34 away from the substrate 1, and extends continuously in the second direction to cover a portion of the second well region 33, gate 36, first oxide layer 351, multiple polycrystalline field plates 37, and a portion of the cutoff ring region 34.
  • the active region metal 42 includes a first active region metal portion 421 and a second active region metal portion 422, which are connected.
  • the first active region metal portion 421 is located in the first direction on the side of the second well region 33 away from the substrate 1
  • the second active region metal portion 422 is located in the first direction on the side of the third oxide layer 41 away from the substrate 1.
  • the second active region metal portion 422 functions as a metal field plate, which reduces the electric field at the main junction, i.e., the second well region 33.
  • the terminal structure 10 of the semiconductor device further includes a cutoff ring metal 43, which includes a first cutoff ring metal portion 431 and a second cutoff ring metal portion 432.
  • the first cutoff ring metal portion 431 is connected to the second cutoff ring metal portion 432.
  • the first cutoff ring metal portion 431 is located on the side of the third oxide layer 41 away from the substrate 1 in a first direction.
  • the first cutoff ring metal portion 431 is spaced apart from the second active region metal portion 422 in a second direction.
  • the second cutoff ring metal portion 432 is located on the side of the cutoff ring region 34 away from the substrate 1 in a first direction.
  • the side of the second cutoff ring metal portion 432 away from the active region 20 is flush with the side of the cutoff ring region 34 away from the active region 20.
  • FIG6 is a block diagram of a semiconductor device according to an embodiment of this application.
  • the semiconductor device 100 includes an active region 20 and a termination structure 10 according to the above embodiment, the termination structure 10 surrounding the active region 20.
  • the semiconductor device 100 of the embodiment of this application can be understood with reference to FIG3 and FIG4, which will not be repeated here.
  • the semiconductor device 100 by employing the termination structure 10 of the semiconductor device of the above embodiment surrounding the active region 20, can improve surface doping and surface electric field distribution, and also reduce electric field peak and leakage current, thereby improving the efficiency of the semiconductor device 100.
  • the size of the termination structure 10 of the semiconductor device is relatively small overall, thereby achieving a higher withstand voltage for the same size of the termination structure 10 of the semiconductor device.
  • the smaller size of the termination structure 10 can reserve more space for the active region 20 of the chip, reducing the proportion of the chip area occupied by the termination structure 10 of the semiconductor device.
  • FIG7 is a block diagram of a power module according to an embodiment of this application, wherein the power module 200 includes a semiconductor device 100 according to the above embodiment.
  • the power module 200 proposed according to the embodiments of this application includes the semiconductor device 100 of the above embodiments. By improving the structure of the semiconductor device 100, the efficiency and voltage resistance of the semiconductor device 100 are improved, thereby improving the efficiency and voltage resistance of the power module 200.
  • FIG8 is a block diagram of a power electronic device according to an embodiment of this application, wherein the power electronic device 2000 includes a power module 200 according to the above embodiment.
  • the power electronic device 2000 by employing the power module 200 of the above embodiments, can improve the efficiency and withstand voltage of the power module 200 by improving the efficiency of the semiconductor device 100, thereby effectively improving the efficiency and performance of the power electronic device 2000.
  • Embodiments of this application also propose a vehicle, as shown in FIG9, which is a block diagram of a vehicle according to an embodiment of this application, wherein the vehicle 1000 includes a semiconductor device 100 according to the above embodiment.
  • the vehicle 1000 by employing the semiconductor device 100 of the above embodiments, can improve the performance of the whole vehicle and the withstand voltage of the circuit structure in the whole vehicle by improving the efficiency of the semiconductor device 100, thereby improving the safety of the vehicle 1000.
  • FIG10 is a schematic diagram of the preparation process of the terminal structure of a semiconductor device according to an embodiment of this application.
  • an epitaxial layer 2 of the first conductivity type is formed on a substrate 1 of the first conductivity type, and the epitaxial layer 2 is located on the substrate 1 in a first direction.
  • a substrate 1 of a first conductivity type, P-type can be provided first.
  • the structure and manufacturing method of this application embodiment are applicable to materials such as Si and SiC that can be used to prepare power devices.
  • Single-crystal silicon can be used as substrate 1, and the (100)/(001) plane can be used for subsequent processes.
  • the substrate 1 is cleaned to remove impurity particles, and a first conductivity type layer of a certain thickness, namely epitaxial layer 2, is epitaxially grown.
  • the thickness of epitaxial layer 2 is 80-120 ⁇ m, and the dose is 1e13-1e14/cm3, depending on the voltage withstand requirement.
  • a field confinement ring structure 3 surrounding the active region is formed in the region of the epitaxial layer 2 away from the substrate 1.
  • the step specifically includes: forming a first well region 31 of a second conductivity type in a region of the epitaxial layer 2 away from the substrate 1; and forming a plurality of doped regions 32 of the first conductivity type spaced apart in the first well region 31 along a second direction perpendicular to the first direction.
  • the second conductivity type is N-type, and a first well region 31 can be formed in the epitaxial layer 2 by ion implantation.
  • Forming the first well region 31 of the second conductivity type in the region of the epitaxial layer 2 away from the substrate 1 includes: performing ion implantation of the second conductivity type on the surface of the epitaxial layer 2 away from the substrate 1 in a first direction and performing high-temperature push-bonding to form the first well region 31 of the second conductivity type.
  • second conductivity type ion implantation is performed at the terminal to form a well structure, i.e., the first well region 31, with a conductivity type different from that of the epitaxial layer 2.
  • the implantation metering is 1e12 to 4e12, and high-temperature push-bonding is performed at 115°C for 180 minutes.
  • Forming a plurality of doped regions 32 of a first conductivity type spaced apart along a second direction perpendicular to the first direction within the first well region 31 includes: performing ion implantation of the first conductivity type in a plurality of spaced-apart implantation regions within the first well region 31, and performing high-temperature push-bonding to form the plurality of doped regions 32 of the first conductivity type. It also includes: performing ion implantation at the end of the epitaxial layer 2 away from the active region in the second direction to form a cutoff ring region 34.
  • a barrier layer is deposited and etched on the surface of the epitaxial layer 2.
  • the barrier layer can be photoresist.
  • the barrier layer on the surface of the first well region 31 forms implantation windows with gradually decreasing spacing from the active region 20 towards the field-limiting ring structure 3, or equally spaced implantation windows, or implantation windows with gradually increasing spacing from the active region 20 towards the field-limiting ring structure 3.
  • First conductivity type ion implantation is performed to form a first conductivity type region within the first well region 31.
  • push-bonding is performed to form multiple first conductivity type doped regions 32 and cutoff ring regions 34.
  • the implantation metering is 9e12 to 3e13, and high-temperature push-bonding is performed at 105°C-115°C/180-360min, where the push-bonding temperature can be selected as 115°C.
  • the spacing between two adjacent doped regions 32 satisfies formula (1-1), where Na is the doping concentration of the doped region 32; Wa is the width of the doped region 32; Nd is the doping concentration of the first well region 31; Wd is the distance between two adjacent doped regions 32; i is the i-th doped region 32; and n is the total number of doped regions 32.
  • a method for manufacturing a terminal structure for a semiconductor device by preparing a combination of a first well region of a second conductivity type and multiple doped regions of the first conductivity type in a field-limiting ring structure, it is equivalent to introducing alternating pillars of different conductivity types with different doping concentrations.
  • the pillars of different conductivity types can be well depleted, thereby improving surface doping and surface electric field distribution, reducing electric field peak and leakage current, improving the efficiency of the terminal structure, and effectively reducing the size of the terminal structure. This allows for higher breakdown voltage at the same terminal structure size.
  • a smaller terminal structure can reserve more space for the active region of the chip, reducing the proportion of chip area occupied by the terminal structure.
  • the first well region can offset part of the electric field of the epitaxial layer, thereby reducing the influence of epitaxial layer doping on the charge balance of the charge compensation region and further improving the breakdown voltage of the terminal structure.
  • FIG12 it is a schematic diagram of the fabrication process of the terminal structure of a semiconductor device according to another embodiment of this application.
  • a field-limiting ring structure 3 surrounding the active region is formed in a region of the epitaxial layer 2 away from the substrate 1.
  • the process further includes forming an oxide layer 35 on the side of the first well region 31, the plurality of doped regions 32, and the stop-ring region 34 away from the substrate 1.
  • the oxide layer 35 covers the first well region 31, a portion of the epitaxial layer 2, the plurality of doped regions 32, and a portion of the stop-ring region 34.
  • an oxide layer 35 is formed on the side of the first well region 31, the plurality of doped regions 32, and the stop ring region 34 away from the substrate 1, including: forming a first oxide layer 351 that extends continuously along a second direction on the side of the plurality of doped regions 32 and the stop ring region 34 away from the substrate 1.
  • the first oxide layer 351 covers a portion of the first well region 31, the plurality of doped regions 32, and the stop ring region 34.
  • a second oxide layer 352 is formed on the side of the epitaxial layer 2 near the active region 20 and away from the substrate 1, and the second oxide layer 352 is connected to the first oxide layer 351.
  • the thickness of the second oxide layer 352 is less than the thickness of the first oxide layer 351.
  • a gate 36 is formed on the side of the oxide layer 35 away from the substrate 1; and a plurality of polycrystalline field plates 37 are formed on the side of the oxide layer 35 away from the substrate 1, the plurality of polycrystalline field plates 37 being spaced apart from and from the gate 36 in a second direction.
  • Forming the gate 36 on the side of the oxide layer 35 away from the substrate 1 includes: forming a first gate portion 361 on the side of the second oxide layer 352 away from the substrate 1; and forming a second gate portion 362 on the side of the first oxide layer 351 away from the substrate 1.
  • a plurality of polycrystalline field plates 37 are formed on the side of the first oxide layer 351 away from the substrate 1.
  • polysilicon is deposited and etched on the upper surface of oxide layer 35 to form gate 36 and multiple polycrystalline field plates 37, which are located on both sides of the left boundary of multiple doped regions 32.
  • a field-limiting ring structure 3 surrounding the active region is formed in the region of the epitaxial layer 2 away from the substrate 1.
  • This further includes performing ion implantation of a second conductivity type on the surface of the second oxide layer 352 near the substrate 1, on the surface of the epitaxial layer 2 away from the substrate 1, and on the side of the first well region 31 near the active region to form a second well region 33 of the second conductivity type.
  • the second well region 33 is connected to the first well region 31.
  • ion implantation of a second conductivity type is performed in the terminal structure 10 of the semiconductor device to form a well structure, i.e., the second well region 33, of a different conductivity type than the epitaxial layer 2.
  • the implantation dose is 1e13 to 1e14, and a high-temperature push-bonding process is performed at 115°C for 105 minutes.
  • the preparation process of the third oxide layer 41, the active region metal 42, and the stop ring metal 43 can be understood in conjunction with FIG2.
  • the method for manufacturing the terminal structure of a semiconductor device further includes forming a third oxide layer 41 extending continuously in a second direction on the side of the second well region 33, gate 36, oxide layer 35, multiple polycrystalline field plates 37 and cutoff ring region 34 away from the substrate 1.
  • the third oxide layer 41 is used to cover a portion of the second well region 33, gate 36, oxide layer 35, multiple polycrystalline field plates 37 and a portion of the cutoff ring region 34.
  • a first active region metal portion 421 is formed on the side of the second well region 33 away from the substrate 1, and a second active region metal portion 422 is formed on the side of the third oxide layer 41 away from the substrate 1.
  • the first active region metal portion 421 and the second active region metal portion 422 are connected.
  • the method for manufacturing the termination structure of the semiconductor device further includes forming a stop ring metal 43 on the side of the third oxide layer 41 away from the substrate 1 and on the side of the stop ring region 34 away from the substrate 1, ultimately forming the termination structure 10 of the semiconductor device as shown in FIG2.
  • the terminal structure 10 of the semiconductor device is prepared by utilizing the charge compensation principle.
  • the first well region 31 and the doped region 32 are formed into alternating P-pillars and N-pillars.
  • the charges of the P-pillars and N-pillars are mutually depleted, and the electric field distribution changes from the triangular distribution in the traditional device structure to a rectangular distribution, thereby effectively improving the electric field distribution and reducing electric field spikes.
  • the influence of the doping of the epitaxial layer 2 on the charge balance of the charge compensation region is reduced, further improving the breakdown voltage of the terminal structure 10 of the semiconductor device, and reducing the proportion of the chip area occupied by the terminal structure 10 of the semiconductor device while improving the breakdown voltage of the terminal structure 10.
  • references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples,” etc. refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application.
  • the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

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Abstract

一种半导体器件的终端结构及其制造方法、半导体器件、功率模块、电力电子器件和车辆，半导体器件的终端结构，包括：第一导电类型的衬底；第一导电类型的外延层，外延层在第一方向上位于衬底上；以及场限环结构，场限环结构在第一方向上位于外延层中，场限环结构环绕有源区设置，场限环结构包括第二导电类型的第一阱区，第一阱区内设有多个第一导电类型的掺杂区，多个第一导电类型的掺杂区沿与第一方向垂直的第二方向间隔排布。

Description

半导体器件的终端结构及其制造方法、半导体器件、功率模块、电力电子器件和车辆
本申请要求于2024年06月28日提交中国专利局、申请号为202410866923.9、申请名称为“半导体器件的终端结构及其制造方法、半导体器件、功率模块、电力电子器件和车辆”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及功率器件技术领域，尤其是涉及一种半导体器件的终端结构及其制造方法、半导体器件、功率模块、电力电子器件和车辆。
背景技术
功率半导体器件的有源区承担耐压的PN结近似于平面结，能够承担较高耐压，而在有源区的边缘会由于电场的集中效应而导致PN结耐压较低，这严重限制了功率器件的耐压值。因此，为提高功率器件的最高耐压，需要在有源区边缘增加一圈终端结构来缓解有源区边缘的电场的集中效应。现有的终端技术场环场板终端，通常利用场环分压来使电压降落在更长的距离来承受高压。
公开内容
本申请旨在至少解决现有技术中存在的技术问题之一。为此，本申请的第一个目的在于提出一种半导体器件的终端结构，能够改善表面掺杂和表面电场分布、降低电场峰值和漏电，提升终端结构的效率，进而能够在较小终端结构的尺寸下保持高耐压。
本申请的第二个目的在于提出一种半导体器件。
本申请的第三个目的在于提出一种功率模块。
本申请的第四个目的在于提出一种电力电子器件。
本申请的第五个目的在于提出一种车辆。
本申请的第六个目的在于提出一种用于制造半导体器件的终端结构的方法。
为了达到上述目的，本申请第一方面实施例提出的半导体器件的终端结构，包括：第一导电类型的衬底；第一导电类型的外延层，所述外延层在第一方向上位于所述衬底上；以及场限环结构，所述场限环结构在所述第一方向上位于所述外延层中，所述场限环结构环绕有源区设置，所述场限环结构包括第二导电类型的第一阱区，所述第一阱区内设有多个第一导电类型的掺杂区，所述多个第一导电类型的掺杂区沿与所述第一方向垂直的第二方向间隔排布。
根据本申请实施例提出的半导体器件的终端结构，在场限环结构中的外延层中设置第二导电类型的第一阱区与多个第一导电类型的掺杂区组合，相当于引入了掺杂浓度的不同导电类型柱交替排列，利用电荷补偿原理，在阻断状态下，使得不同导电类型柱能够很好的耗尽，从而能够改善表面掺杂和表面电场分布，还能降低电场峰值和漏电，提升终端结构的效率，还能有效减小终端结构的尺寸，从而使得在相同的终端结构尺寸时获得更高的耐压，对于相同的半导体器件，小尺寸的终端结构能够为芯片的有源区预留出更多的空间，减少终端结构所占芯片面积的比例。
此外，通过在场限环结构中的外延层中设置第一阱区，第一阱区能够抵消掉一部分外延层的电场，从而能够降低外延层掺杂对电荷补偿区电荷平衡的影响，进一步提升了终端结构的耐压。
在本申请的一些实施例中，多个所述第一导电类型的掺杂区分别为环绕整个所述有源区的环形掺杂区。
在本申请的一些实施例中，每个所述第一导电类型的掺杂区环绕所述有源区设置，且每个所述第一导电类型的掺杂区包括多个彼此间隔设置的第一导电类型的子掺杂区。
在本申请的一些实施例中，所述第一导电类型的子掺杂区为第一导电类型的柱形子掺杂区。
在本申请的一些实施例中，在所述第二方向上，多个所述第一导电类型的掺杂区中的相邻的所述掺杂区之间的距离相等；或者在所述第二方向上，多个所述第一导电类型的掺杂区中的相邻的所述掺杂区之间的距离沿远离所述有源区的方向逐渐增大；或者在所述第二方向上，多个所述第一导电类型的掺杂区中的相邻的所述掺杂区之间的距离沿远离所述有源区的方向逐渐减小。
在本申请的一些实施例中，所述场限环结构还包括：第二导电类型的第二阱区，所述第二阱区在所述第一方向上位于所述外延层中，所述第二阱区位于所述第一阱区的靠近所述有源区的一侧，所述第二阱区与所述第一阱区连接。其中，第二阱区的作用在于充当主结，其能够为终端提供电流引出位置和功率MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应管)栅的放置位置。
在本申请的一些实施例中，所述场限环结构还包括：截止环区，所述截止环区位于所述外延层的在所述第二方向上远离所述有源区的端部且与所述第一阱区间隔设置。
在本申请的一些实施例中，所述第一阱区、所述第二阱区、各个所述掺杂区、所述截止环区分别自其远离所述衬底的表面沿靠近所述衬底的方向延伸到所述外延层中。
在本申请的一些实施例中，所述半导体器件的终端结构，还包括：氧化层，所述氧化层在所述第一方向上位于所述第一阱区、所述第二阱区、多个所述掺杂区以及所述截止环区的远离所述衬底的一侧上，且覆盖所述第一阱区、所述第二阱区的一部分、多个所述掺杂区以及所述截止环区的一部分。
在本申请的一些实施例中，所述半导体器件的终端结构，还包括：栅极，所述栅极包括互相连接的第一栅极部和第二栅极部，所述第一栅极部在所述第一方向上位于所述氧化层的远离所述衬底的一侧。
在本申请的一些实施例中，所述半导体器件的终端结构，还包括：多个多晶场板，多个所述多晶场板在所述第一方向上位于所述氧化层的远离所述衬底的一侧，多个所述多晶场板在所述第二方向上与所述第二栅极间隔设置且彼此间隔设置。
在本申请的一些实施例中，所述氧化层包括：第一氧化层，所述第一氧化层在所述第一方向上位于所述第一阱区、多个所述掺杂区和所述截止环区的远离所述衬底的一侧且沿所述第二方向连续延伸，所述第一氧化层的在所述第一方向上远离所述衬底的一侧上设有所述第二栅极部和所述多个多晶场板，所述第一氧化层覆盖所述第一阱区、多个所述掺杂区以及所述截止环区的所述一部分。
在本申请的一些实施例中，所述氧化层还包括：第二氧化层，所述第二氧化层与所述第一氧化层连接，所述第二氧化层在所述第一方向上位于所述第二阱区的远离所述衬底的一侧，且位于所述第二阱区与所述第一栅极部之间；其中，所述第一氧化层的厚度大于所述第二氧化层的厚度。其中，通过设置第一氧化层更厚可以承受更高的击穿电压；而第二氧化层较厚则会导致阈值电压过大，甚至可能导致半导体器件无法开启。
在本申请的一些实施例中，所述半导体器件的终端结构，还包括：防护层，所述防护层在所述第一方向上位于所述场限环结构的远离所述衬底的一侧。
在本申请的一些实施例中，所述防护层包括：第三氧化层，所述第三氧化层在所述第一方向上位于所述第二阱区、所述栅极、所述第一氧化层、多个所述多晶场板以及所述截止环区的远离所述衬底的一侧并沿所述第二方向连续延伸，用于覆盖所述第二阱区的一部分、所述栅极、所述第一氧化层、多个所述多晶场板以及所述截止环区的一部分。
在本申请的一些实施例中，所述防护层还包括：有源区金属，所述有源区金属包括第一有源区金属部和第二有源区金属部，所述第一有源区金属部和所述第二有源区金属部连接，所述第一有源区金属部在所述第一方向上位于所述第二阱区的远离所述衬底的一侧，所述第二有源区金属部在所述第一方向上位于所述第三氧化层的远离所述衬底的一侧。其中，第二有源区金属部的作用是作为金属场板，通过设置该金属场板能够降低主结也就是第二阱区处的电场。
在本申请的一些实施例中，所述半导体器件的终端结构，还包括：截止环金属，所述截止环金属包括第一截止环金属部和第二截止环金属部，所述第一截止环金属部与所述第二截止环金属部连接，所述第一截止环金属部在所述第一方向上位于所述第三氧化层的远离所述衬底的一侧，所述第一截止环金属部在所述第二方向上与所述第二有源区金属部间隔开，所述第二截止环金属部在所述第一方向上位于所述截止环区的远离衬底的一侧，所述第二截止环金属部的远离所述有源区的侧面与所述截止环区的远离所述有源区的侧面平齐。
为了达到上述目的，本申请第二方面实施例提出的半导体器件，包括：有源区；和根据上面实施例中任一项所述的半导体器件的终端结构，所述半导体器件的终端结构环绕所述有源区设置。
根据本申请实施例提出的半导体器件，通过采用上面实施例的半导体器件的终端结构环绕所述有源区设置，能够改善表面掺杂和表面电场分布，还能降低电场峰值和漏电，提升半导体器件的效率。形成的上述终端结构的尺寸整体较小，从而使得在相同的终端结构尺寸时获得更高的耐压，对于相同的半导体器件，小尺寸的终端结构能够为芯片的有源区预留出更多的空间，减少终端结构所占芯片面积的比例。
为了达到上述目的，本申请第三方面实施例提出一种功率模块，包括根据上面第二方面实施例所述的半导体器件。
根据本申请实施例提出的功率模块，包括上面实施例的半导体器件，通过改进半导体器件的结构，实现提升半导体器件的效率和奶也，进而能够提升功率模块的效率和耐压。
为了达到上述目的，本申请第四方面实施例提出一种电力电子器件，包括根据上面第三方面实施例所述的功率模块。
根据本申请实施例提出的电力电子器件，通过采用采用上面实施例的功率模块，通过提升半导体器件的效率，能够提升功率模块的效率和耐压，进而能够有效提升电力电子器件的效率和性能。
为了达到上述目的，本申请第五方面实施例提出一种车辆，包括根据上面实施例所述的半导体器件。
根据本申请实施例提出的车辆，通过采用上面实施例的半导体器件，通过提升半导体器件的效率，能够提升整车的性能和整车中的电路结构的耐压，进而提升车辆的安全性。
为了达到上述目的，本申请第六方面实施例提出一种用于制造半导体器件的终端结构的方法，包括：在第一导电类型的衬底上形成第一导电类型的外延层，所述外延层在第一方向上位于所述衬底上；在所述外延层的远离所述衬底的区域中形成环绕有源区的场限环结构，包括：在所述外延层的远离所述衬底的区域中，形成第二导电类型的第一阱区；以及在所述第一阱区内形成沿与所述第一方向垂直的所述第二方向上间隔排布的多个第一导电类型的掺杂区。
根据本申请实施例提出的用于制造半导体器件的终端结构的方法，通过在场限环结构中，制备第二导电类型的第一阱区与多个第一导电类型的掺杂区组合，相当于引入了掺杂浓度的不同导电类型柱交替排列，利用电荷补偿原理，使得不同导电类型柱能够很好的耗尽，从而能够改善表面掺杂和表面电场分布，降低电场峰值和漏电，提升终端结构的效率，还能有效减小终端结构的尺寸，从而使得在相同的终端结构尺寸时获得更高的耐压，对于相同的半导体器件，小尺寸的终端结构能够为芯片的有源区预留出更多的空间，减少终端结构所占芯片面积的比例。
此外，通过在场限环结构中的外延层中设置第一阱区，第一阱区能够抵消掉一部分外延层的电场，从而能够降低外延层掺杂对电荷补偿区电荷平衡的影响，进一步提升了终端结构的耐压。
在本申请的一些实施例中，在所述外延层的远离所述衬底的区域中，形成第二导电类型的第一阱区，包括：在所述外延层的在所述第一方向上远离所述衬底的表面上进行第二导电类型的离子注入并进行高温推结，以形成所述第二导电类型的第一阱区。
在本申请的一些实施例中，在所述第一阱区内形成沿与所述第一方向垂直的所述第二方向上间隔排布的多个第一导电类型的掺杂区，包括：在所述第一阱区内的多个间隔开的注入区域中，进行第一导电类型的离子注入，并进行高温推结，以形成多个第一导电类型的掺杂区。
在本申请的一些实施例中，相邻的两个所述掺杂区之间的间距满足：
其中，Na为所述掺杂区的掺杂浓度；Wa为所述掺杂区的宽度，Nd为所述第一阱区的掺杂浓度，Wd为相邻的两个所述掺杂区之间的距离，i为第i个掺杂区，n为所述掺杂区的总数量为n。
在本申请的一些实施例中，在所述外延层的远离所述衬底的区域中形成环绕有源区的场限环结构，还包括：在所述外延层的在所述第二方向上远离所述有源区的端部进行离子注入以形成截止环区。
在本申请的一些实施例中，在所述外延层的远离所述衬底的区域中形成环绕有源区的场限环结构，还包括：在所述第一阱区、多个所述掺杂区以及所述截止环区的远离所述衬底的一侧上形成氧化层，所述氧化层覆盖所述第一阱区、所述外延层的一部分、多个所述掺杂区以及所述截止环区的一部分；在所述氧化层的远离所述衬底的一侧形成栅极；以及在所述氧化层的远离所述衬底的一侧形成多个多晶场板，多个所述多晶场板在所述第二方向上与所述栅极间隔设置且彼此间隔设置。
在本申请的一些实施例中，在所述第一阱区、多个所述掺杂区以及所述截止环区的远离所述衬底的一侧上形成氧化层，包括：在多个所述掺杂区和所述截止环区的远离所述衬底的一侧形成沿所述第二方向连续延伸的第一氧化层；以及在所述外延层的靠近所述有源区且远离所述衬底的一侧形成第二氧化层，所述第二氧化层与所述第一氧化层连接。
在本申请的一些实施例中，在所述氧化层的远离所述衬底的一侧形成栅极，包括：在所述第二氧化层的远离所述衬底的一侧形成第一栅极部；以及在所述第一氧化层的远离所述衬底的一侧上形成第二栅极部，所述第一氧化层覆盖所述第一阱区、多个所述掺杂区以及所述截止环区的所述一部分，其中，所述第一氧化层的厚度大于所述第二氧化层的厚度。
在本申请的一些实施例中，在所述外延层的远离所述衬底的区域中形成环绕有源区的场限环结构，还包括：在所述第一氧化层的远离所述衬底的一侧上形成多个多晶场板。
在本申请的一些实施例中，在所述外延层的远离所述衬底的区域中形成环绕有源区的场限环结构，还包括：在所述第二氧化层靠近所述衬底的表面、所述外延层的远离所述衬底的表面上且在所述第一阱区的靠近所述有源区的一侧，进行第二导电类型的离子注入来形成第二导电类型的第二阱区，所述第二阱区与所述第一阱区连接。
在本申请的一些实施例中，所述用于制造半导体器件的终端结构的方法，还包括：在所述第二阱区、所述栅极、所述氧化层、多个所述多晶场板以及所述截止环区的远离所述衬底的一侧形成沿所述第二方向连续延伸的第三氧化层，所述第三氧化层用于覆盖所述第二阱区的一部分、所述栅极、所述氧化层、多个所述多晶场板以及所述截止环区的一部分；以及在所述第二阱区的远离所述衬底的一侧形成第一有源区金属部，在所述第三氧化层的远离所述衬底的一侧形成第二有源区金属部，所述第一有源区金属部和所述第二有源区金属部连接。
在本申请的一些实施例中，所述用于制造半导体器件的终端结构的方法，还包括：在所述第三氧化层的远离所述衬底的一侧和所述截止环区的远离衬底的一侧形成截止环金属。
本申请的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1为根据本申请一个实施例的一种半导体器件的终端结构的示意图；
图2为根据本申请另一个实施例的一种半导体器件的终端结构的示意图；
图3为根据本申请一个实施例的一种半导体器件的俯视图；
图4为根据本申请另一个实施例的一种半导体器件的俯视图；
图5为根据本申请一个实施例的仿真提取的终端结构与经典场环场板终端结构的表面电场分布示意图；
图6为根据本申请一个实施例的半导体器件的框图；
图7为根据本申请一个实施例的功率模块的框图；
图8为根据本申请一个实施例的电力电子器件的框图；
图9为根据本申请一个实施例的车辆的框图；
图10为根据本申请一个实施例的半导体器件的终端结构的制备过程的示意图；
图11为根据本申请另一个实施例的半导体器件的终端结构的制备过程的示意图；
图12为根据本申请又一个实施例的半导体器件的终端结构的制备过程的示意图。
附图标记：
1000：车辆；
2000：电力电子器件；
200：功率模块；
100：半导体器件；
10：半导体器件的终端结构；20：有源区；
1：衬底；2：外延层；3：场限环结构；
31：第一阱区；32：掺杂区；33：第二阱区；34：截止环区；35：氧化层；36：
栅极；37：多晶场板；41：第三氧化层；42：有源区金属；43：截止环金属；
351：第一氧化层；352：第二氧化层；361：第一栅极部；362：第二栅极部；
421：第一有源区金属部；422：第二有源区金属部；431：第一截止环金属部；432：
第二截止环金属部。
具体实施方式
相关技术中，功率半导体器件由于场环掺杂浓度较高很难耗尽，导致其终端效率低，尺寸较大，此外，表面电场分布不均，易发生雪崩导致漏电增加。有鉴于此，本申请实施例提供了一种半导体器件的终端结构及其制造方法、半导体器件、功率模块、电力电子器件和车辆，能够改善表面掺杂和表面电场分布、降低电场峰值和漏电，提升终端结构的效率，进而能够在较小终端结构的尺寸下保持高耐压。
下面详细描述本申请的实施例，参考附图描述的实施例是示例性的。
下面参考图1-图5描述根据本申请实施例的半导体器件的终端结构。图1为根据本申请一个实施例的一种半导体器件的终端结构的示意图，其中，图1仅为基本示意，半导体器件的终端结构10包括第一导电类型的衬底1、第一导电类型的外延层2以及场限环结构3。
具体可结合图2理解本申请实施例的半导体器件的终端结构10，图2为根据本申请另一个实施例的一种半导体器件的终端结构的示意图。
其中，如图2所示，外延层2在第一方向上位于衬底1上；以及场限环结构3在第一方向上位于外延层2中。外延层2在第一方向上位于衬底1上。其中，外延层2和衬底1的区别在于浓度不同，衬底1更好掺杂，另外外延层2和衬底1的价格和生长速率也不同。可以理解的是，衬底1作为整个功率器件的衬底。
场限环结构3环绕有源区设置，场限环结构3包括第二导电类型的第一阱区31，第一阱区31内设有多个第一导电类型的掺杂区32，多个第一导电类型的掺杂区32沿与第一方向垂直的第二方向间隔排布。
其中，本申请实施例中图1仅示出了半导体器件的终端结构10的切面，实际上场限环结构3是设置在芯片外围一圈的封闭包围结构。
根据本申请实施例提出的半导体器件的终端结构10，在场限环结构3中的外延层2中设置第一阱区31，并在第一阱区31内设有间隔排布的多个第一导电类型的掺杂区32，第二导电类型的第一阱区31与多个第一导电类型的掺杂区32组合，相当于引入了掺杂浓度的不同导电类型柱交替排列，利用电荷补偿原理，在阻断状态下，使得不同导电类型柱能够很好地耗尽，从而能够改善表面掺杂和表面电场分布，并且P柱和N柱的电荷能够互相耗尽，还能降低电场峰值和漏电，提升半导体器件的终端结构10的效率，有效减小半导体器件的终端结构10的尺寸，从而使得在相同的半导体器件的终端结构10尺寸时获得更高的耐压，对于相同的半导体器件，小尺寸的半导体器件的终端结构10能够为芯片的有源区预留出更多的空间，减少半导体器件的终端结构10所占芯片面积的比例。
此外，通过增加第一阱区31，第一阱区31能够抵消掉一部分外延层2的电场，从而能够降低外延层2掺杂对电荷补偿区电荷平衡的影响，进一步提升了半导体器件的终端结构10的耐压。
其中，在一些实施例中，多个第一导电类型的掺杂区32分别为环绕整个源区的环形掺杂区。具体地，如图3所示，为根据本申请一个实施例的一种半导体器件的俯视图，在制备第一导电类型的掺杂区32时，需要在第一阱区31上进行开口并注入第一导电类型杂质，可设置半导体器件的终端结构10的多个第一导电类型的掺杂区32注入开口为条形，每个条形围绕有源区20最终形成多个环形结构。
或者，在另一些实施例中，如图4所示，为根据本申请另一个实施例的一种半导体器件的俯视图，其中，每个第一导电类型的掺杂区32环绕有源区设置，且每个第一导电类型的掺杂区32包括多个彼此间隔设置的第一导电类型的子掺杂区。进一步地，在一些实施例中，第一导电类型的子掺杂区为第一导电类型的柱形子掺杂区。
可以理解的是，在制备第一导电类型的掺杂区32时，需要在第一阱区31上进行开口并注入第一导电类型杂质，可设置半导体器件的终端结构10的多个第一导电类型的掺杂区32注入开口为方形，图4中仅示出一部分第一导电类型的掺杂区32，多个方形的第一导电类型的掺杂区32环绕有源区20排列，多个方形的第一导电类型的掺杂区32最终形成多个环形结构。
可以理解的是，第二导电类型可以为P型，第一导电类型为N型，多个第一导电类型的掺杂区32设置在第一阱区31内，相当于多个第一导电类型的掺杂区32与第一阱区31形成了交替排列的掺杂浓度的不同导电类型柱。如图5所示，为根据本申请一个实施例的仿真提取的终端结构与经典场环场板终端结构的表面电场分布示意图，其中，曲线A为本申请实施例的仿真提取的半导体器件的终端结构10的电场分布曲线，曲线B为仿真提取的经典场环场板终端结构0的电场分布曲线，从图中可以看出，本申请实施例的半导体器件的终端结构10能够明显改善表面电场分布。通过引入低掺杂浓度的不同导电类型柱交替排列，即制备交替排列的P柱和N柱，利用电荷补偿原理，在阻断状态下，使得不同导电类型柱能够很好地耗尽，电场分布由传统器件结构中的三角分布变为矩形分布，改善了表面掺杂和表面电场分布，降低了电场峰值和漏电，提升了终端效率，减小了半导体器件的终端结构10尺寸，在相同的半导体器件的终端结构10尺寸时获得更高的耐压。
在本申请的一些实施例中，结合图2-图4进行理解，在第二方向上，可设置多个第一导电类型的掺杂区32中的相邻的掺杂区32之间的距离相等；或者在第二方向上，还可设置多个第一导电类型的掺杂区32中的相邻的掺杂区32之间的距离沿远离有源区的方向逐渐增大；或者在第二方向上，还可设置多个第一导电类型的掺杂区32中的相邻的掺杂区32之间的距离沿远离有源区的方向逐渐减小。
在本申请的一些实施例中，通过合理设置相邻的掺杂区32之间的距离，达到合理排布交替排列的P柱和N柱的情况，进而规划半导体器件的终端结构10中的电场分布和耗尽情况，达到改善电场分布、降低电场尖峰的目的。
在本申请的一些实施例中，如图2所示，场限环结构3还包括第二导电类型的第二阱区33，第二阱区33在第一方向上位于外延层2中，第二阱区33位于第一阱区31的靠近有源区的一侧，第二阱区33与第一阱区31连接。其中，第二阱区33的作用在于充当主结，第二阱区33的尺寸可根据实际设计需要选择其尺寸，此处不做具体限制，其作用在于为终端提供电流引出位置和功率MOSFET栅的放置位置。
在一些实施例中，场限环结构3还包括截止环区34，截止环区34位于外延层2的在第二方向上远离有源区的端部且与第一阱区31间隔设置。其中，第一阱区31、第二阱区33、各个掺杂区32、截止环区34分别自其远离衬底1的表面沿靠近衬底1的方向延伸到外延层2中。
在一些实施例中，如图2所示，半导体器件的终端结构10还包括氧化层35、栅极36以及多个多晶场板37，氧化层35在第一方向上位于第一阱区31、第二阱区33、多个掺杂区32以及截止环区34的远离衬底1的一侧上，且覆盖第一阱区31、第二阱区33的一部分、多个掺杂区32以及截止环区34的一部分；具体地，氧化层35包括第一氧化层351以及第二氧化层352，第一氧化层351在第一方向上位于第一阱区31、多个掺杂区32和截止环区34的远离衬底1的一侧且沿第二方向连续延伸，第一氧化层351为场氧层，第一氧化层351的在第一方向上远离衬底1的一侧上设有第二栅极部362和多个多晶场板37，第一氧化层351覆盖第一阱区31、多个掺杂区32以及截止环区34的一部分。
第二氧化层352为栅氧，第二氧化层352在第一方向上位于第二阱区33的远离衬底1的一侧，且位于第二阱区33与第一栅极部361之间；第二氧化层352与第一氧化层351连接，其中，第一氧化层351的厚度大于第二氧化层352的厚度。可以理解的是，由于第一氧化层351是场氧层，场氧层更厚可以承受更高的击穿电压；而第二氧化层352是栅氧，栅氧较厚则会导致阈值电压过大，甚至可能导致半导体器件无法开启。
以及，栅极36包括互相连接的第一栅极部361和第二栅极部362，第一栅极部361在第一方向上位于氧化层35的远离衬底1的一侧；多个多晶场板37在第一方向上位于氧化层35的远离衬底1的一侧，多个多晶场板37在第二方向上与第二栅极36间隔设置且彼此间隔设置。其中，多个多晶场板37与栅极36所采用的材料相同。
如图2所示，半导体器件的终端结构10还包括防护层，防护层在第一方向上位于场限环结构3的远离衬底1的一侧。具体地，防护层包括第三氧化层41以及有源区金属42。其中，2中未示出防护层。
其中，第三氧化层41在第一方向上位于第二阱区33、栅极36、第一氧化层351、多个多晶场板37以及截止环区34的远离衬底1的一侧并沿第二方向连续延伸，用于覆盖第二阱区33的一部分、栅极36、第一氧化层351、多个多晶场板37以及截止环区34的一部分；有源区金属42包括第一有源区金属部421和第二有源区金属部422，第一有源区金属部421和第二有源区金属部422连接，第一有源区金属部421在第一方向上位于第二阱区33的远离衬底1的一侧，第二有源区金属部422在第一方向上位于第三氧化层41的远离衬底1的一侧。其中，第二有源区金属部422的作用是作为金属场板，通过设置该金属场板能够降低主结也就是第二阱区33处的电场。
如图2所示，半导体器件的终端结构10还包括：截止环金属43，截止环金属43包括第一截止环金属部431和第二截止环金属部432，第一截止环金属部431与第二截止环金属部432连接，第一截止环金属部431在第一方向上位于第三氧化层41的远离衬底1的一侧，第一截止环金属部431在第二方向上与第二有源区金属部422间隔开，第二截止环金属部432在第一方向上位于截止环区34的远离衬底1的一侧，第二截止环金属部432的远离有源区20的侧面与截止环区34的远离有源区20的侧面平齐。
本申请的实施例还提出一种半导体器件，如图6所示，为根据本申请一个实施例的半导体器件的框图，其中，半导体器件100包括有源区20和根据上面实施例的半导体器件的终端结构10，半导体器件的终端结构10环绕有源区20设置。具体地，可参考图3和图4理解本申请实施例的半导体器件100，此处不再进行赘述。
根据本申请实施例的半导体器件100，通过采用上面实施例的半导体器件的终端结构10环绕所述有源区20设置，能够改善表面掺杂和表面电场分布，还能降低电场峰值和漏电，提升半导体器件100的效率。形成的上述半导体器件的终端结构10的尺寸整体较小，从而使得在相同的半导体器件的终端结构10尺寸时获得更高的耐压，对于相同的半导体器件100，小尺寸的半导体器件的终端结构10能够为芯片的有源区20预留出更多的空间，减少半导体器件的终端结构10所占芯片面积的比例。
本申请的实施例还提出一种功率模块，如图7所示，为根据本申请一个实施例的功率模块的框图，其中，功率模块200包括根据上面实施例的半导体器件100。
根据本申请实施例提出的功率模块200，包括上面实施例的半导体器件100，通过改进半导体器件100的结构，实现提升半导体器件100的效率和奶也，进而能够提升功率模块200的效率和耐压。
本申请的实施例还提出一种电力电子器件，如图8所示，为根据本申请一个实施例的电力电子器件的框图，其中，电力电子器件2000包括根据上面实施例的功率模块200。
根据本申请实施例提出的电力电子器件2000，通过采用采用上面实施例的功率模块200，通过提升半导体器件100的效率，能够提升功率模块200的效率和耐压，进而能够有效提升电力电子器件2000的效率和性能。
本申请的实施例还提出一种车辆，如图9所示，为根据本申请一个实施例的车辆的框图，其中，车辆1000包括根据上面实施例的半导体器件100。
根据本申请实施例提出的车辆1000，通过采用上面实施例的半导体器件100，通过提升半导体器件100的效率，能够提升整车的性能和整车中的电路结构的耐压，进而提升车辆1000的安全性。
在本申请的一些实施例中，还提出一种用于制造半导体器件的终端结构的方法，具体地，可结合图10理解本申请实施例的半导体器件的终端结构的制备过程；图10为根据本申请一个实施例的半导体器件的终端结构的制备过程的示意图。
首先，在第一导电类型的衬底1上形成第一导电类型的外延层2，外延层2在第一方向上位于衬底1上。
具体地，可先提供第一导电类型的衬底1，第一导电类型为P型，本申请实施例的结构及制造方法适用于Si、SiC等可以用来制备功率器件的材料。可选用单晶硅做衬底1，并选用(100)/(001)面进行后续工艺。对衬底1进行表面清洁去除杂质颗粒，外延生长一定厚度的第一导电类型层也就是外延层2，外延层2厚度为80-120μm，剂量在1e13-1e14/cm3，根据耐压需求而定。
然后，在外延层2的远离衬底1的区域中形成环绕有源区的场限环结构3。
该步骤具体包括：在外延层2的远离衬底1的区域中，形成第二导电类型的第一阱区31；以及在第一阱区31内形成沿与第一方向垂直的第二方向上间隔排布的多个第一导电类型的掺杂区32。
如图10所示，第二导电类型为N型，可采用离子注入的方式，在上述外延层2中形成第一阱区31。在外延层2的远离衬底1的区域中，形成第二导电类型的第一阱区31，包括：在外延层2的在第一方向上远离衬底1的表面上进行第二导电类型的离子注入并进行高温推结，以形成第二导电类型的第一阱区31。具体地，在终端进行第二导电类型离子注入来形成与外延层2不同导电类型的阱结构也就是第一阱区31，注入计量1e12～4e12，并进行115℃/180min高温推结。
进一步地，如图11所示，为根据本申请另一个实施例的半导体器件的终端结构的制备过程的示意图。在第一阱区31内形成沿与第一方向垂直的第二方向上间隔排布的多个第一导电类型的掺杂区32，包括：在第一阱区31内的多个间隔开的注入区域中，进行第一导电类型的离子注入，并进行高温推结，以形成多个第一导电类型的掺杂区32。以及，还包括：在外延层2的在第二方向上远离有源区的端部进行离子注入以形成截止环区34。
具体地，如图11所示，在上述外延层2的表面淀积阻挡层并刻蚀，阻挡层可以为光刻胶。第一阱区31表面阻挡层形成从有源区20向场限环结构3方向间距逐渐减小的注入窗口，或者形成等间距注入窗口，或者形成从有源区20向场限环结构3方向间距逐渐增大的注入窗口，并进行第一导电类型离子注入，在第一阱区31内形成第一导电类型区，并进行推结形成多个第一导电类型的掺杂区32和截止环区34。其中，注入计量为9e12～3e13，并进行105℃-115℃/180-360min高温推结，其中，推结温度可选用115℃。
进一步地，在一些实施例中，相邻的两个掺杂区32之间的间距满足公式(1-1)，其中，Na为掺杂区32的掺杂浓度；Wa为掺杂区32的宽度，Nd为第一阱区31的掺杂浓度，Wd为相邻的两个掺杂区32之间的距离，i为第i个掺杂区32，n为掺杂区32的总数量为n。
根据本申请实施例提出的用于制造半导体器件的终端结构的方法，通过在场限环结构中，制备第二导电类型的第一阱区与多个第一导电类型的掺杂区组合，相当于引入了掺杂浓度的不同导电类型柱交替排列，利用电荷补偿原理，使得不同导电类型柱能够很好的耗尽，从而能够改善表面掺杂和表面电场分布，降低电场峰值和漏电，提升终端结构的效率，还能有效减小终端结构的尺寸，从而使得在相同的终端结构尺寸时获得更高的耐压，对于相同的半导体器件，小尺寸的终端结构能够为芯片的有源区预留出更多的空间，减少终端结构所占芯片面积的比例。
此外，通过在场限环结构中的外延层中设置第一阱区，第一阱区能够抵消掉一部分外延层的电场，从而能够降低外延层掺杂对电荷补偿区电荷平衡的影响，进一步提升了终端结构的耐压。
在本申请的一些实施例中，如图12所示，为根据本申请又一个实施例的半导体器件的终端结构的制备过程的示意图。其中，在外延层2的远离衬底1的区域中形成环绕有源区的场限环结构3，还包括：在第一阱区31、多个掺杂区32以及截止环区34的远离衬底1的一侧上形成氧化层35，氧化层35覆盖第一阱区31、外延层2的一部分、多个掺杂区32以及截止环区34的一部分。
具体地，在第一阱区31、多个掺杂区32以及截止环区34的远离衬底1的一侧上形成氧化层35，包括：在多个掺杂区32和截止环区34的远离衬底1的一侧形成沿第二方向连续延伸的第一氧化层351。第一氧化层351覆盖第一阱区31、多个掺杂区32以及截止环区34的一部分。以及在外延层2的靠近有源区20且远离衬底1的一侧形成第二氧化层352，且第二氧化层352与第一氧化层351连接。其中，第二氧化层352的厚度小于第一氧化层351的厚度。
进一步地，在氧化层35的远离衬底1的一侧形成栅极36；以及在氧化层35的远离衬底1的一侧形成多个多晶场板37，多个多晶场板37在第二方向上与栅极36间隔设置且彼此间隔设置。在氧化层35的远离衬底1的一侧形成栅极36，包括：在第二氧化层352的远离衬底1的一侧形成第一栅极部361；以及在第一氧化层351的远离衬底1的一侧上形成第二栅极部362。在第一氧化层351的远离衬底1的一侧上形成多个多晶场板37。
具体地，在氧化层35的上表面淀积和刻蚀多晶硅，形成栅极36和多个多晶场板37，多个多晶场板37的位置在多个掺杂区32左边界两边。
在另一些实施例中，在外延层2的远离衬底1的区域中形成环绕有源区的场限环结构3，还包括在第二氧化层352靠近衬底1的表面、外延层2的远离衬底1的表面上且在第一阱区31的靠近有源区的一侧，进行第二导电类型的离子注入来形成第二导电类型的第二阱区33，第二阱区33与第一阱区31连接。具体地，在半导体器件的终端结构10中进行第二导电类型离子注入来形成与外延层2不同导电类型的阱结构也就是第二阱区33，注入计量为1e13～1e14，并进行115℃/105min高温推结。
在本申请的一些实施例中，可结合图2理解本申请实施例中的关于第三氧化层41、有源区金属42和截止环金属43的制备过程。
具体地，用于制造半导体器件的终端结构的方法还包括在第二阱区33、栅极36、氧化层35、多个多晶场板37以及截止环区34的远离衬底1的一侧形成沿第二方向连续延伸的第三氧化层41，第三氧化层41用于覆盖第二阱区33的一部分、栅极36、氧化层35、多个多晶场板37以及截止环区34的一部分；以及在第二阱区33的远离衬底1的一侧形成第一有源区金属部421，在第三氧化层41的远离衬底1的一侧形成第二有源区金属部422，第一有源区金属部421和第二有源区金属部422连接。
进一步地，用于制造半导体器件的终端结构的方法还包括在第三氧化层41的远离衬底1的一侧和截止环区34的远离衬底1的一侧形成截止环金属43，最终形成如图2中示出的半导体器件的终端结构10。
基于以上，根据本申请实施例提出的用于制造半导体器件的终端结构的方法，制备出的半导体器件的终端结构10，利用电荷补偿原理，制备的第一阱区31和掺杂区32形成了交替排列的P柱和N柱，在阻断状态下，P柱和N柱的电荷互相耗尽，电场分布由传统器件结构中的三角分布变为矩形分布，进而有效改善电场分布、降低电场尖峰。以及，通过增加第一阱区31，降低了外延层2掺杂对电荷补偿区电荷平衡的影响，进一步提升了半导体器件的终端结构10的耐压，并在提高半导体器件的终端结构10耐压的同时减少半导体器件的终端结构10所占芯片面积的比例。
根据本申请实施例的车辆1000、半导体器件100和半导体器件的终端结构10的其他构成以及操作对于本领域普通技术人员而言都是已知的，这里不再详细描述。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示意性实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。
尽管已经示出和描述了本申请的实施例，本领域的普通技术人员可以理解：在不脱离本申请的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本申请的范围由权利要求及其等同物限定。

Claims (33)

  1. 一种半导体器件的终端结构，其中，包括：
    第一导电类型的衬底(1)；
    第一导电类型的外延层(2)，所述外延层(2)在第一方向上位于所述衬底(1)上；以及
    场限环结构(3)，所述场限环结构(3)在所述第一方向上位于所述外延层(2)中，所述场限环结构(3)环绕有源区(20)设置，所述场限环结构(3)包括第二导电类型的第一阱区(31)，所述第一阱区(31)内设有多个第一导电类型的掺杂区(32)，所述多个第一导电类型的掺杂区(32)沿与所述第一方向垂直的第二方向间隔排布。
  2. 根据权利要求1所述的半导体器件的终端结构，其中，
    多个所述第一导电类型的掺杂区(32)分别为环绕整个所述有源区(20)的环形掺杂区。
  3. 根据权利要求1所述的半导体器件的终端结构，其中，每个所述第一导电类型的掺杂区(32)环绕所述有源区(20)设置，且每个所述第一导电类型的掺杂区(32)包括多个彼此间隔设置的第一导电类型的子掺杂区。
  4. 根据权利要求3所述的半导体器件的终端结构，其中，所述第一导电类型的子掺杂区为第一导电类型的柱形子掺杂区。
  5. 根据权利要求1-4中任一项所述的半导体器件的终端结构，其中，
    在所述第二方向上，多个所述第一导电类型的掺杂区(32)中的相邻的所述掺杂区(32)之间的距离相等；或者
    在所述第二方向上，多个所述第一导电类型的掺杂区(32)中的相邻的所述掺杂区(32)之间的距离沿远离所述有源区(20)的方向逐渐增大；或者
    在所述第二方向上，多个所述第一导电类型的掺杂区(32)中的相邻的所述掺杂区(32)之间的距离沿远离所述有源区(20)的方向逐渐减小。
  6. 根据权利要求1-5任一项所述的半导体器件的终端结构，其中，所述场限环结构(3)还包括：
    第二导电类型的第二阱区(33)，所述第二阱区(33)在所述第一方向上位于所述外延层(2)中，所述第二阱区(33)位于所述第一阱区(31)的靠近所述有源区(20)的一侧，所述第二阱区(33)与所述第一阱区(31)连接。
  7. 根据权利要求6所述的半导体器件的终端结构，其中，所述场限环结构(3)还包括：
    截止环区(34)，所述截止环区(34)位于所述外延层(2)的在所述第二方向上远离所述有源区(20)的端部且与所述第一阱区(31)间隔设置。
  8. 根据权利要求7所述的半导体器件的终端结构，其中，所述第一阱区(31)、所述第二阱区(33)、各个所述掺杂区(32)、所述截止环区(34)分别自其远离所述衬底(1)的表面沿靠近所述衬底(1)的方向延伸到所述外延层(2)中。
  9. 根据权利要求7或8所述的半导体器件的终端结构，其中，还包括：
    氧化层(35)，所述氧化层(35)在所述第一方向上位于所述第一阱区(31)、所述第二阱区(33)、多个所述掺杂区(32)以及所述截止环区(34)的远离所述衬底(1)的一侧上，且覆盖所述第一阱区(31)、所述第二阱区(33)的一部分、多个所述掺杂区(32)以及所述截止环区(34)的一部分。
  10. 根据权利要求9所述的半导体器件的终端结构，其中，还包括：
    栅极(36)，所述栅极(36)包括互相连接的第一栅极部(361)和第二栅极部(362)，所述第一栅极部(361)在所述第一方向上位于所述氧化层(35)的远离所述衬底(1)的一侧。
  11. 根据权利要求10所述的半导体器件的终端结构，其中，还包括：
    多个多晶场板(37)，多个所述多晶场板(37)在所述第一方向上位于所述氧化层(35)的远离所述衬底(1)的一侧，多个所述多晶场板(37)在所述第二方向上与所述第二栅极部(362)间隔设置且彼此间隔设置。
  12. 根据权利要求11所述的半导体器件的终端结构，其中，所述氧化层(35)包括：
    第一氧化层(351)，所述第一氧化层(351)在所述第一方向上位于所述第一阱区(31)、多个所述掺杂区(32)和所述截止环区(34)的远离所述衬底(1)的一侧且沿所述第二方向连续延伸，所述第一氧化层(351)的在所述第一方向上远离所述衬底(1)的一侧上设有所述第二栅极部(362)和所述多个多晶场板(37)，所述第一氧化层(351)覆盖所述第一阱区(31)、多个所述掺杂区(32)以及所述截止环区(34)的所述一部分。
  13. 根据权利要求12所述的半导体器件的终端结构，其中，所述氧化层(35)还包括：
    第二氧化层(352)，所述第二氧化层(352)与所述第一氧化层(351)连接，所述第二氧化层(352)在所述第一方向上位于所述第二阱区(33)的远离所述衬底(1)的一侧，且位于所述第二阱区(33)与所述第一栅极部(361)之间；
    其中，所述第一氧化层(351)的厚度大于所述第二氧化层(352)的厚度。
  14. 根据权利要求12所述的半导体器件的终端结构，其中，还包括：
    防护层，所述防护层在所述第一方向上位于所述场限环结构(3)的远离所述衬底(1)的一侧。
  15. 根据权利要求14所述的半导体器件的终端结构，其中，所述防护层包括：
    第三氧化层(41)，所述第三氧化层(41)在所述第一方向上位于所述第二阱区(33)、所述栅极(36)、所述第一氧化层(351)、多个所述多晶场板(37)以及所述截止环区(34)的远离所述衬底(1)的一侧并沿所述第二方向连续延伸，用于覆盖所述第二阱区(33)的一部分、所述栅极(36)、所述第一氧化层(351)、多个所述多晶场板(37)以及所述截止环区(34)的一部分。
  16. 根据权利要求15所述的半导体器件的终端结构，其中，所述防护层还包括：
    有源区金属(42)，所述有源区金属(42)包括第一有源区金属部(421)和第二有源区金属部(422)，所述第一有源区金属部(421)和所述第二有源区金属部(422)连接，所述第一有源区金属部(421)在所述第一方向上位于所述第二阱区(33)的远离所述衬底(1)的一侧，所述第二有源区金属部(422)在所述第一方向上位于所述第三氧化层(41)的远离所述衬底(1)的一侧。
  17. 根据权利要求16所述的半导体器件的终端结构，其中，还包括：
    截止环金属(43)，所述截止环金属(43)包括第一截止环金属部(431)和第二截止环金属部(432)，所述第一截止环金属部(431)与所述第二截止环金属部(432)连接，所述第一截止环金属部(431)在所述第一方向上位于所述第三氧化层(41)的远离所述衬底(1)的一侧，所述第一截止环金属部(431)在所述第二方向上与所述第二有源区金属部(422)间隔开，所述第二截止环金属部(432)在所述第一方向上位于所述截止环区(34)的远离衬底(1)的一侧，所述第二截止环金属部(432)的远离所述有源区(20)的侧面与所述截止环区(34)的远离所述有源区(20)的侧面平齐。
  18. 一种半导体器件，其中，包括：
    有源区(20)；和
    根据权利要求1-17中任一项所述的半导体器件的终端结构(10)，所述半导体器件的终端结构(10)环绕所述有源区(20)设置。
  19. 一种功率模块，其中，包括根据权利要求18所述的半导体器件(100)。
  20. 一种电力电子器件，其中，包括根据权利要求19所述的功率模块(200)。
  21. 一种车辆，其中，包括根据权利要求18所述的半导体器件(100)。
  22. 一种用于制造半导体器件的终端结构的方法，其中，包括：
    在第一导电类型的衬底上形成第一导电类型的外延层，所述外延层在第一方向上位于所述衬底上；
    在所述外延层的远离所述衬底的区域中形成环绕有源区的场限环结构，包括：
    在所述外延层的远离所述衬底的区域中，形成第二导电类型的第一阱区；以及
    在所述第一阱区内形成沿与所述第一方向垂直的第二方向上间隔排布的多个第一导电类型的掺杂区。
  23. 根据权利要求22所述的用于制造半导体器件的终端结构的方法，其中，在所述外延层的远离所述衬底的区域中，形成第二导电类型的第一阱区，包括：
    在所述外延层的在所述第一方向上远离所述衬底的表面上进行第二导电类型的离子注入并进行高温推结，以形成所述第二导电类型的第一阱区。
  24. 根据权利要求22或23所述的用于制造半导体器件的终端结构的方法，其中，在所述第一阱区内形成沿与所述第一方向垂直的所述第二方向上间隔排布的多个第一导电类型的掺杂区，包括：
    在所述第一阱区内的多个间隔开的注入区域中，进行第一导电类型的离子注入，并进行高温推结，以形成多个第一导电类型的掺杂区。
  25. 根据权利要求22-24任一项所述的用于制造半导体器件的终端结构的方法，其中，相邻的两个所述掺杂区之间的间距满足：
    其中，Na为所述掺杂区的掺杂浓度；Wa为所述掺杂区的宽度，Nd为所述第一阱区的掺杂浓度，Wd为相邻的两个所述掺杂区之间的距离，i为第i个掺杂区，n为所述掺杂区的总数量为n。
  26. 根据权利要求22-25任一项所述的用于制造半导体器件的终端结构的方法，其中，在所述外延层的远离所述衬底的区域中形成环绕有源区的场限环结构，还包括：
    在所述外延层的在所述第二方向上远离所述有源区的端部进行离子注入以形成截止环区。
  27. 根据权利要求26所述的用于制造半导体器件的终端结构的方法，其中，在所述外延层的远离所述衬底的区域中形成环绕有源区的场限环结构，还包括：
    在所述第一阱区、多个所述掺杂区以及所述截止环区的远离所述衬底的一侧上形成氧化层，所述氧化层覆盖所述第一阱区、所述外延层的一部分、多个所述掺杂区以及所述截止环区的一部分；
    在所述氧化层的远离所述衬底的一侧形成栅极；以及
    在所述氧化层的远离所述衬底的一侧形成多个多晶场板，多个所述多晶场板在所述第二方向上与所述栅极间隔设置且彼此间隔设置。
  28. 根据权利要求27所述的用于制造半导体器件的终端结构的方法，其中，在所述第一阱区、多个所述掺杂区以及所述截止环区的远离所述衬底的一侧上形成氧化层，包括：
    在多个所述掺杂区和所述截止环区的远离所述衬底的一侧形成沿所述第二方向连续延伸的第一氧化层；以及
    在所述外延层的靠近所述有源区且远离所述衬底的一侧形成第二氧化层，所述第二氧化层与所述第一氧化层连接。
  29. 根据权利要求28所述的用于制造半导体器件的终端结构的方法，其中，在所述氧化层的远离所述衬底的一侧形成栅极，包括：
    在所述第二氧化层的远离所述衬底的一侧形成第一栅极部；以及
    在所述第一氧化层的远离所述衬底的一侧上形成第二栅极部，所述第一氧化层覆盖所述第一阱区、多个所述掺杂区以及所述截止环区的所述一部分，其中，所述第一氧化层的厚度大于所述第二氧化层的厚度。
  30. 根据权利要求29所述的用于制造半导体器件的终端结构的方法，其中，在所述外延层的远离所述衬底的区域中形成环绕有源区的场限环结构，还包括：
    在所述第一氧化层的远离所述衬底的一侧上形成多个多晶场板。
  31. 根据权利要求30所述的用于制造半导体器件的终端结构的方法，其中，在所述外延层的远离所述衬底的区域中形成环绕有源区的场限环结构，还包括：
    在所述第二氧化层靠近所述衬底的表面、所述外延层的远离所述衬底的表面上且在所述第一阱区的靠近所述有源区的一侧，进行第二导电类型的离子注入来形成第二导电类型的第二阱区，所述第二阱区与所述第一阱区连接。
  32. 根据权利要求31所述的用于制造半导体器件的终端结构的方法，其中，还包括：
    在所述第二阱区、所述栅极、所述氧化层、多个所述多晶场板以及所述截止环区的远离所述衬底的一侧形成沿所述第二方向连续延伸的第三氧化层，所述第三氧化层用于覆盖所述第二阱区的一部分、所述栅极、所述氧化层、多个所述多晶场板以及所述截止环区的一部分；以及
    在所述第二阱区的远离所述衬底的一侧形成第一有源区金属部，在所述第三氧化层的远离所述衬底的一侧形成第二有源区金属部，所述第一有源区金属部和所述第二有源区金属部连接。
  33. 根据权利要求32所述的用于制造半导体器件的终端结构的方法，其中，还包括：
    在所述第三氧化层的远离所述衬底的一侧和所述截止环区的远离衬底的一侧形成截止环金属。
PCT/CN2025/081061 2024-06-28 2025-03-06 半导体器件的终端结构及其制造方法、半导体器件、功率模块、电力电子器件和车辆 Pending WO2026001070A1 (zh)

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CN202839619U (zh) * 2012-09-28 2013-03-27 中国科学院微电子研究所 一种高压半导体器件及其终端
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CN202839619U (zh) * 2012-09-28 2013-03-27 中国科学院微电子研究所 一种高压半导体器件及其终端
CN109346512A (zh) * 2018-11-15 2019-02-15 江苏捷捷微电子股份有限公司 一种半导体器件的终端结构及其制造方法
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