Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32431—Constructional details of the reactor
  • H01J37/32715—Workpiece holder
  • H01J37/32724—Temperature
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32917—Plasma diagnostics
  • H01J37/32935—Monitoring and controlling tubes by information coming from the object and/or discharge
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
  • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
  • H10P72/0602—Temperature monitoring
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
  • H10P95/90—Thermal treatments, e.g. annealing or sintering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
  • H01J2237/32—Processing objects by plasma generation
  • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
  • H01J2237/334—Etching

Definitions

• the present invention relates to a plasma processing apparatus.
• etching is performed on so-called multilayer films, which are made up of multiple films stacked on top of each other and formed on the surface of a plate-shaped sample such as a semiconductor wafer (hereinafter simply referred to as a "wafer").
• a wafer a plate-shaped sample such as a semiconductor wafer
• the sample stage of a plasma processing device has a built-in heater, and when processing wafers, the temperature is adjusted to an appropriate temperature for processing, thereby improving processing accuracy.
• Patent Document 1 is an example of a conventional technique for arranging a heater in a plasma processing apparatus such as the one described above and adjusting the temperature to a level suitable for wafer processing.
• Patent Document 1 aims to provide a temperature control device, a temperature control method, and an inspection device that can accurately estimate and control the temperature of a temperature-controlled object even when the object generates heat.
• a temperature control device that controls the temperature of a temperature-controlled object includes a heating mechanism having a heat source that heats the object, a temperature measuring device that measures the temperature in the vicinity of the object, a temperature estimation unit that dynamically estimates the temperature of the object based on the power input to the heat source, the power supplied to the object, and the temperature in the vicinity, and a temperature controller that controls the power input to the heat source based on the estimated temperature of the object.
• a temperature controller that controls the power input to the heat source based on the estimated temperature of the object.
• an LED heating mechanism is placed on the sample stage, and a cooling mechanism (refrigerant flow path) is built into the sample stage.
• the device also includes a temperature controller and a temperature estimation unit (observer).
• the temperature estimation unit is placed because, due to structural issues with the device, it is difficult to directly measure the temperature of the wafer placed on the sample stage. Therefore, the temperature near the wafer is measured and the temperature estimation unit estimates the wafer temperature.
• the temperature controller controls the heat output of the LED heating mechanism and the cooling amount of the cooling mechanism (opening and closing the valve in the refrigerant flow path) so that this estimated wafer temperature remains constant at the target temperature.
• Patent Document 2 discloses the following as an invention related to a wafer temperature control apparatus, a control method for a wafer temperature control apparatus, and a program for a wafer temperature control apparatus: "To provide a wafer temperature control apparatus that can estimate a wafer temperature with sufficient accuracy and control the wafer temperature to a target temperature even when a cooling operation amount input to a cooler is changed, the apparatus includes: a heater 1 that heats a wafer W in accordance with an input heating operation amount; a cooler 2 that cools the wafer W in accordance with an input cooling operation amount; a proximity temperature measuring device 3 that measures a temperature in the vicinity of the wafer W; a temperature estimation observer 4 that estimates a wafer temperature based on the proximity temperature measured by the proximity temperature measuring device 3 and the cooling operation amount input to the cooler 2 or the cooling amount output by the cooler; and a temperature controller 5 that controls the cooling operation amount so as
• an object of the present invention is to provide a technique that can estimate the temperature of a wafer for each region and control it with high precision.
• one representative plasma processing apparatus of the present invention comprises a processing chamber disposed within a vacuum vessel in which plasma for processing a wafer to be processed is generated; a sample stage disposed within the processing chamber and on whose upper surface the wafer is placed; a plurality of heaters disposed in multiple regions within a dielectric film disposed within the sample stage and covering the upper surface of a substrate having a disk or cylindrical shape; a coolant flow path disposed within the substrate and temperature sensors disposed at a first plurality of locations between the coolant flow path and the upper surface of the substrate; and a control unit that estimates the temperature or heat transfer coefficient of the wall surface of the coolant flow path at a second plurality of locations using the output from the temperature sensor and the coolant temperature, estimates the temperature of the wafer at a third plurality of locations using the estimated temperature or heat transfer coefficient of the wall surface of the coolant flow path and the output of the temperature sensor, and controls the operation of the plurality of heaters using the estimated wafer temperature so that the wafer reaches
• the wafer temperature can be estimated for each region and controlled with high precision.
• FIG. 1 is a cross-sectional view schematically showing the configuration of a plasma processing apparatus according to an embodiment of the present invention.
• FIG. 2 is a cross-sectional view schematically showing a part of the configuration of the sample stage of the plasma processing apparatus shown in FIG.
• FIG. 3 is a diagram showing an example of a correspondence relationship between a coolant flow path inside a substrate, a heater film, and a location where the wafer temperature is estimated.
• FIG. 4 is a data flow diagram showing a processing sequence for controlling the temperature of a wafer.
• FIG. 5 is a block diagram showing another example of a processing sequence for controlling the temperature of a wafer.
• upper or “top” refers to the vertically upward direction when a component is placed horizontally.
• upper and its opposite, “lower”(”lower”) are sometimes referred to as the “positive z-axis direction” and the “negative z-axis direction,” and the horizontal direction is sometimes referred to as the "x-axis direction,” the “y-axis direction,” the “xy plane direction,” etc.
• the flat surface of a member that is located above the other member and faces upward is referred to as the "upper surface.”
• the flat surface of a member that is located below the other member and faces downward is referred to as the "lower surface.”
• surfaces of the members that extend in the vertical direction are referred to as "side walls,”"wallsurfaces,””side wall surfaces,” etc.
• FIG. 1 is a cross-sectional view schematically illustrating the configuration of a plasma processing apparatus according to an embodiment of the present invention.
• the plasma processing apparatus 100 includes a processing chamber 104 disposed within a vacuum vessel 101, in which plasma for processing a wafer 109 to be processed is generated, and a sample stage 120 disposed within the processing chamber 104 and on whose upper surface the wafer 109 is placed.
• the sample stage 120 also includes a dielectric film (201, 203) covering the upper surface of a disk- or cylindrical-shaped substrate 108.
• the sample stage 120 also includes a plurality of heaters (heater film 204) disposed in multiple regions within the dielectric film.
• the substrate 108 also includes a coolant flow path 152 disposed within the substrate 108, and temperature sensors 202 disposed at first multiple locations between the coolant flow path 152 and the upper surface of the substrate 108. Then, the control unit (170, 171) estimates the temperature or heat transfer coefficient of the wall surface of the coolant flow path 152 at a second plurality of locations using the output from the temperature sensor 202 and the temperature of the coolant, and estimates the temperature of the wafer 109 at a third plurality of locations using the estimated temperature or heat transfer coefficient of the coolant flow path 152 and the output of the temperature sensor 202. Furthermore, the control unit (170, 171) controls the operation of the plurality of heaters (heater films 204) using the estimated temperature of the wafer 109 so that the wafer 109 reaches a target temperature.
• the control unit (170, 171) controls the operation of the plurality of heaters (heater films 204) using the estimated temperature of the wafer 109 so that the wafer 109 reaches a target temperature.
• Plasma processing apparatus 100 is controlled by personal computer 170 and PLC (Programmable Logic Controller) 171.
• Personal computer 170 sets the processing sequence for plasma processing apparatus 100 and sends the set processing sequence and processing conditions to PLC 171.
• PLC 171 sends control signals to the components of plasma processing apparatus 100 to operate in accordance with the processing sequence. Note that while personal computer 170 and PLC 171 are described separately in this disclosure, this disclosure is not limited to this case. It is also possible to apply a configuration that realizes the functions of personal computer 170 and PLC 171 to control unit 172. This is explained in detail below.
• Figure 1 shows a plasma etching apparatus that uses a microwave electric field as the electric field for forming plasma, generates ECR (Electron Cyclotron Resonance) between the microwave electric field and magnetic field to form plasma, and uses the plasma to etch a plate-shaped sample such as a semiconductor wafer. While the case of a plasma etching apparatus will be described here, the present disclosure is not limited to plasma etching apparatuses and can also be applied to processing apparatuses that perform processes other than plasma etching.
• ECR Electro Cyclotron Resonance
• the plasma processing apparatus 100 has a vacuum vessel 101 equipped with a processing chamber 104 inside where plasma is formed.
• the vacuum vessel 101 has a cylindrical shape with an open top, and a dielectric window 103 (made of quartz, for example) for introducing microwaves is arranged at the top as a lid member, forming the processing chamber 104 with an airtight partition between the inside and outside.
• a vacuum exhaust port 110 is disposed at the bottom of the vacuum vessel 101, and the vacuum vessel 101 is connected to a vacuum exhaust device (not shown) disposed below the vacuum vessel 101.
• a shower plate 102 which forms the ceiling surface of the processing chamber 104, is provided below the underside of a dielectric window 103 that forms the upper lid member of the vacuum vessel 101.
• the shower plate 102 has multiple gas introduction holes 102a disposed in the center, and etching process gas is introduced into the processing chamber 104 through these multiple gas introduction holes 102a.
• the shower plate 102 is a disk made of a dielectric material such as quartz.
• an electric field/magnetic field generating unit 160 is disposed above the exterior of the vacuum vessel 101, generating an electric field and a magnetic field for generating plasma 116.
• a waveguide 105 is disposed between the electric field/magnetic field generating unit 160 and the processing chamber 104.
• the waveguide 105 is disposed above the dielectric window 103, and transmits an electric field of a predetermined frequency generated in the electric field/magnetic field generating unit 160, supplying it to the processing chamber 104.
• the electric field transmitted inside the waveguide 105 is generated by oscillation in the electric field generating power supply 106.
• the frequency of the electric field is not particularly limited, but in this embodiment, microwaves of 2.45 GHz are used.
• the magnetic field generating coil 107 that forms the magnetic field is positioned above the dielectric window 103, at a position that surrounds the side wall of the vacuum vessel 101 and the outer periphery of the lower end of the waveguide 105.
• the electric field generated by the electric field generating power supply 106 propagates inside the waveguide 105, passes through the dielectric window 103 and shower plate 102, and is supplied to the processing chamber 104.
• the interaction between the magnetic field and electric field generated by the magnetic field generating coil 107 and supplied into the processing chamber 104 causes ECR (Electron Cyclotron Resonance).
• high-density plasma 116 is generated in the processing chamber 104 by exciting and dissociating atoms or molecules of the processing gas introduced into the processing chamber 104 through the gas introduction holes 102a of the shower plate 102.
• the sample stage 120 which functions as a wafer mounting electrode, is provided below the processing chamber 104, in other words, below the space where the plasma 116 is formed.
• the sample stage 120 has a mounting surface 120a on which a wafer 109, which is the sample (object to be processed), is mounted.
• the mounting surface 120a of the sample stage 120 faces the shower plate 102 or the dielectric window 103.
• the sample stage 120 is covered with a dielectric film 140 that forms the mounting surface 120a.
• the conductive film 111 is an element that forms the mounting surface 120a of the sample stage 120, and is a film-like electrostatic attraction electrode to which DC power is supplied to generate electrostatic force for wafer attraction.
• the conductive film 111 may be bipolar, in which one of the multiple film-like electrodes has a different polarity from the other, or unipolar, in which the same polarity is given, but in this embodiment it is shown as unipolar.
• a high-frequency power supply 124 and a matcher 129 are disposed closer to the conductive film 111 than the high-frequency filter 125.
• the high-frequency power supply 124 and the matcher 129 are connected to a conductive electrode substrate (hereinafter simply referred to as "substrate") 108 having a circular or cylindrical shape and disposed inside the sample stage 120.
• the high-frequency power supply 124 is connected to the ground 112.
• High-frequency power of a predetermined frequency is supplied from the high-frequency power supply 124 to the substrate 108, and a bias potential is formed above the wafer 109, which is attracted to and held on the mounting surface 120a of the sample stage 120, during processing of the wafer 109.
• the sample stage 120 has electrodes to which high-frequency power is supplied from the high-frequency power supply 124 while the plasma 116 is being generated. The electrodes for forming the bias potential will be described later.
• a refrigerant flow path 152 is arranged spirally or concentrically around the central axis, assuming that the central axis extends in the vertical direction of the substrate 108 or sample stage 120, inside the substrate 108.
• a cooling refrigerant for cooling the substrate 108 flows through this refrigerant flow path 152.
• a heater film 204 is provided on the sample stage 120, and power is supplied from the heater power supply 180 to heat the sample stage 120 (substrate 108).
• a recess 120d is arranged on the outer periphery of the upper part of the sample stage 120.
• a susceptor ring 113 which is a ring-shaped member made of a dielectric material such as quartz or ceramics such as alumina, is placed on the upper surface of the ring-shaped recess 120d, which is formed at a height lower than the mounting surface 120a of the sample stage 120.
• the upper surface of the susceptor ring 113 has dimensions that position it higher than the mounting surface 120a of the sample stage 120.
• the susceptor ring 113 is arranged on the outer periphery of the mounting surface 120a of the sample stage 120 and covers the surface of the sample stage 120.
• the susceptor ring 113 is configured to cover the upper surface of the recess 120d, the cylindrical side wall surface of the recess 120d, and the cylindrical side wall surface of the sample stage 120 below the recess 120d.
• the unprocessed wafer 109 is placed on the tip of the arm of a wafer transfer robot located in a vacuum transfer chamber, which is a vacuum chamber separate from the vacuum chamber 101.
• the vacuum transfer chamber is connected to the vacuum chamber 101, and the interior of the vacuum transfer chamber is depressurized to the same pressure as the processing chamber 104.
• a gate that defines a passage connecting the vacuum transfer chamber and the processing chamber 104 is opened by the operation of a valve located in the vacuum transfer chamber, and the unprocessed wafer 109 is transferred into the processing chamber 104 while placed on the tip of the arm of the robot.
• the wafer 109 is transported to above the mounting surface 120a of the sample stage 120 in the processing chamber 104, and is transferred onto the lift pins (not shown) by the up and down movement of the lift pins. After being placed on the mounting surface 120a, the wafer 109 is attracted to and held on the mounting surface 120a of the sample stage 120 by the electrostatic force generated by DC power applied from the DC power supply 126.
• the etching process gas has its flow rate or speed adjusted by a mass flow controller (not shown) and is introduced into the space between the dielectric window 103 and the quartz shower plate 102. After diffusing within this space, it is introduced into the processing chamber 104 through the gas inlet holes 102a in the shower plate 102.
• the vacuum exhaust system then operates to exhaust gas and particles from the processing chamber 104 through the vacuum exhaust port 110.
• the pressure within the processing chamber 104 is adjusted to a predetermined value within a range suitable for processing the wafer 109.
• a heat-conductive gas such as He (helium) is supplied from an opening (not shown) on the top surface of the dielectric film 140 into the gap between the wafer 109 and the top surface of the dielectric film 140, which is the mounting surface 120a of the sample stage 120, thereby promoting heat transfer between the wafer 109 and the sample stage 120.
• a refrigerant regulated to a temperature within a predetermined range circulates through the refrigerant flow path 152, thereby adjusting the temperature of the sample stage 120 or substrate 108 before the wafer 109 is placed on it.
• the temperature of the wafer 109 is adjusted to approach a temperature within the predetermined range before the etching process, and heat is transferred from the wafer 109 even after the etching process has begun, adjusting the temperature of the wafer 109.
• microwave electric and magnetic fields are supplied into the processing chamber 104, causing the gas to react and generate plasma 116.
• radio frequency (RF) bias power is supplied to the substrate 108 from the radio frequency power supply 124, creating a bias potential above the top surface of the wafer 109.
• Charged particles such as ions in the plasma 116 are attracted to the top surface of the wafer 109 in response to the potential difference between them. These charged particles then collide with a mask pre-positioned on the top surface of the wafer 109 and a film structure including the film layer to be processed, thereby performing the etching process.
• the etching gas introduced into the processing chamber 104 and reaction product particles generated during the etching process are exhausted from the vacuum exhaust port 110.
• high-frequency power is supplied from the high-frequency power source 127 to a conductor ring 131 located above the outer periphery of the sample stage 120 via a power supply connector 161 (described below) that is provided on the sample stage 120 and has an elastic conductive member.
• the AC high voltage generated by the radio frequency power supply 127 is introduced into a conductor ring 131 made of a conductive material and arranged inside the susceptor ring 113 via a load matcher 128 and a load impedance variable box 130.
• the load impedance variable box 130 which is adjusted to a suitable impedance value, combined with the relatively high impedance portion arranged above the susceptor ring 113, relatively reduces the impedance value for radio frequency power from the radio frequency power supply 127 through the substrate 108 to the outer edge of the wafer 109.
• the radio frequency power supply 127 is connected to ground 112. Note that the frequency of the radio frequency power supply 127 in this embodiment is preferably set to the same frequency as that of the radio frequency power supply 124 or a constant multiple thereof.
• the substrate 108 shown in FIG. 2 is made of a metallic material such as titanium, aluminum, or a compound thereof. It is electrically connected to the ground electrode S (not shown) and is conductively connected to the wall of the vacuum vessel 101 shown in FIG. 1, thereby being fixed to ground potential.
• the substrate 108 has a central upper surface 120b on which the wafer 109 is placed, and a recessed portion 120d arranged in a ring shape on the outer periphery of the upper surface 120b, surrounding the upper surface 120b and having a lower height than the upper surface 120b. Between the upper surface 120b and the recessed portion 120d is a stepped portion 120e that forms the outer sidewall of the upper surface 120b.
• a susceptor ring 113 is placed in the ring-shaped recessed portion 120d.
• the coolant flow path 152 has a spiral or concentric shape around the central axis ca of the substrate 108 (sample stage 120).
• the dielectric films (201, 203) are sprayed onto the upper surface 120b of the substrate 108, covering the upper surface 102e.
• a dielectric film 201 made of a dielectric material such as ceramics is disposed on the upper surface 102e of the substrate 108.
• a heater film 204 made of a film-like electrode made of a conductive material and consisting of multiple heaters that generate heat when supplied with DC power is disposed on top of the dielectric film 201, covering multiple areas of the upper surface 120b of the substrate 108.
• the dielectric film 201 is disposed on the upper surface 120b of the substrate 108, and a heater film 204 made of a film-like heater is further formed on top of this dielectric film 201.
• the sample stage 120 has a structure in which a heater film 204 surrounded by dielectric films 201 and 203 is disposed on the upper surface 102e of the substrate 108, and is further surrounded (covered) by a shielding film 205, a film-like conductive member disposed on the upper surface of the dielectric film 203, surrounding the upper and peripheral edges.
• the structure in which the heater film 204 is surrounded by the shielding film (conductor film) 205 is encapsulated by the dielectric material that constitutes part of the dielectric films 201 and 203.
• the shielding film 205 is electrically connected to the substrate 108, which fixes the shielding film 205 to the same ground potential as the substrate 108, thereby suppressing the inflow of high-frequency waves into the heater film 204.
• a dielectric film 206 is disposed on the upper surface of the shielding film 205, and an electrode film 207, which is an electrode for electrostatic attraction and an electrode to which high-frequency power for generating a high-frequency bias is supplied, is disposed on top of this dielectric material member.
• the electrode film 207 is a film made of a conductive material, and is connected to the high-frequency power supply 124, which supplies high-frequency power of a predetermined frequency.
• the electrode film 207 is also electrically connected to the DC power supply 126, and by applying a DC voltage, the wafer 109 placed on the mounting surface of the sample stage 120 can be attracted by electrostatic force.
• the electrode film 207 has the dual functions of generating a bias potential and electrostatically adsorbing the wafer and includes the conductive film 111 in FIG. 1, the present disclosure is not limited to this configuration. An electrode for generating a bias potential and an electrode for electrostatic adsorption may be provided separately.
• FIG. 3 is a diagram schematically illustrating an example of the correspondence between the coolant flow path 152, the heater film 204, and the wafer temperature estimation point 305 inside the substrate 108.
• the reason for dividing the coolant flow path 152 into regions 301, 302, 303, and 304 is that the results of thermal analysis revealed that the temperatures of the respective regions on the upper wall surface of the coolant flow path 152 differ.
• the heat transfer coefficients for heat transfer from the coolant contained in each of the coolant flow path regions 301, 302, 303, and 304 to the wafer 109 also vary. When used to control the temperature of the wafer 109, these heat transfer coefficients affect the control accuracy.
• Figure 3 shows the positional relationships of the wafer 109 (Figure 3(a)), heater film 204 (Figure 3(b)), and coolant flow path 152 (Figure 3(c)) extracted from the configuration related to the sample stage 120. All of these have a roughly circular shape and are arranged so that their central axes are in common. The common central axis is indicated as ca. As shown in the order of Figures 3(c) to 3(a), the coolant flow path 152 (inside the substrate 108 of the sample stage 120), heater film 204 (above the substrate 108), and wafer 109 (above the heater film 204) are arranged in this order.
• Figure 3(c) shows the results of a thermal analysis of the wall surface of refrigerant flow path 152, assuming that a refrigerant is flowing through refrigerant flow path 152.
• Refrigerant flow path 152 has a three-dimensional size in a spiral or concentric circle shape, and the results of the thermal analysis are shown projected onto the xy plane.
• temperature differences are indicated by color (hatching), and the temperatures and colors respectively follow the color bar shown in Figure 3(d).
• the refrigerant flows clockwise from the inlet 152i of the refrigerant flow path 152 along the outer periphery of the substrate 108 (the position farthest from the central axis ca), then reverses direction just before reaching the inlet 152i and flows counterclockwise at a position closer to the central axis ca. As it approaches the inlet 152i, it reverses direction again and flows clockwise at a position even closer to the central axis ca.
• the refrigerant flows in a circular motion from the outside of the substrate 108, changes direction, passes almost evenly throughout the substrate 108, and approaches the central axis ca, before flowing out of the substrate 108 from the outlet 152o of the refrigerant flow path 152.
• the temperature of the wall surface of the refrigerant flow path 152 is 2°C at the outermost part of the flow path from the inlet 152i, and changes to 9°C, 15°C, and 21°C as it approaches the central axis ca.
• the location where the wall temperature is 2°C is designated as region 301, the location where the wall temperature is 9°C is designated as region 302, the location where the wall temperature is 15°C is designated as region 303, and the location where the wall temperature is 21°C is designated as region 304.
• Thermal analysis enabled the wall temperatures of regions 301 to 304 (second multiple locations) of the refrigerant flow path 152 to be estimated.
• the refrigerant flow path 152 has been described as having its inlet located on the outer periphery of the substrate 108 and its outlet located in the center of the substrate 108, the present disclosure is not limited to this case. The present disclosure can be applied depending on the positions of the inlet and outlet of the refrigerant flow path 152. Furthermore, although the present disclosure has been described as having its temperature divided into four ranges, the present disclosure can also be applied when the temperature is divided into a number other than four.
• Figure 3(b) shows the heater film 204 projected onto the xy plane.
• the heater film 204 is divided into multiple regions, each labeled R1 to R13.
• region 301 of the refrigerant flow path 152 roughly corresponds to regions R1 to R4 of the heater film 204
• region 302 of the refrigerant flow path 152 roughly corresponds to regions R5 to R8 of the heater film 204.
• region 303 of the refrigerant flow path 152 roughly corresponds to regions R9 to R12 of the heater film 204
• region 304 of the refrigerant flow path 152 roughly corresponds to region R13 of the heater film 204.
• a case where the heater film 204 is divided into 13 regions is described, but the present disclosure is not limited to this case.
• the estimated locations 305 indicate locations where the temperature estimation unit 209 estimates the temperature of the wafer 109, and are ranges having a predetermined area. Compared to FIG. 3(b), the estimated locations 305-1 to 305-13 (third multiple locations) are located approximately in the center of each of the regions R1 to R13 of the heater film 204. Note that, although a case where there are 13 estimated locations 305 will be described, the present disclosure is not limited to this case. Locations other than 13 may also be used as estimated locations.
• the first plurality of locations are smaller than the second plurality of locations.
• the first plurality of locations are also smaller than the third plurality of locations.
• the range measured by the temperature sensors 202-1 to 202-3 arranged at the first plurality of locations is smaller than the range occupied by the second plurality of locations (regions 301 to 304 of the coolant flow path 152).
• the range measured by the temperature sensors 202-1 to 202-3 arranged at the first plurality of locations is also smaller than the range occupied by the third plurality of locations (locations 305-1 to 305-13 where the temperature of the wafer 109 is estimated).
• the temperature of the wall surface of the coolant flow path 152 differs for each of the regions 301 to 304, when considering the heat transfer between the coolant in the coolant flow path 152 and the estimated locations 305-1 to 305-13 on the wafer 109, it is preferable to set a heat transfer coefficient for each of the regions 301 to 304 of the coolant flow path 152 rather than using a single heat transfer coefficient.
• Example of wafer temperature control 4 is a data flow diagram showing the processing sequence for controlling the temperature of the wafer 109.
• the wall temperature or heat transfer coefficient of the second plurality of locations (regions 301 to 304) of the coolant flow path 152 is estimated using the output from the temperature sensor 202 and the coolant temperature.
• the estimated wall temperature or heat transfer coefficient of the coolant flow path 152 and the output from the temperature sensor 202 are used to estimate the temperature of the wafer 109 at a third plurality of locations (estimated locations 305-1 to 305-13 ).
• the estimated wafer 109 temperature is then used to control the operation of the heater (heater film 204) so that the wafer 109 reaches a target temperature.
• the wall temperature of the coolant flow path 152 is estimated using an observer.
• the observer estimates the temperature or heat transfer coefficient of the wall surface at a second plurality of locations in the coolant flow path 152 using at least one of the temperature of the inlet 152i of the coolant flow path 152, the temperature of the coolant, the thermal conductivity of the substrate 108 or the coolant, and the amount of current or power supplied to the heater (heater film 204).
• Step S1 the control and calculation unit 210 acquires a set value for the wafer temperature.
• the set value may be calculated by the control and calculation unit 210 based on the processing conditions, or may be specified by the user of the plasma processing apparatus 100.
• step S2 the control and calculation unit 210 calculates the temperature difference between the set value for the wafer temperature and the estimated value for the wafer temperature.
• step S3 the calculated temperature difference is converted into power (electric power) by the control and calculation unit 210.
• the PLC 171 controls the heater power supply 180 based on the converted power, causing the heater film 204 to generate heat. While the sample stage 120 is heated by the heater film 204, the temperature sensor 202 detects the temperature in the vicinity of the temperature sensor 202. The temperature sensor 202 mainly detects the heat generated by the heater film 204. At this time, the PLC 171 controls the supply of refrigerant to the refrigerant flow path 152.
• the temperature estimation unit 209 acquires information indicating the power based on the temperature difference (power related to the set temperature of the heater film 204) and the temperature in the vicinity of the temperature sensor 202, and estimates the wafer temperature and the temperature of the wall surface of the coolant flow path 152.
• the estimated wafer temperature is notified to the control and calculation unit 210, and is used to calculate the temperature difference in step S2.
• the control and calculation unit 210 calculates heat transfer coefficients h1 to hn from temperatures t1 to tn.
• the control and calculation unit 210 calculates parameters p1 to pn used in the calculation to estimate the wafer temperature in the temperature estimation unit 209.
• Parameters p1 to pn are sent to the temperature estimation unit 209, which updates the parameters.
• the processing sequence shown in Figure 4 is repeated at predetermined time intervals, for example, while the plasma etching process is being performed, to control the wafer temperature.
• the temperature estimation unit 209 estimates the wafer temperature using the nearby temperature, and also estimates the wall temperature of the divided area of the coolant flow path 152.
• the estimated wall temperature of the coolant flow path 152 is converted into heat transfer conditions or heat transfer coefficients, and the parameters of the temperature estimation unit 209 are updated.
• the parameters of the temperature estimation unit 209 calculated at the previous sampling time are used to estimate the wafer temperature and wall temperature of the coolant flow path 152 at the next sampling time.
• FIG. 5 is a block diagram showing another example of a processing sequence for controlling the temperature of wafer 109.
• the temperature of the wall surface of coolant flow path 152 is estimated using a Kalman filter.
• the example shown in FIG. 5 differs from the example shown in FIG. 4 in that the processing sequence is set by control calculation unit 210 in personal computer 170, while the function of temperature estimation unit 209 is executed by PLC 171.
• Figure 5 shows an example of calculating the heat transfer coefficient corresponding to each of regions 301, 302, 303, and 304, and controlling the wafer 109 to a target temperature.
• the personal computer 170 (particularly the control and calculation unit 210) sets the temperature at the inlet 152i of the refrigerant flow path 152 (TCR Temp Setting), the flow rate of the refrigerant flowing through the refrigerant flow path 152 (Massflow Setting), and the wafer temperature at a predetermined estimated point 305 on the wafer 109 (Temp Setting).
• the set values are sent to the PLC 171, which performs calculations within the PLC 171. Based on the results of calculations within the PLC 171, the PLC 171 operates the heater film 204 inside the sample stage (Plant) 120.
• the difference between the wafer temperature tw estimated by the PLC 171 and the wafer temperature (Temp Setting) set by the PC 170 is calculated and input to the PID controller 406.
• the PID control unit 406 calculates the amount of heat generated by the heater film 204 required to reduce the difference, and operates the heater film 204 of the sample stage 120 again based on this calculation result.
• the heat transfer coefficients for each of the regions 301 to 304 of the refrigerant flow path 152 are calculated using the estimated wall temperatures t1 to t4 of the refrigerant flow path 152 and the set refrigerant flow rate (Massflow Setting), and the model for estimating the wafer temperature is updated in real time (the parameters for the next sampling time are calculated using the previous sampling time). In this way, the accuracy of estimating the wafer temperature can be improved.
• dividing the regions of the refrigerant flow path 152 into four is one example. The number of regions that the refrigerant flow path 152 is not limited to four, and the more regions it is divided into, the higher the accuracy of the estimation model can be.
• the wafer temperature is estimated after the heat transfer coefficient is set according to the temperature distribution in the coolant flow path, so that the wafer temperature can be estimated for each region and controlled with high accuracy.
• a processing chamber disposed within the vacuum vessel in which plasma for processing a wafer to be processed is generated; a sample stage disposed in the processing chamber and on which the wafer is placed; a plurality of heaters arranged in a plurality of regions inside a dielectric film arranged to cover an upper surface of a substrate having a disk or a cylindrical shape inside the sample stage; a coolant flow path disposed within the substrate and temperature sensors disposed at a first plurality of locations between the coolant flow path and the upper surface of the substrate; a control unit that estimates the temperature or heat transfer coefficient of a wall surface of a second plurality of locations of the coolant flow path using the output from the temperature sensor and the temperature of the coolant, estimates the temperature of the wafer at a third plurality of locations using the estimated temperature or heat transfer coefficient of the wall surface of the coolant flow path and the output of the temperature sensor, and controls the operation of the plurality of heaters using
• Aspect 2 The plasma processing apparatus according to aspect 1, The plasma processing apparatus, wherein the first plurality of locations is smaller than the second plurality of locations.
• Aspect 3 The plasma processing apparatus according to aspect 1 or aspect 2, The plasma processing apparatus, wherein the first plurality of locations is smaller than the third plurality of locations.
• Aspect 4 The plasma processing apparatus according to any one of aspects 1 to 3, The control unit estimates the temperature of the wall surface of the coolant flow path using an observer.
• Aspect 5 The plasma processing apparatus according to any one of aspects 1 to 4, The control unit estimates the temperature of the wall surface of the coolant flow path using a Kalman filter.
• the plasma processing apparatus according to any one of aspects 1 to 5,
• the control unit estimates the temperature or heat transfer coefficient of the wall surface of the second plurality of locations of the coolant flow path using at least one of the temperature at the inlet of the coolant flow path, the temperature of the coolant, the thermal conductivity of the substrate or the coolant, and the amount of current or power supplied to the heater.
• the plasma processing apparatus according to any one of aspects 1 to 6,
• the dielectric film is formed by spraying onto the upper surface of the metal substrate to cover the upper surface.
• 100 Plasma processing apparatus, 101: Vacuum vessel, 102: shower plate, 103: Dielectric window, 104: Processing chamber, 105: Waveguide, 106: Electric field generating power supply, 107: Magnetic field generating coil, 108: Substrate, 109: Wafer, 110: Vacuum exhaust port, 111: Conductive film, 112: Ground, 113: Susceptor ring, 116: Plasma, 120: Sample stage, 124: High frequency power supply, 125: High frequency filter, 126: DC power supply, 127: High frequency power supply, 128: Matching box, 129: Matching box Detector, 130: Load impedance variable box, 131: Conductor ring, 140: Dielectric film, 152: Refrigerant flow path, 160: Magnetic field generating unit, 161: Power supply connector, 170: Personal computer, 171: PLC, 172: Control unit, 180: Heater power supply, 201: Dielectric film, 202: Temperature sensor, 203: Dielectric film,

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• 2024
  • 2024-03-11 CN CN202480006022.0A patent/CN120937120A/zh active Pending
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• 2025
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