Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs

Definitions

• This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.
• the etching conditions used to form the trench can sometimes deteriorate the condition of the gate insulating film above the trench.
• operating the semiconductor device can cause the gate insulating film above the trench to deteriorate, reducing the insulation reliability of the semiconductor device.
• This disclosure has been made in consideration of the above-mentioned problems, and aims to provide technology that can improve the insulation reliability of semiconductor devices.
• a first semiconductor device comprises a drift layer of a first conductivity type, a well region of a second conductivity type provided on the drift layer, an impurity region of the first conductivity type provided on the well region, an electrode provided on an insulating film inside a trench that extends from the top surface of the impurity region through the well region to the drift layer, and an interlayer insulating film provided on the electrode, wherein an insulating film end portion, which is an end portion of the insulating film facing the impurity region, and an electrode end portion, which is an end portion of the electrode facing the impurity region, are lower than the top surface of the impurity region, the trench includes an external trench in a termination region, and the interlayer insulating film provided on the electrode in the external trench is provided across the inside and outside of the external trench.
• a second semiconductor device comprises a drift layer of a first conductivity type, a well region of a second conductivity type provided on the drift layer, an impurity region of the first conductivity type provided on the well region, an electrode provided on an insulating film inside a trench that extends from the upper surface of the impurity region through the well region to the drift layer, and an interlayer insulating film provided on the electrode, wherein an insulating film end portion, which is an end portion of the insulating film facing the impurity region, and an electrode end portion, which is an end portion of the electrode facing the impurity region, are lower than the upper surface of the impurity region, and a recess is provided between the side surface of the trench and the upper surface of the impurity region in a cross-sectional view, and the interlayer insulating film covers at least a portion of the recess.
• the insulating film edge and the electrode edge are lower than the top surface of the impurity region. This configuration can improve the insulation reliability of the semiconductor device.
• FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a first modification of the first embodiment.
• 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a first modification of the first embodiment.
• FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a second modification of the first embodiment.
• FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a second modification of the first embodiment.
• FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment.
• FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment.
• FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to a first modification of the third embodiment.
• FIG. 10 is a plan view showing a configuration of a semiconductor device according to a fourth embodiment.
• FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment.
• FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment.
• FIG. 13 is a plan view showing a configuration of a semiconductor device according to a first modification of the fourth embodiment;
• FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to a first modification of the fourth embodiment.
• FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a fifth embodiment.
• a certain portion having a higher concentration than another portion may mean, for example, that the average concentration of the certain portion is higher than the average concentration of the other portion.
• a certain portion having a lower concentration than another portion may mean, for example, that the average concentration of the certain portion is lower than the average concentration of the other portion.
• the first conductivity type is n-type and the second conductivity type is p-type; however, the first conductivity type may also be p-type and the second conductivity type may also be n-type.
• Fig. 1 is a plan view showing the configuration of a semiconductor device according to the first embodiment
• Fig. 2 is a cross-sectional view showing the configuration of the semiconductor device taken along lines A-A and B-B in Fig. 1.
• the semiconductor device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but it may also be an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting - IGBT).
• MOSFET Metal Oxide Semiconductor Field Effect Transistor
• IGBT Insulated Gate Bipolar Transistor
• RC-IGBT Reverse Conducting - IGBT
• the semiconductor device includes a semiconductor substrate 1, a gate insulating film 7 which is an insulating film, a gate electrode 8 which is an electrode, an interlayer insulating film 9, a drain electrode 14, and a source electrode 15.
• Semiconductor substrate 1 includes at least one of a normal semiconductor wafer and an epitaxially grown layer.
• at least one of A, B, C, ..., and Z for example, means any one of all combinations of one or more types selected from the group A, B, C, ..., and Z.
• Semiconductor substrate 1 may be made of ordinary silicon (Si), or may be made of a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond.
• SiC silicon carbide
• GaN gallium nitride
• semiconductor substrate 1 is made of a wide bandgap semiconductor, stable operation of the semiconductor device at high temperatures and high voltages is possible, and switching speeds can be increased.
• the semiconductor substrate 1 includes the p-type contact region 5 of FIG. 1, the n-type drift layer 2 of FIG. 2, the p-type well region 3, the n-type source region 4 which is an impurity region, the p-type electric field relaxation region 11, and the p-type high concentration region 12. Note that the contact region 5, the electric field relaxation region 11, and the high concentration region 12 are not essential.
• the well region 3 is provided on the drift layer 2, and the source region 4 is provided on the well region 3.
• the contact region 5 in Figure 1 is provided on the well region 3, just like the source region 4, and provides ohmic contact with the source electrode 15.
• the depth of the gate trench 6 and the depth of the external trench 13 are the same or substantially the same. With this configuration, the depth of the depletion layer in the drift layer 2 can be made uniform, thereby suppressing a decrease in the breakdown voltage of the semiconductor device due to electric field concentration at the periphery of the active region 51.
• the insulating film end 7a which is the end of the gate insulating film 7 facing the source region 4
• the electrode end 8a which is the end of the gate electrode 8 facing the source region 4
• the insulating film end 7a directly faces the source region 4, and the electrode end 8a indirectly faces the source region 4.
• the electric field at the bottom of the gate trench 6 may be relaxed by providing a p-type high concentration region 18 deep in the mesa portion between the gate trenches 6, as shown in Figure 3.
• the impurity concentration of the p-type high concentration region 18 needs to be equal to or higher than the impurity concentration of the p-type well region 3.
• step S1 a semiconductor substrate 1 including a drift layer 2, a well region 3, and a source region 4 is formed, for example, by photolithography and ion implantation.
• step S2 a gate trench 6 and an external trench 13 are formed on the upper surface of the semiconductor substrate 1, for example, by photolithography and etching.
• step S3 a gate insulating film 7 is formed inside the gate trench 6 and the external trench 13, for example, by thermal oxidation.
• step S4 a conductive polysilicon film is formed, and then, for example, photolithography and etching back of the polysilicon film are performed to form a gate electrode 8 whose electrode end 8a is lower than the upper surface 4a of the source region 4.
• step S5 for example, wet etching is performed on part of the gate insulating film 7, making the insulating film end 7a lower than the upper surface 4a of the source region 4.
• step S6 an interlayer insulating film 9 is formed on the gate electrode 8.
• the interlayer insulating film 9 may be formed by, for example, CVD (Chemical Vapor Deposition), photolithography and dry etching, or by other methods.
• a gate insulating film is formed on the upper portion of the trench (e.g., the portion between the upper end of the trench and a position approximately 100 nm in depth from the upper end of the trench).
• unevenness may be formed on the gate insulating film due to the formation of unevenness on the upper portion of the trench, resulting in poor gate insulating film quality.
• an electric field may concentrate around the corner 4c between the upper surface 4a and the side surface 4b of the source region 4, i.e., around the upper portion of the trench, degrading the gate insulating film at the upper portion of the trench and reducing the insulating reliability of the semiconductor device.
• the external trench 13 does not have a periodic structure in plan view like the gate trench 6, and the electric field distribution at the upper portion of the trench is likely to differ from that of the gate trench 6, resulting in electric field concentration at the upper portion of the trench. Therefore, the gate insulating film in the external trench 13 is likely to deteriorate as described above, reducing the insulating reliability of the semiconductor device.
• the electrode end 8a of the gate electrode 8 is lower than the upper surface 4a of the source region 4. This configuration prevents voltage from being applied to the upper part of the trench, thereby improving the insulation reliability of the semiconductor device.
• the insulating film end 7a of the gate insulating film 7 is also lower than the upper surface 4a of the source region 4.
• the corner 4c of the source region 4 does not come into contact with the gate insulating film 7, which is relatively thin and has low insulating reliability, but rather comes into contact with the interlayer insulating film 9, which is relatively thick and has high insulating reliability, thereby improving the insulating reliability of the semiconductor device.
• the interlayer insulating film 9 can be made thicker, thereby improving the insulating reliability of the semiconductor device.
• the interlayer insulating film 9 provided on the gate electrode 8 of the external trench 13 is provided across both the inside and outside of the external trench 13.
• improving the insulation reliability of the semiconductor device is effective when the semiconductor substrate 1 is made of silicon carbide and a high breakdown field strength is required at the corner 4c of the source region 4.
• ⁇ First Modification of First Embodiment> 5 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 1.
• the gate electrodes 8 of the gate trench 6 and the external trench 13 each include a protruding portion 8b.
• the protruding portion 8b is provided in a portion other than the electrode end portion 8a and is higher than the upper surface 4a of the source region 4.
• FIG. 6 is a cross-sectional view showing the manufacturing process of a semiconductor device according to Variation 1, specifically the process of forming the gate electrode 8 (i.e., step S4 in FIG. 4). Below, the manufacturing process of the gate electrode 8 of the external trench 13 is described, but the manufacturing process of the gate electrode 8 of the gate trench 6 is similar to the description below.

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