WO2025013919A1 - 基板の製造方法 - Google Patents

基板の製造方法 Download PDF

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Publication number
WO2025013919A1
WO2025013919A1 PCT/JP2024/025088 JP2024025088W WO2025013919A1 WO 2025013919 A1 WO2025013919 A1 WO 2025013919A1 JP 2024025088 W JP2024025088 W JP 2024025088W WO 2025013919 A1 WO2025013919 A1 WO 2025013919A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
heat dissipation
circuit layer
substrate
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2024/025088
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English (en)
French (fr)
Japanese (ja)
Inventor
隆博 原田
弥 小坂
晋也 山本
洋史 黒田
敦准 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2024564603A priority Critical patent/JPWO2025013919A1/ja
Publication of WO2025013919A1 publication Critical patent/WO2025013919A1/ja
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Definitions

  • the present invention relates to a method for manufacturing a substrate.
  • the method used to form the circuit layer of a circuit board involves forming a circuit layer and then etching it with a solvent to form a circuit pattern.
  • Patent Document 1 describes a method for manufacturing a circuit board, which includes partially dissolving and removing a circuit layer laminated on a support substrate using an etching solution to form a circuit layer.
  • One example of an objective of the present invention is to provide a method for manufacturing a substrate that includes a thick circuit layer.
  • the present invention provides the following substrate manufacturing method.
  • a method for manufacturing a substrate comprising: [2] The encapsulating material has a melt viscosity ⁇ of 10 or more and 40 or less, the melt viscosity being calculated by the following method.
  • the reaction rate of the heat dissipation layer calculated from the measurement results of a DSC is more than 0% and not more than 60%.
  • the sealing material is in a plate-like tablet shape when disposed opposite the circuit layer.
  • the encapsulating material layer is molded to cover at least a portion of the first surface of the circuit layer.
  • the method further includes a step of removing the encapsulant layer molded to cover at least a portion of the first surface of the circuit layer.
  • the sheet includes polyimide. A method for manufacturing a substrate according to [7].
  • the base substrate includes at least one of copper and aluminum. A method for manufacturing a substrate according to any one of [1] to [8]. [10] The base substrate includes a heat dissipation portion provided on a surface opposite to the heat dissipation layer. A method for manufacturing a substrate according to any one of [1] to [9].
  • a method for manufacturing a substrate that includes a thick circuit layer can be provided.
  • FIG. 2 is a diagram showing an example of a cross section of a substrate according to the embodiment.
  • FIG. 4 is a diagram showing a second example of a cross section of the substrate according to the embodiment.
  • 5A to 5C are cross-sectional views showing a process for manufacturing a substrate according to the embodiment.
  • 5A to 5C are cross-sectional views showing a removing step.
  • 10A to 10C are process cross-sectional views showing a modified example of the substrate manufacturing process according to the embodiment.
  • 10A to 10C are process cross-sectional views showing a specific example of a preparation process.
  • 1 is a cross-sectional view showing a process of an example of a tape manufacturing method.
  • FIG. 1 is a diagram showing an example of a cross section of a substrate 100 according to the present embodiment.
  • the substrate 100 includes a base substrate 10, a heat dissipation layer 20, a circuit layer 30, and a sealing material layer 40.
  • the heat dissipation layer 20 is disposed on one surface of the base substrate 10.
  • a circuit layer 30 for mounting a semiconductor element is disposed on one surface of the heat dissipation layer 20 opposite to the base substrate 10.
  • the circuit layer 30 is sealed by the sealing material layer 40.
  • the total thickness T0 of the substrate 100 is not particularly limited, but is preferably 0.7 mm or more and 7 mm or less, and more preferably 0.9 mm or more and 6 mm or less. Each component will be described in detail below.
  • the base substrate 10 holds the heat dissipation layer 20. Moreover, as shown in FIG. 2, it is preferable that a heat dissipation member 11 such as a heat dissipation fin or a radiator is attached to the surface of the base substrate 10 opposite to the heat dissipation layer 20. This improves the heat dissipation performance of the substrate 100.
  • the heat dissipation member 11 may be integrated with the base substrate 10. Moreover, the heat dissipation member 11 may be attached externally to the base substrate 10.
  • the material constituting the base substrate 10 may be, for example, one or a combination of two or more selected from copper, copper alloys, aluminum, and aluminum alloys. Among these, it is preferable to use at least one of copper and aluminum from the viewpoint of strength.
  • the thickness T1 of the base substrate 10 is not particularly limited, but is preferably 30% or more and 70% or less of the total thickness T0.
  • the upper limit of the thickness T1 of the base substrate 10 is, for example, 5 mm or less, preferably 4 mm or less, and more preferably 3 mm or less. If the thickness T1 of the base substrate 10 is set to this value or less, the substrate 100 becomes thinner and the processability of the substrate 100 in the outer shape processing, cutting processing, etc. is improved.
  • the lower limit of the thickness T1 of the base substrate 10 is, for example, 0.3 mm or more, preferably 0.5 mm or more, and more preferably 0.8 mm or more. If the thickness T1 of the base substrate 10 is set to this value or more, the heat dissipation properties of the substrate 100 can be improved.
  • the material constituting the heat dissipation layer 20 according to the present embodiment is, for example, a thermosetting resin.
  • the thermosetting resin may be one or a combination of two or more selected from the group consisting of epoxy resin, phenol resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, and polyurethane resin.
  • a filler composed of particles having electrical insulation and high thermal conductivity into the heat dissipation layer 20.
  • the constituent material of the particles of such a filler can be, for example, at least one of a metal oxide such as alumina and a nitride such as boron nitride.
  • the thickness T2 of the heat dissipation layer 20 is appropriately set according to the purpose, but from the viewpoint of being able to more effectively transfer heat from the semiconductor element to the base substrate 10 while improving mechanical strength and heat resistance, the thickness T2 of the heat dissipation layer 20 is preferably 30 ⁇ m or more and 300 ⁇ m or less, and from the viewpoint of a better balance between heat dissipation and insulation in the entire substrate 100, it is more preferable to set it to 50 ⁇ m or more and 200 ⁇ m or less. By setting the thickness T2 of the heat dissipation layer 20 to the above upper limit value or less, it is possible to easily transfer heat from the semiconductor element to the base substrate 10.
  • the heat dissipation layer 20 can sufficiently alleviate the generation of thermal stress due to the difference in thermal expansion coefficient between the base substrate 10 and the heat dissipation layer 20. Furthermore, the insulation of the substrate 100 is improved.
  • the circuit layer 30 is made of a metal material having electrical conductivity, and for example, a semiconductor element is mounted on the circuit layer 30.
  • the metal material constituting the circuit layer 30 may be, for example, one or a combination of two or more selected from copper, copper alloy, aluminum, and aluminum alloy. This allows the circuit layer 30 to have a relatively small resistance value. It is more preferable that the circuit layer 30 is a copper-containing layer that contains copper. At least a portion of the circuit layer 30 may be covered with a resist material.
  • the lower limit of the thickness T3 of the circuit layer 30 is, for example, 0.3 mm or more, preferably 0.5 mm or more, more preferably 1.0 mm or more, and even more preferably 2.0 mm or more.
  • the upper limit of the thickness T3 of the circuit layer 30 is, for example, 3.0 mm or less, preferably 2.5 mm or less, and even more preferably 2.0 mm or less.
  • the sealing material layer 40 seals the circuit layer 30.
  • the sealing material layer 40 is formed so as not to cover the first surface 31 of the circuit layer 30 opposite the heat dissipation layer 20, but the sealing material layer 40 may be formed so as to cover at least a part of the first surface 31.
  • the sealing material layer 40 is formed, for example, from a cured body of a thermosetting resin.
  • the thermosetting resin may be one or a combination of two or more selected from, for example, epoxy resin, phenolic resin, polyimide resin, bismaleimide resin, urea resin, melamine resin, polyurethane resin, cyanate ester resin, silicone resin, oxetane resin (oxetane compound), (meth)acrylate resin, unsaturated polyester resin, diallyl phthalate resin, benzoxazine resin, etc.
  • the thermosetting resin contains an epoxy resin.
  • both the heat dissipation layer 20 and the sealing resin layer 40 contain an epoxy resin, the adhesion between the heat dissipation layer 20 and the sealing resin layer 40 is improved.
  • thermosetting resin examples include novolac-type phenolic resins such as phenol novolac resin, cresol novolac resin, bisphenol A-type novolac resin, and triazine skeleton-containing phenol novolac resin; phenolic resins such as unmodified resol phenolic resins, oil-modified resol phenolic resins modified with tung oil, linseed oil, walnut oil, etc., resol-type phenolic resins, aralkyl-type phenolic resins such as phenol aralkyl-type phenolic resins, and triphenylmethane-type phenolic resins; Bisphenol type epoxy resins such as bisphenol A type epoxy resins, bisphenol F type epoxy resins, tetramethylbisphenol F type epoxy resins, bisphenol S type epoxy resins, bisphenol E type epoxy resins, bisphenol M type epoxy resins, bisphenol P type epoxy resins, and bisphenol Z type epoxy resins; novolac type epoxy resins such as
  • the sealing material layer 40 may also contain a filler.
  • the material constituting the filler may be, for example, one or a combination of two or more selected from the following: silica, alumina, kaolin, talc, clay, mica, rock wool, wollastonite, glass powder, glass flakes, glass beads, glass fiber, silicon carbide, silicon nitride, aluminum nitride, carbon black, graphite, titanium dioxide, calcium carbonate, calcium sulfate, barium carbonate, magnesium carbonate, magnesium sulfate, barium sulfate, cellulose, aramid, wood, etc.
  • Fig. 3 is a cross-sectional view showing the manufacturing process of the substrate 100.
  • ⁇ S10 Preparation process>
  • the substrate 100 having the above-mentioned base substrate 10, the circuit layer 30, and the heat dissipation layer 20 located between the base substrate 10 and the circuit layer 30 is prepared.
  • the sealing material 50 is disposed so as to face the first surface 31, which is the surface of the circuit layer 30 opposite to the heat dissipation layer 20, and the sealing material 50 is pressed against the heat dissipation layer 20.
  • the sealing material layer 40 that seals the circuit layer 30 is molded by, for example, compression molding in the molding step S20. For example, as shown in FIG. While the substrate 100 is placed in the mold 1, the sealing material 50 is pressed against the heat dissipation layer 20 at a pressure of 10 MPa, and the substrate 100 is heated at a heating temperature of 175° C. for a heating time of 180 seconds.
  • the sealing material 50 is, for example, the above-mentioned thermosetting resin before hardening.
  • the shape of the sealing material 50 may be, for example, granular, powdery, plate-shaped tablet, or sheet-shaped, but a plate-shaped tablet is particularly preferred from the viewpoint of uniform pressure applied to each circuit layer 30.
  • the sealing material 50 may also contain the above-mentioned filler.
  • the sealing material 50 preferably has a melt viscosity ⁇ calculated under the following conditions of 10 or more and 40 or less, and more preferably 20 or more and 40 or less.
  • a melt viscosity ⁇ calculated under the following conditions of 10 or more and 40 or less, and more preferably 20 or more and 40 or less.
  • [formula] ⁇ ( ⁇ D 4 P ⁇ 10 3 /128LQ) (Pa ⁇ sec) where D is the die hole diameter (mm), P is the test pressure (Pa), L is the die length (mm), and Q is the flow rate (cm 3 /sec).
  • D is the die hole diameter (mm)
  • P is the test pressure (Pa)
  • L is the die length (mm)
  • Q is the flow rate (cm 3 /sec).
  • the heat dissipation layer 20 when the sealing material 50 is pressed toward the heat dissipation layer 20 and heated, the heat dissipation layer 20 is preferably in a B-stage state.
  • the B-stage state means, for example, that the reaction rate of the heat dissipation layer 20 calculated from the measurement results of a DSC (differential scanning calorimeter) is more than 0% and not more than 60%.
  • the heat dissipation layer 20 is in a temporary pressure-bonded state with the circuit layer 30 before heating. Then, the heat dissipation layer 20 is heated together with the sealing material 50, and the sealing material layer 40 is formed and hardened to be bonded to the circuit layer 30.
  • the circuit layer 30 is sealed with the sealing material 50 (sealing material layer 40) when the heat dissipation layer 20 hardens, the position of the circuit layer 30 is fixed and does not move even if the heat dissipation layer 20 shrinks.
  • the sealing material layer 40 is molded so as to cover at least a portion of the first surface 31 of the circuit layer 30 opposite the heat dissipation layer 20, but it may be molded so as not to cover the first surface 31. However, from the viewpoint of uniformly distributing pressure to each circuit layer 30, it is preferable that the sealing material layer 40 is molded so as to cover at least a portion of the first surface 31 of the circuit layer 30 opposite the heat dissipation layer 20.
  • the manufacturing method of the substrate 100 according to this embodiment may further include a removal step S30 if the sealing material layer 40 is molded in the molding step S20 so as to cover at least a portion of the first surface 31 of the circuit layer 30 opposite the heat dissipation layer 20.
  • FIG. 4 is a process cross-sectional view showing the removal process S30, which follows the molding process S20. As shown in FIG. 4, the removal process S30 removes the sealing material layer 40 covering the first surface 31, for example, by grinding the sealing material layer 40. This makes it possible to expose the first surface 31 of the circuit layer 30, or to increase the exposed area.
  • the sealing material layer 40 when the sealing material layer 40 is molded to cover at least a portion of the first surface 31 in the molding step S20, the pressure applied to each circuit layer 30 can be made uniform. Therefore, a substrate 100 with a smaller height difference between each circuit layer 30 can be obtained by molding the sealing material layer 40 to cover at least a portion of the first surface 31 in the molding step S20 and then removing the sealing material layer 40 that covers the first surface 31 in the removal step S30, rather than simply molding the sealing material layer 40 so as not to cover the first surface 31 in the molding step S20.
  • the substrate 100 is prepared in which the circuit layers 30 include bridges 32 that secure the circuit layers 30 to each other.
  • the bridges 32 are made of the same material as the circuit layers 30.
  • a sealing material layer 40 that seals the bridges 32 and the circuit layers 30 is molded.
  • the removal step S30 the sealing material layer 40 that covers the bridges 32 and the bridges 32 are removed by grinding or the like to separate the circuit layers 30.
  • the circuit layers 30 are fixed to each other by the bridges 32, which further prevents the circuit layers 30 from shifting when the sealing material layer 40 is molded.
  • the circuit layer 30 having the bridges 32 can be obtained, for example, by bending the portions of the metal plate that is the material of the circuit layer 30 that will become the bridges 32. At this time, the degree of curvature is set to be approximately the same as the thickness of the metal plate. After that, the circuit layer 30 having the bridges 32 can be obtained by pressing and punching.
  • FIG. 6 is a process cross-sectional view showing a specific example of the preparation step S10.
  • a sheet 2 that holds the circuit layer 30 on one side is prepared (S11).
  • the sheet 2 includes, for example, an adhesive layer that adheres and holds the circuit layer 30, and a base layer for holding the adhesive layer.
  • the heat dissipation layer 20 is arranged on one side of the base substrate 10 (S12). Specifically, for example, the material that constitutes the heat dissipation layer 20 described above in a B-stage state is applied.
  • the material that constitutes the heat dissipation layer 20 in a sheet-like B-stage state is arranged. Then, the circuit layer 30 held by the sheet 2 described above is pressed and fixed against the heat dissipation layer 20, and the sheet 2 is then released (S13).
  • FIG. 7 is a cross-sectional view showing an example of a process for manufacturing the tape 2.
  • one side of the metal plate 4 (the bottom side in the figure) is covered with masking tape 3 (S1).
  • masking tape 3 There are no particular limitations on the masking tape 3 as long as it is resistant to the etching in the next step (S2).
  • the other side of the metal plate 4 that is not covered with the masking tape 3 (the top side in the figure) is etched to obtain a grooved metal plate 4 in which grooves 5 of the desired pattern are formed to a specified depth.
  • the grooved metal plate 4 covered with tape 2 is turned over so that the tape 2 is on the bottom to adjust its position (S4), and the top surface of the grooved metal plate 4 (i.e. the surface opposite the tape 2) is etched to remove and open the top surfaces of the grooves 5, forming the circuit layer 30 (S5). This results in a tape 2 that holds the circuit layer 30 on one side.
  • any type of resin tape can be used as the tape 2 as long as it can adequately cover the surface of the metal plate 4 and can be adequately peeled off during the manufacturing process of the substrate 100.
  • the resin tape polyimide resin tape is preferable, and more specifically, a film member having a two-layer structure in which an adhesive layer is provided on one side of the polyimide layer serving as the base material is preferable.
  • the thickness of the polyimide layer serving as the base material can be, for example, about 25 ⁇ m.
  • the adhesive layer for example, acrylic resin, epoxy resin, or silicone resin can be used.
  • the method for manufacturing the substrate 100 according to this embodiment has the following advantages.
  • the method for manufacturing the substrate 100 according to this embodiment forms the circuit layer 30 by attaching the already formed circuit layer 30 to the heat dissipation layer 20. Then, as described with reference to FIG. 7, it is possible to attach the circuit layer 30 formed by performing etching from both sides. Therefore, compared to the conventional method for manufacturing a substrate in which a metal plate is attached and then etched to form the circuit layer 30, it is possible to form a circuit layer 30 with a large thickness. Furthermore, the method for manufacturing the substrate 100 according to this embodiment can simultaneously form the circuit layer 30 and harden the heat dissipation layer 20, thereby simplifying the manufacturing process. Also, as shown in FIG. 3, when pressing the substrate 100 vertically (from above in the example of FIG. 3) in the molding process S20, it is possible to suppress the misalignment of each circuit layer 30.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
PCT/JP2024/025088 2023-07-12 2024-07-11 基板の製造方法 Pending WO2025013919A1 (ja)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002335056A (ja) * 2001-05-08 2002-11-22 Nitto Shinko Kk 金属ベース基板及びその製造方法
JP2013251368A (ja) * 2012-05-31 2013-12-12 Hitachi Chemical Co Ltd 半導体装置の製造方法及びそれに用いる熱硬化性樹脂組成物並びにそれにより得られる半導体装置
US20140069693A1 (en) * 2012-09-07 2014-03-13 E I Du Pont De Nemours And Company Multi-layer article comprising discrete conductive pathways contacting a curable composition comprising bis-benzoxazine
WO2018189797A1 (ja) * 2017-04-10 2018-10-18 日立化成株式会社 回路基板の製造方法、回路シート及び回路基板
WO2020111045A1 (ja) * 2018-11-26 2020-06-04 日本発條株式会社 金属ベース回路基板の製造方法
WO2023090013A1 (ja) * 2021-11-19 2023-05-25 住友ベークライト株式会社 ヒートシンク付回路基板およびその製造方法、ならびに半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002335056A (ja) * 2001-05-08 2002-11-22 Nitto Shinko Kk 金属ベース基板及びその製造方法
JP2013251368A (ja) * 2012-05-31 2013-12-12 Hitachi Chemical Co Ltd 半導体装置の製造方法及びそれに用いる熱硬化性樹脂組成物並びにそれにより得られる半導体装置
US20140069693A1 (en) * 2012-09-07 2014-03-13 E I Du Pont De Nemours And Company Multi-layer article comprising discrete conductive pathways contacting a curable composition comprising bis-benzoxazine
WO2018189797A1 (ja) * 2017-04-10 2018-10-18 日立化成株式会社 回路基板の製造方法、回路シート及び回路基板
WO2020111045A1 (ja) * 2018-11-26 2020-06-04 日本発條株式会社 金属ベース回路基板の製造方法
WO2023090013A1 (ja) * 2021-11-19 2023-05-25 住友ベークライト株式会社 ヒートシンク付回路基板およびその製造方法、ならびに半導体装置およびその製造方法

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