Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

• This disclosure relates to a display device.
• Display devices use a large number of transistors in their drivers.
• a display device includes a plurality of display pixels, a plurality of scanning lines, a first buffer circuit connected to one end of each scanning line, and a second buffer circuit connected to the other end of each scanning line.
• the display device further includes a first driver, a second driver, and a display control circuit.
• the first driver is electrically connected to one end of each of the scanning lines via the first buffer circuit, and is capable of sequentially selecting a plurality of display pixels for each unit pixel row via the plurality of scanning lines.
• the second driver is electrically connected to the other end of each of the scanning lines via the second buffer circuit, and is capable of sequentially selecting a plurality of display pixels for each unit pixel row via the plurality of scanning lines.
• the display control circuit is capable of controlling the first buffer circuit, the second buffer circuit, the first driver, and the second driver.
• FIG. 1 is a diagram illustrating an example of a schematic configuration of a display device according to an embodiment of the present disclosure.
• FIG. 2 is a diagram showing an example of a circuit configuration of one pixel connected to an arbitrary scanning line in the display device of FIG. 1, as well as two gate drivers and two buffer circuits.
• Fig. 3(A) shows an example of a change over time of a pulse signal CLKV generated by a gate driver.
• Fig. 3(B) shows an example of a change over time of a state control signal RSTL input to a buffer circuit.
• Fig. 3(C) shows an example of a change over time of a state of a buffer circuit to which a state control signal RSTL is input.
• Fig. 3(A) shows an example of a change over time of a pulse signal CLKV generated by a gate driver.
• Fig. 3(B) shows an example of a change over time of a state control signal RSTL input to a buffer circuit.
• FIG. 3(D) shows an example of a change over time of a state control signal RSTR input to a buffer circuit.
• FIG. 3(E) shows an example of a change over time of a state of a buffer circuit to which a state control signal RSTR is input.
• Fig. 4(A) shows an example of a change over time of a pulse signal CLKV generated by a gate driver.
• Fig. 4(B) shows an example of a change over time of a state control signal RSTL input to a buffer circuit.
• Fig. 4(C) shows an example of a change over time of a state of a buffer circuit to which a state control signal RSTL is input.
• Fig. 4(A) shows an example of a change over time of a pulse signal CLKV generated by a gate driver.
• Fig. 4(B) shows an example of a change over time of a state control signal RSTL input to a buffer circuit.
• Fig. 4(C) shows an example
• FIG. 4(D) shows an example of a change over time of a state control signal RSTR input to a buffer circuit.
• Fig. 3(E) shows an example of a change over time of a state of a buffer circuit to which a state control signal RSTR is input.
• FIG. 5 is a diagram showing an example of a truth table of a logic circuit formed by a pair of gate drivers and buffer circuits shown in FIG.
• FIG. 6 is a diagram showing an example of the operation of the logic circuit when the inputs are "L, L" in the truth table of FIG.
• FIG. 7 is a diagram showing an example of the operation of the logic circuit when the inputs are "L, H" in the truth table of FIG.
• FIG. 8 is a diagram showing an example of the operation of the logic circuit when the inputs are "H, L" in the truth table of FIG.
• FIG. 9 is a diagram showing an example of the operation of the logic circuit when the inputs are "H, H” in the truth table of FIG.
• Fig. 10(A) shows an example of a change over time of a pulse signal CLKV generated by a gate driver.
• Fig. 10(B) shows a modified example of a change over time of a state control signal RSTL input to a buffer circuit.
• Fig. 10(C) shows a modified example of a change over time of a state of a buffer circuit to which a state control signal RSTL is input.
• Fig. 10(A) shows an example of a change over time of a pulse signal CLKV generated by a gate driver.
• Fig. 10(B) shows a modified example of a change over time of a state control signal RSTL input to a buffer circuit.
• FIG. 10(D) shows a modified example of a change over time of a state control signal RSTR input to a buffer circuit.
• Fig. 10(E) shows a modified example of a change over time of a state of a buffer circuit to which a state control signal RSTR is input.
• FIG. 11 is a diagram showing a modified example of the circuit configuration of one pixel connected to an arbitrary scanning line in the display device of FIG. 1, as well as two gate drivers and two buffer circuits.
• FIG. 12 is a diagram showing an example of a truth table of a logic circuit formed by a pair of the gate driver and buffer circuit shown in FIG.
• FIG. 1 illustrates an example of a schematic configuration of the display device 1.
• the display device 1 includes, for example, a display panel 10 and a logic IC (Integrated Circuit) 20, as shown in Fig. 1.
• IC Integrated Circuit
• the display panel 10 has a pixel array region 10A in which a plurality of display pixels 11 are arranged two-dimensionally in the row and column directions, for example.
• the pixel array region 10A corresponds to the image display region of the display panel 10.
• the display panel 10 further has a peripheral region 10B in which a plurality of buffer circuits 12 and a plurality of buffer circuits 13 are arranged, for example.
• the peripheral region 10B is a region that surrounds the pixel array region 10A in a plan view, and corresponds to the frame region of the display panel 10.
• the display panel 10 is capable of displaying an image based on a video signal input from outside the display device 1, for example, by the plurality of display pixels 11 being actively driven by a logic IC 20.
• the display panel 10 has, for example, a number of scanning lines WSL extending in the row direction and a number of signal lines DTL extending in the column direction.
• display pixels 11 are provided at the intersections of the signal lines DTL and the scanning lines WSL.
• Each scanning line WSL is connected to the output terminals of gate drivers 21 and 22, which will be described later.
• Each signal line DTL is connected to the output terminal of a data driver 23, which will be described later.
• each display pixel 11 has a transistor Tr that writes a signal voltage to the display pixel 11, a storage capacitance Cs that holds the voltage written to the display pixel 11, and an optical element OE connected in parallel to the storage capacitance Cs. The voltage held in the storage capacitance Cs is applied to the optical element OE.
• the optical element OE is an element that can perform optical modulation or emit light according to the magnitude of the voltage held in the storage capacitance Cs or the magnitude of the current flowing through the optical element OE due to the voltage held in the storage capacitance Cs, and is composed of, for example, a liquid crystal layer, an organic EL (Electro Luminescence) layer, or an electrophoretic layer.
• One end of the storage capacitance Cs and the optical element OE is connected to the scanning line WSL, and the other end of the storage capacitance Cs and the optical element OE is connected to, for example, a common potential line COM.
• the buffer circuit 12 is connected to one end of the scanning line WSL and is disposed between the output terminal of the gate driver 21 and the scanning line WSL.
• the buffer circuit 13 is connected to the other end of the scanning line WSL and is disposed between the output terminal of the gate driver 22 and the scanning line WSL.
• the buffer circuits 12 and 13 have, for example, a p-type MOS transistor P1 and an n-type MOS transistor N1 connected in series between the power supply potential line VDD and the power supply potential line VSS, and a p-type MOS transistor P2 and an n-type MOS transistor N2 connected in series, as shown in FIG. 2.
• the buffer circuits 12 and 13 further have, for example, a p-type MOS transistor P0, as shown in FIG. 2.
• the voltage Vdd of the power supply potential line VDD is a voltage value higher than the voltage Vss of the power supply potential line VSS.
• the transistor P0 included in the buffer circuit 12 in FIG. 2 corresponds to a specific example of a "first switch element" according to an embodiment of the present disclosure.
• the transistor P0 included in the buffer circuit 13 in FIG. 2 corresponds to a specific example of a "second switch element" according to an embodiment of the present disclosure.
• the source of p-type MOS transistor P1 and the drain of n-type MOS transistor N1 are connected to each other, and their connection point a is connected to the scanning line WSL.
• the gate of p-type MOS transistor P1 and the gate of n-type MOS transistor N1 are connected to each other, and their connection point b is connected to the connection point between the source of p-type MOS transistor P2 and the drain of n-type MOS transistor N2.
• the gate of p-type MOS transistor P2 and the gate of n-type MOS transistor N2 are connected to each other.
• the p-type MOS transistor P0 is connected to the power supply potential line VDD and the drain of p-type MOS transistor P1.
• the gate of the p-type MOS transistor P0 in the buffer circuit 12 is input with a state control signal RSTL, which will be described later.
• the gate of the p-type MOS transistor P0 in the buffer circuit 13 is input with a state control signal RSTR, which will be described later.
• a connection point c between the gate of the p-type MOS transistor P2 and the gate of the n-type MOS transistor N2 in the buffer circuit 12 is connected to the output terminal of the output circuit 211 of the gate driver 21.
• a connection point d between the gate of the p-type MOS transistor P2 and the gate of the n-type MOS transistor N2 in the buffer circuit 13 is connected to the output terminal of the output circuit 221 of the gate driver 22.
• the buffer circuit 12 is capable of outputting the output (selection pulse) from the gate driver 21 to the scanning line WSL.
• the buffer circuit 13 is capable of outputting the output (selection pulse) from the gate driver 22 to the scanning line WSL.
• the p-type MOS transistor P0 functions as a switch capable of switching between a "normal period ⁇ Ta" and a "recovery period ⁇ Tb" based on a state control signal RSTL described later.
• the p-type MOS transistor P0 is a switch element capable of electrically connecting and disconnecting the output terminal of the buffer circuit 12 and the power supply potential line VDD.
• the p-type MOS transistor P0 functions as a switch capable of switching between a "normal period ⁇ Tc" and a "recovery period ⁇ Td" based on a state control signal RSTR described later.
• the p-type MOS transistor P0 is a switch element capable of electrically connecting and disconnecting the output terminal of the buffer circuit 13 and the power supply potential line VDD.
• FIG. 3 illustrates an example of switching between the "normal period ⁇ Ta" and the “recovery period ⁇ Tb" in the buffer circuit 12, and switching between the "normal period ⁇ Tc" and the “recovery period ⁇ Td” in the buffer circuit 13.
• FIG. 3(A) illustrates an example of the time change of the synchronization signal VST and the pulse signal CLKV in one frame period.
• the synchronization signal VST has a frequency that is the reciprocal of one frame period (1F), for example, 120 Hz.
• the pulse signal CLKV is a control signal generated by the gate drivers 21 and 22.
• the pulse signal CLKV has a frequency that is the reciprocal of one frame period (1F) divided by the number of unit pixel rows included in the display panel 10.
• a unit pixel row refers to one or more pixel rows selected at one time by the gate drivers 21 and 22.
• Figure 3 (B) shows an example of the change over time of the state control signal RSTL.
• the state control signal RSTL is a control signal input to the buffer circuit 12 from the display control circuit 24 described below.
• Figure 3 (C) shows an example of the change over time of the state of the buffer circuit 12 ("normal period ⁇ Ta”, “recovery period ⁇ Tb”).
• Figure 3 (D) shows an example of the change over time of the state control signal RSTR.
• the state control signal RSTR is a control signal input to the buffer circuit 13 from the display control circuit 24 described below.
• Figure 3 (E) shows an example of the change over time of the state of the buffer circuit 13 ("normal period ⁇ Tc", "recovery period ⁇ Td").
• FIGS 3(A) to 3(E) illustrate an example in which the "normal period ⁇ Ta” and the “recovery period ⁇ Tb” alternate every frame period (1F), and the "normal period ⁇ Tc” and the “recovery period ⁇ Td” alternate every frame period (1F).
• the switching period of the "normal period ⁇ Ta” and the “recovery period ⁇ Tb” is not limited to one frame period (1F)
• the switching period of the "normal period ⁇ Tc" and the "recovery period ⁇ Td” is not limited to one frame period (1F).
• the "normal period ⁇ Ta" and the “recovery period ⁇ Tb” may alternate every several frame periods, for example, and the "normal period ⁇ Tc" and the “recovery period ⁇ Td” may alternate every several frame periods, for example.
• the "normal period ⁇ Ta” and the “recovery period ⁇ Tb” may alternate, for example, every two frame periods
• the "normal period ⁇ Tc" and the “recovery period ⁇ Td” may alternate, for example, every two frame periods.
• FIG. 4 corresponds to a specific example of a "first period” according to an embodiment of the present disclosure.
• the period in which the recovery period ⁇ Tb and the normal period ⁇ Tc overlap in FIG. 3 and FIG. 4 corresponds to a specific example of a "second period" according to an embodiment of the present disclosure.
• the buffer circuits 12 and 13 can output the output (selection pulse) from the gate drivers 21 and 22 to the scanning line WSL.
• the period during which the buffer circuit 12 is in this state is called the "normal period ⁇ Ta”.
• the period during which the buffer circuit 13 is in this state is called the "normal period ⁇ Tc”.
• a potential of -(Vdd-Vss) is applied to the gate of the p-type MOS transistor P2, and for example, a potential of (Vdd-Vss) is applied to the gate of the n-type MOS transistor N1. Therefore, the degradation of characteristics due to BTI can become significant in proportion to the ON period.
• the period during which p-type MOS transistor P2 and n-type MOS transistor N1 are ON will be referred to simply as the "ON period.”
• the period during which p-type MOS transistor P2 and n-type MOS transistor N1 are OFF (OFF period) will be referred to simply as the "OFF period.”
• buffer circuits 12, 13 do not output the output (selection pulse) from gate drivers 21, 22 to scanning line WSL, and the output impedance of the output terminal of buffer circuits 12, 13 can be set to high impedance (Hi-z).
• Hi-z high impedance
• p-type MOS transistor P2 and n-type MOS transistor N1 are OFF in buffer circuits 12, 13. Therefore, the characteristics of p-type MOS transistor P2 and n-type MOS transistor N1 that fluctuated during the ON period gradually recover to their original characteristics over time during the OFF period.
• the period during which buffer circuit 12 is in this state is called the “recovery period ⁇ Tb”.
• the period during which buffer circuit 13 is in this state is called the "recovery period ⁇ Td".
• the logic IC 20 is configured to include, for example, one or more ICs.
• the logic IC 20 is provided, for example, in the peripheral region 10B of the display panel 10.
• the logic IC 20 may be electrically connected to the display panel 10, for example, via an FPC (Flexible Printed Circuits).
• the logic IC 20 has, for example, gate drivers 21 and 22, a data driver 23, and a display control circuit 24.
• the logic IC 20 is capable of displaying an image based on a video signal input from outside the display device 1 on the display panel 10, for example, by actively driving a plurality of display pixels 11 of the display panel 10.
• the display control circuit 24 can, for example, store and hold the input video signal in a frame memory for each screen (for each display of one frame).
• the display control circuit 24 can also, for example, control the gate drivers 21, 22 and data driver 23 that drive the display panel 10 so that they operate in conjunction with each other.
• the data driver 23 can, for example, supply a scanning timing control signal (e.g., a synchronization signal VST and a clock signal) to the gate drivers 21, 22, and supply the data driver 23 with a video signal for a unit pixel row based on the video signal held in the frame memory, and a display timing control signal.
• a scanning timing control signal e.g., a synchronization signal VST and a clock signal
• the data driver 23 is capable of supplying, for example, a video signal for a unit pixel row supplied from the display control circuit 24 to each display pixel 11 as a signal voltage. Specifically, the data driver 23 is capable of supplying, for example, a signal voltage corresponding to the video signal for a unit pixel row to each display pixel 11 in the unit pixel row selected by the data driver 23 via a signal line DTL.
• Gate drivers 21 and 22 are connected to a common set of scanning lines WSL via buffer circuits 12 and 13. Gate driver 21 is connected to one end of the scanning lines WSL via buffer circuit 12, and gate driver 22 is connected to the other end of the scanning lines WSL via buffer circuit 13.
• the gate drivers 21 and 22 can select the display pixel 11 to be driven based on, for example, a scanning timing control signal (for example, a synchronization signal VST and a clock signal) supplied from the display control circuit 24. Specifically, the gate drivers 21 and 22 can select each display pixel 11 of a unit pixel row among the multiple display pixels 11 arranged two-dimensionally in the pixel array region 10A as a drive target by applying a selection pulse to the gate of the transistor of the display pixel 11 via the scanning line WSL, for example. Then, in these display pixels 11, the unit pixel row is displayed according to the signal voltage supplied from the data driver 23. In this way, the gate drivers 21 and 22 can sequentially scan the unit pixel row by unit pixel row in a time-division manner, for example, to cause the display panel 10 to perform display over the entire display area.
• a scanning timing control signal for example, a synchronization signal VST and a clock signal
• the gate drivers 21 and 22 each have, for example, a shift register circuit.
• the shift register circuit is capable of generating a pulse signal CLKV that sequentially shifts the selected unit pixel row in the scanning direction based on a scanning timing control signal (for example, a synchronization signal VST and a clock signal) supplied from the display control circuit 24.
• a scanning timing control signal for example, a synchronization signal VST and a clock signal
• the gate driver 21 has an output circuit 211 for each unit pixel row, for example, as shown in FIG. 2, in the rear stage of the shift register circuit.
• the output circuit 211 includes a NOR circuit and a NOT circuit, for example, as shown in FIG. 2.
• the output circuit 211 includes a NOR circuit to which the state control signal RSTL and the pulse signal CLKV are input, and a NOT circuit to which the output of the NOR circuit is input, for example, as shown in FIG. 2.
• the gate driver 22 has an output circuit 221 for each unit pixel row, for example, as shown in FIG. 2, in the rear stage of the shift register circuit.
• the output circuit 221 includes a NOR circuit and a NOT circuit, for example, as shown in FIG. 2.
• the output circuit 221 includes a NOR circuit to which the state control signal RSTR and the pulse signal CLKV are input, and a NOT circuit to which the output of the NOR circuit is input, for example, as shown in FIG. 2.
• FIG. 5 shows an example of a truth table of a logic circuit formed by output circuit 211 and buffer circuit 12, or output circuit 221 and buffer circuit 13.
• FIG. 6 shows an example of the operation of the logic circuit when the inputs are "L, L” in the truth table of FIG. 5.
• FIG. 7 shows an example of the operation of the logic circuit when the inputs are "L, H” in the truth table of FIG. 5.
• FIG. 8 shows an example of the operation of the logic circuit when the inputs are "H, L” in the truth table of FIG. 5.
• FIG. 9 shows an example of the operation of the logic circuit when the inputs are "H, H” in the truth table of FIG. 5.
• the output circuit 221 and the buffer circuit 13 can also operate in the same manner as shown in Figures 6 and 7.
• the output impedance of the output terminal of the buffer circuit 12 becomes "high impedance Hi-z", and the scanning line WSL is electrically isolated from the power supply potential line VDD of the buffer circuit 12.
• the signal level of the scanning line WSL at this time becomes a signal level according to the output voltage of the buffer circuit 13.
• the output impedance of the output terminal of the buffer circuit 12 becomes "high impedance Hi-z", and the scanning line WSL is electrically isolated from the power supply potential line VDD of the buffer circuit 12.
• the signal level of the scanning line WSL at this time becomes a signal level according to the output voltage of the buffer circuit 13.
• the output circuit 221 and buffer circuit 13 can also be in the same state as shown in Figures 8 and 9.
• the characteristics of the p-type MOS transistor P2 and the n-type MOS transistor N1 that fluctuate during the ON period (normal period ⁇ Tc) gradually recover to their original characteristics over time.
• the operation of the output circuit 221 and buffer circuit 13 at this time corresponds to, for example, the operation during the "recovery period ⁇ Td" in Figure 4 (E).
• the display control circuit 24 can input a state control signal RSTL to the buffer circuit 12, thereby setting whether or not the buffer circuit 12 is to output a selection pulse to the scanning line WSL.
• the display control circuit 24 inputs an "L-level signal" to the buffer circuit 12 as the state control signal RSTL.
• the buffer circuit 12 is able to output a selection pulse to the scanning line WSL while the "L-level signal” is being input as the state control signal RSTL from the display control circuit 24 (normal period ⁇ Ta).
• the display control circuit 24 inputs an "H level signal” as the state control signal RSTL to the buffer circuit 12.
• the buffer circuit 12 cannot output a selection pulse to the scanning line WSL while the "H level signal” is being input as the state control signal RSTL from the display control circuit 24 (recovery period ⁇ Tb).
• the p-type MOS transistor P2 and the n-type MOS transistor N1 are turned OFF, and the characteristics of the p-type MOS transistor P2 and the n-type MOS transistor N1 that fluctuated during the ON period (normal period ⁇ Ta) gradually recover to their original characteristics over time.
• the display control circuit 24 can also set whether or not the buffer circuit 13 outputs a selection pulse to the scanning line WSL, for example, by inputting a state control signal RSTR to the buffer circuit 13. For example, the display control circuit 24 inputs an "L-level signal" as the state control signal RSTL to the gate driver 22. At this time, the buffer circuit 13 can output a selection pulse to the scanning line WSL while the "L-level signal” is being input as the state control signal RSTR from the display control circuit 24 (normal period ⁇ Tc).
• the display control circuit 24 inputs an "H level signal” as the state control signal RSTR to the buffer circuit 13.
• the buffer circuit 13 cannot output a selection pulse to the scanning line WSL while the "H level signal” is being input as the state control signal RSTR from the display control circuit 24 (recovery period ⁇ Td).
• the p-type MOS transistor P2 and the n-type MOS transistor N1 are turned OFF, and the characteristics of the p-type MOS transistor P2 and the n-type MOS transistor N1 that fluctuated during the ON period (normal period ⁇ Tc) gradually recover to their original characteristics over time.
• the display control circuit 24 inputs an "H level signal” as the state control signal RSTL and an "L level signal” as the state control signal RSTR. At this time, the display control circuit 24 electrically connects the output terminal of the gate driver 22 to the scanning line WSL via the buffer circuit 13 and electrically isolates the output terminal of the buffer circuit 12 from the scanning line WSL (time t1, see Figures 3 and 4). After that, the display control circuit 24 switches the state control signal RSTL from an "H level signal” to an "L level signal” and switches the state control signal RSTR from an "L level signal” to an "H level signal”. At this time, the display control circuit 24 electrically isolates the output terminal of the buffer circuit 13 from the scanning line WSL and connects the output terminal of the buffer circuit 12 to the scanning line WSL (time t2, see Figures 3 and 4).
• the display control circuit 24 inputs an "L level signal” as the state control signal RSTL and an "H level signal” as the state control signal RSTR.
• the display control circuit 24 electrically isolates the output terminal of the buffer circuit 13 from the scanning line WSL and electrically connects the output of the gate driver 21 to the scanning line WSL via the buffer circuit 12 (time t3, see Figures 3 and 4).
• the display control circuit 24 switches the state control signal RSTL from an "L level signal” to an "H level signal” and switches the state control signal RSTR from an "H level signal” to an “L level signal”.
• the display control circuit 24 connects the output terminal of the buffer circuit 13 to the scanning line WSL and electrically isolates the output terminal of the buffer circuit 12 from the scanning line WSL (time t4, see Figures 3 and 4).
• the display control circuit 24 inputs an "H level signal” as the state control signal RSTL and an "L level signal” as the state control signal RSTR. At this time, the display control circuit 24 electrically connects the output terminal of the gate driver 22 to the scanning line WSL via the buffer circuit 13 and electrically isolates the output terminal of the buffer circuit 12 from the scanning line WSL (time t5, see Figures 3 and 4).
• the display control circuit 24 may set the period for switching the state control signal RSTL between "H level signal” and “L level signal” and the period for switching the state control signal RSTR between "H level signal” and “L level signal” to one frame period (1F).
• the display control circuit 24 may set these periods to N frame periods (N ⁇ 2). In this case, the display control circuit 24 may set the period for connecting and disconnecting the output terminal of the buffer circuit 12 to and from the scanning line WSL and the period for connecting and disconnecting the output terminal of the buffer circuit 13 to and from the scanning line WSL to one frame period (1F).
• the display control circuit 24 may set these periods to N frame periods.
• the display control circuit 24 may, for example, as shown in Figures 3 and 4, match the timing at which the state control signal RSTL switches from an "H level signal” to an "L level signal” with the timing at which the state control signal RSTR switches from an "L level signal” to an "H level signal.”
• the display control circuit 24 may, for example, as shown in Figure 10, shift the timing at which the state control signal RSTL switches from an "H level signal” to an "L level signal” with the timing at which the state control signal RSTR switches from an "L level signal” to an “H level signal.”
• it is preferable that the period ⁇ t during which the normal period ⁇ Ta in the buffer circuit 12 and the normal period ⁇ Tc in the buffer circuit 13 overlap each other is within a period during which no video is displayed (a blanking period), for example.
• the display control circuit 24 is capable of controlling the buffer circuits 12, 13 and the drivers 21, 22 so that the period (first period) in which the normal period ⁇ Ta and the recovery period ⁇ Td overlap with each other and the period (second period) in which the recovery period ⁇ Tb and the normal period ⁇ Tc overlap with each other alternate every one frame period or every few frame periods.
• a specific example of the "first period” according to an embodiment of the present disclosure corresponds to the period in FIG. 10 in which the normal period ⁇ Ta and the recovery period ⁇ Td overlap with each other.
• a specific example of the "second period” according to an embodiment of the present disclosure corresponds to the period in FIG. 10 in which the recovery period ⁇ Tb and the normal period ⁇ Tc overlap with each other.
• the output terminal of the driver 21 is electrically connected to the scanning line WSL via the buffer circuit 12, and the output terminal of the buffer circuit 13 is electrically isolated from the scanning line WSL. Furthermore, during the period (second period) in which the recovery period ⁇ Tb and the normal period ⁇ Tc overlap each other, the output terminal of the buffer circuit 12 is electrically isolated from the scanning line WSL, and the output terminal of the driver 22 is electrically connected to the scanning line WSL via the buffer circuit 13.
• the p-type MOS transistor P0 of the buffer circuit 12 is turned off, and the output terminal of the buffer circuit 12 is electrically isolated from the power supply line VDD. Furthermore, during the period (first period) in which the normal period ⁇ Ta and the recovery period ⁇ Td overlap, the p-type MOS transistor P0 of the buffer circuit 13 is turned off, and the output terminal of the buffer circuit 13 is electrically isolated from the power supply line VDD.
• the buffer circuits 12, 13 and the drivers 21, 22 are controlled so that the first period and the second period alternate every one frame period or every few frame periods. This allows an OFF period of the p-type MOS transistor P0 included in the buffer circuit 13 to be provided during the first period, and an OFF period of the p-type MOS transistor P0 included in the buffer circuit 12 to be provided during the second period. As a result, the characteristics of the p-type MOS transistor P0 included in the buffer circuit 13 can be restored during the first period, and the characteristics of the p-type MOS transistor P0 included in the buffer circuit 12 can be restored during the second period. Therefore, characteristic fluctuations due to the p-type MOS transistor P0 included in the buffer circuit 12 and the p-type MOS transistor P0 included in the buffer circuit 13 can be suppressed.
• the drivers 21 and 22 are configured to include a NOR circuit and a NOT circuit.
• the state control signal RSTL and the pulse signal CLKV are input to the NOR circuit, and the output of the NOR circuit is input to the NOT circuit.
• the state control signal RSTL is input to the p-type MOS transistor P0.
• the state control signal RSTR and the pulse signal CLKV are input to the NOR circuit, and the output of the NOR circuit is input to the NOT circuit.
• the state control signal RSTR is input to the p-type MOS transistor P0.
• the output circuit 211 may be configured to include, for example, a NOT circuit to which the negative logic of the state control signal RSTL is input, and a NAND circuit to which the negative logic of the state control signal RSTL and the negative logic of the pulse signal CLKV are input, as shown in FIG. 11.
• the output circuit 221 may be configured to include, for example, a NOT circuit to which the negative logic of the state control signal RSTR is input, and a NAND circuit to which the negative logic of the state control signal RSTL and the negative logic of the pulse signal CLKV are input, as shown in FIG. 11. At this time, the output of the NOT circuit is applied to the gate of the p-type MOS transistor P0.
• the drivers 21 and 22 are configured to include a NOT circuit and a NAND circuit.
• the negative logic of the state control signal RSTL is input to the NOT circuit
• the negative logic of the state control signal RSTL and the negative logic of the pulse signal CLKV are input to the NAND circuit
• the output of the NOT circuit is input to the p-type MOS transistor P0.
• the negative logic of the state control signal RSTR is input to the NOT circuit
• the negative logic of the state control signal RSTL and the negative logic of the pulse signal CLKV are input to the NAND circuit
• the buffer circuit 13 the output of the NOT circuit is input to the p-type MOS transistor P0.
• the present disclosure can have the following configuration.
• the display control circuit includes: during a first period, an output terminal of the first driver is electrically connected to the scanning line via the first buffer circuit, and an output terminal of the second buffer circuit is electrically isolated from the scanning line; In the second period, an output terminal of the first buffer circuit is electrically isolated from
• the first buffer circuit has a first switch element capable of electrically connecting and disconnecting an output terminal of the first buffer circuit and a first power supply potential line
• the second buffer circuit has a second switch element capable of electrically connecting and disconnecting an output terminal of the second buffer circuit and a second power supply potential line
• the display control circuit includes: during the second period, the first switch element is turned off, thereby making it possible to electrically isolate the output terminal of the first buffer circuit from the first power supply potential line;
• the display device according to (1) wherein, during the first period, the second switch element is turned off, thereby making it possible to electrically isolate the output terminal of the second buffer circuit from the second power supply potential line.
• the display control circuit is capable of controlling the first buffer circuit, the second buffer circuit, the first driver, and the second driver so that the first period and the second period alternate every one frame period or every few frame periods.
• the first driver includes a first NOR circuit and a first NOT circuit to which an output of the first NOR circuit is input;
• the second driver includes a second NOR circuit and a second NOT circuit to which an output of the second NOR circuit is input;
• the first driver includes a first NOT circuit and a first NAND circuit
• the second driver includes a second NOT circuit and a second NAND circuit
• the display control circuit is capable of inputting a negative logic of a first state control signal to the first NOT circuit, inputting the negative logic of the first state control signal and the negative logic of a pulse signal to the first NAND circuit, inputting a negative logic of a second state control signal to the second NOT circuit, and inputting the negative logic of the second state control signal and the negative logic of the pulse signal to the second NAND circuit.

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Citations (9)

• 2024
  • 2024-06-04 JP JP2025532426A patent/JPWO2025013463A1/ja active Pending
  • 2024-06-04 WO PCT/JP2024/020366 patent/WO2025013463A1/ja active Pending

Patent Citations (9)

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