WO2024252872A1 - 半導体装置、マッチング回路及びフィルタ回路 - Google Patents

半導体装置、マッチング回路及びフィルタ回路 Download PDF

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WO2024252872A1
WO2024252872A1 PCT/JP2024/017953 JP2024017953W WO2024252872A1 WO 2024252872 A1 WO2024252872 A1 WO 2024252872A1 JP 2024017953 W JP2024017953 W JP 2024017953W WO 2024252872 A1 WO2024252872 A1 WO 2024252872A1
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layer
electrode
electrode layer
substrate
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French (fr)
Japanese (ja)
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是清 伊藤
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to CN202480033092.5A priority patent/CN121153352A/zh
Publication of WO2024252872A1 publication Critical patent/WO2024252872A1/ja
Priority to US19/406,145 priority patent/US20260101527A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks

Definitions

  • the present invention relates to a semiconductor device, a matching circuit, and a filter circuit.
  • Patent Document 1 Figures 1 and 2 show a semiconductor device in which an insulating layer, a first electrode layer, a dielectric layer, a second electrode layer, a moisture-resistant protective layer, and a resin protective layer are formed in that order on a substrate. Vias are formed through the moisture-resistant protective layer, the resin protective layer, etc., exposing a portion of the surface of the first and second electrode layers, and first and second external electrodes made of a seed layer, a first plating layer, and a second plating layer are formed on top of the vias.
  • Patent document 2 describes a technique for forming a Ni layer of uniform thickness on the surface of an Al electrode by electroless plating.
  • Patent Document 3 discloses a semiconductor device comprising a substrate, a first electrode layer provided on the substrate, a dielectric film provided on the first electrode layer, a second electrode layer provided on the dielectric film, a protective layer covering the first electrode layer and the second electrode layer, and an external electrode penetrating the protective layer, the dielectric film being made of silicon nitride, and the atomic concentration ratio of Si to the total amount of Si and N contained in the dielectric film being 43 atom% or more and 70 atom% or less.
  • Patent Document 1 a semiconductor process is used, and Al is used for the electrode layer.
  • Fig. 1 is a cross-sectional view showing a schematic diagram of a plating layer formed by electrolytic plating at a slow deposition rate, showing the state at the initial stage of electrolytic plating.
  • Fig. 2 is a cross-sectional view showing a schematic diagram of a plating layer formed by electrolytic plating at a slow deposition rate, showing the state after electrolytic plating is completed.
  • the Al layer 122 undergoes recrystallization due to the Al film formation temperature and the heat treatment of the dielectric layer (SiN film) and resin protective layer (polyimide) on top of it. Then, it becomes a polycrystalline film with random crystal orientation, and the size of the crystals grows to a size of several to 10 ⁇ m in the horizontal direction while the thickness direction is about 0.1 to 2 ⁇ m.
  • the seed layer 123 of the external electrode formed on this Al layer 122 is usually composed of a Ti layer 123a and a Cu layer 123b formed by a sputtering method, but the Ti layer 123a and the Cu layer 123b grow continuously, inheriting the crystallinity of the surface of the Al layer 122. Therefore, the horizontal crystal grain size of the Ti layer 123a and the Cu layer 123b is several to 10 ⁇ m, the same as that of the Al layer 122.
  • the plating layer 124 formed on the seed layer 123 is formed by electrolytic plating using Cu, Ni, Au, etc., and in this case, if the film growth rate is sufficiently slow, the Ni plating film grows preferentially from the grain boundaries of the seed layer 123, and growth from the surface other than the grain boundaries is very slow (see Figure 1). Therefore, as shown in Figure 2, film growth from the grain boundaries progresses horizontally, and while the entire surface is covered, growth in the film thickness direction does not progress, and after the entire surface is covered, the film growth rate is constant over the entire surface, so the surface unevenness of the Ni plating layer 124b becomes smaller. However, slowing down the film growth rate increases costs.
  • Figure 3 is a cross-sectional view that shows a schematic diagram of a plating layer formed by electrolytic plating at a fast film-forming rate, showing the state at the initial stage of electrolytic plating.
  • Figure 4 is a cross-sectional view that shows a schematic diagram of a plating layer formed by electrolytic plating at a fast film-forming rate, showing the state after electrolytic plating is completed.
  • the external electrode appearance extremely randomly rough, making it impossible to inspect the external electrode for other appearance defects (peeling film, dirt, scratches, pattern defects, etc.) using an automatic appearance inspection machine.
  • the surface roughness Ra of the plating must be 500 nm or less.
  • Figure 5 is a plan view that shows a schematic of the surface of an external electrode formed by electrolytic plating at a high film formation rate.
  • convex portions 126 are generated on the surface of the external electrode in a shape that borders random shapes that depend on the grain size of the large crystals 125 in the Al layer 122.
  • An automatic appearance inspection machine will erroneously detect this pattern of convex portions 126 as a defective appearance.
  • the Cu plating layer 124a does not have any surface irregularities, unlike the Ni plating layer 124b, regardless of the deposition rate.
  • Patent Document 2 describes an issue in which the growth rate of the Ni plating formed on the Al electrode differs depending on the crystal plane of the Al electrode, so if the crystals of the Al electrode are large, the Ni does not grow uniformly and unevenness occurs. For this reason, a layer (Al oxide layer) that breaks the continuity of the Al crystals is formed on the surface of the Al metal layer, and a second Al metal layer is formed on that surface to make the Al crystals smaller.
  • Patent Document 2 since electroless plating is used, there is no growth from grain boundaries, but the plating similarly grows continuously by taking over the crystals of the Al layer, and by reducing the crystal grain size of the Al layer, unevenness in the plating film is suppressed. As a specific measure, an Al oxide layer is formed on the surface of the Al layer, which increases the electrical resistance of the electrode. Therefore, although the semiconductor device functions as a heat sink, it does not function as an electrode and cannot be used as a capacitor.
  • the present invention has been made to solve the above problems, and aims to provide a semiconductor device in which the plating surface of the external electrodes is flat and can be inspected for visual defects using a visual inspection device, as well as a matching circuit and a filter circuit that include the semiconductor device.
  • the semiconductor device of the present invention comprises a substrate, an insulating layer provided on the substrate, a first electrode layer provided on the insulating layer, a dielectric film provided on the first electrode layer, a second electrode layer provided on the dielectric film, a moisture-resistant film covering the first electrode layer and the second electrode layer, and an external electrode penetrating the moisture-resistant film, the first electrode layer and the second electrode layer being made of Al or an alloy of Al, the external electrode having a first external electrode and a second external electrode electrically connected to the first electrode layer and the second electrode layer, respectively, the external electrode having a seed layer made of Cu/Ti, Cu/Cr or Cu/Nichrome, and a plating layer provided on the seed layer, the horizontal crystal grain size of the seed layer being 500 nm or less, and the horizontal crystal grain size of the plating layer being 500 nm or less.
  • the matching circuit of the present invention includes the semiconductor device of the present invention.
  • the filter circuit of the present invention includes the semiconductor device of the present invention.
  • the present invention provides a semiconductor device in which the plating surface of the external electrodes is flat and can be inspected for visual defects using a visual inspection device, as well as a matching circuit and a filter circuit that include the semiconductor device.
  • FIG. 1 is a cross-sectional view showing a schematic diagram of a plating layer formed by electrolytic plating at a slow film formation rate, and shows the initial stage of electrolytic plating.
  • FIG. 2 is a cross-sectional view showing a schematic diagram of a plating layer formed by electrolytic plating at a slow film formation rate, and shows the state after the electrolytic plating is completed.
  • FIG. 3 is a cross-sectional view showing a schematic diagram of a plating layer formed by electrolytic plating at a high film formation rate, showing the initial stage of electrolytic plating.
  • FIG. 4 is a cross-sectional view showing a schematic diagram of a plating layer formed by electrolytic plating at a high film formation rate, showing the state after the electrolytic plating is completed.
  • FIG. 1 is a cross-sectional view showing a schematic diagram of a plating layer formed by electrolytic plating at a slow film formation rate, and shows the initial stage of electrolytic plating.
  • FIG. 3 is a cross
  • FIG. 5 is a plan view showing a schematic view of the surface of an external electrode formed by electrolytic plating at a high film formation rate.
  • FIG. 6 is a cross-sectional view illustrating an example of a capacitor according to the first embodiment of the present invention.
  • FIG. 7 is a plan view illustrating an example of a capacitor according to the first embodiment of the present invention.
  • FIG. 8 is a cross-sectional view of the capacitor shown in FIG. 6, focusing on a region in which a first external electrode is formed.
  • FIG. 9 is a cross-sectional view of the capacitor shown in FIG. 6, focusing on a region in which the second external electrode is formed.
  • FIG. 10 is an enlarged plan view showing a schematic view of the surface of an external electrode of the capacitor shown in FIG. FIG.
  • FIG. 11 is a cross-sectional view showing a schematic example of a capacitor according to a second embodiment of the present invention, focusing on a first external electrode forming region.
  • FIG. 12 is a cross-sectional view showing a schematic example of a capacitor according to a second embodiment of the present invention, focusing on a second external electrode forming region.
  • FIG. 13 is a cross-sectional view showing a schematic example of a capacitor according to a third embodiment of the present invention, focusing on a first external electrode forming region.
  • FIG. 14 is a cross-sectional view showing a schematic example of a capacitor according to a third embodiment of the present invention, focusing on a second external electrode forming region.
  • FIG. 12 is a cross-sectional view showing a schematic example of a capacitor according to a second embodiment of the present invention, focusing on a first external electrode forming region.
  • FIG. 13 is a cross-sectional view showing a schematic example of a capacitor according to a third embodiment of the present
  • FIG. 15 is a cross-sectional view showing a schematic example of a capacitor according to a fourth embodiment of the present invention, focusing on a first external electrode forming region.
  • FIG. 16 is a cross-sectional view showing a schematic example of a capacitor according to a fourth embodiment of the present invention, focusing on a second external electrode forming region.
  • FIG. 17 is a plan view illustrating an example of the dividing layer illustrated in FIGS. 15 and 16.
  • FIG. 18 is a plan view diagrammatically illustrating another example of the dividing layer shown in FIGS. 15 and 16.
  • FIG. 19 is an explanatory diagram showing an example of a matching circuit including a semiconductor device of the present invention.
  • FIG. 20 is an explanatory diagram showing an example of a filter circuit including the semiconductor device of the present invention.
  • the present invention is not limited to the following configurations, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual preferred configurations of the present invention described below.
  • each embodiment will be referred to simply as the "semiconductor device of the present invention.”
  • the shape and arrangement of each component of the semiconductor device of the present invention are not limited to the examples shown in the drawings.
  • the semiconductor device of the present invention may be a capacitor itself (i.e., a capacitor element), or may be a device that includes a capacitor.
  • the surface roughness Ra of the insulating layer below the first electrode layer is controlled to be 5 nm or more and 500 nm or less.
  • FIG. 6 is a cross-sectional view showing an example of a capacitor according to the first embodiment of the present invention.
  • FIG. 7 is a plan view showing an example of a capacitor according to the first embodiment of the present invention.
  • FIG. 6 is a cross-sectional view taken along line I-I of the capacitor shown in FIG. 7.
  • the length direction, width direction, and thickness direction of a capacitor are defined as the directions indicated by arrows L, W, and T, respectively, as shown in Figures 6 and 7.
  • the length direction L, width direction W, and thickness direction T are mutually orthogonal.
  • the 6 and 7 includes a substrate 10, an insulating layer 21 provided on the substrate 10, a first electrode layer 22 provided on the insulating layer 21, a dielectric film 23 provided on the first electrode layer 22, a second electrode layer 24 provided on the dielectric film 23, a moisture-resistant film 25 covering the first electrode layer 22 and the second electrode layer 24, a protective layer 26 provided on the moisture-resistant film 25, and an external electrode 27 penetrating the moisture-resistant film 25 and the protective layer 26.
  • the first electrode layer 22 and the second electrode layer 24 are made of Al or an alloy of Al.
  • the external electrode 27 includes a first external electrode 27A connected to the first electrode layer 22 and a second external electrode 27B connected to the second electrode layer 24.
  • the first external electrode 27A penetrates the protective layer 26, the moisture-resistant film 25, and the dielectric film 23, and the second external electrode 27B penetrates the protective layer 26 and the moisture-resistant film 25.
  • the external electrodes 27 (first external electrode 27A and second external electrode 27B) have a seed layer 28 made of Cu/Ti, Cu/Cr, or Cu/nichrome, and a plating layer 29 provided on the seed layer 28.
  • the first electrode layer 22, the dielectric film 23, and the second electrode layer 24 are stacked in this order to form a MIM (Metal Insulator Metal) capacitor structure.
  • MIM Metal Insulator Metal
  • FIG. 8 is a cross-sectional view of the capacitor shown in FIG. 6, focusing on the first external electrode formation region.
  • FIG. 9 is a cross-sectional view of the capacitor shown in FIG. 6, focusing on the second external electrode formation region.
  • the horizontal crystal grain size of the seed layer 28 is 500 nm or less
  • the horizontal crystal grain size of the plating layer 29 is 500 nm or less.
  • the plating surfaces of the first external electrode 27A and the second external electrode 27B flat.
  • the surface roughness Ra of the first external electrode 27A and the second external electrode 27B is 500 nm or less.
  • a visual inspection device can generally detect defects of 0.5 to 1 ⁇ m or more in size (peeling, dirt, scratches, pattern defects, etc.), it is possible to inspect the capacitor 1, and in particular the external electrode 27, for visual defects using the visual inspection device.
  • FIG. 10 is a schematic plan view showing an enlarged view of the surface of the external electrode of the capacitor shown in FIG. 7.
  • the appearance inspection device may erroneously detect the unevenness of the plating surface of the external electrode 27 as an appearance defect.
  • the horizontal crystal grain size of the seed layer 28 is preferably 5 nm or more and 500 nm or less, and more preferably 5 nm or more and 200 nm or less.
  • the horizontal crystal grain size of the plating layer 29 is preferably 5 nm or more and 500 nm or less, and more preferably 5 nm or more and 200 nm or less.
  • the horizontal crystal grain size is measured by observing the cross section of the layer with a scanning electron microscope (SEM), measuring the grain size (maximum length) of 50 random crystal grains in the in-plane direction (direction perpendicular to the thickness direction) in the observed image, and calculating the average.
  • SEM scanning electron microscope
  • the rough surface of the base layer of the first external electrode 27A and the second external electrode 27B made of Al or an Al alloy makes the crystal grain size of the first external electrode 27A and the second external electrode 27B small during film formation, and is also unlikely to become large during subsequent heat treatment. This reduces the horizontal crystal grain size of the seed layer 28 on the first external electrode 27A and the second external electrode 27B, as described above, and the horizontal crystal grain size of the plating layer (preferably a Ni plating layer) on the seed layer 28. As a result, the unevenness of the surfaces of the first external electrode 27A and the second external electrode 27B can be controlled to be small.
  • the surface roughness Ra of the insulating layer 21 below the first electrode layer 22 is 5 nm or more and 500 nm or less
  • the first electrode layer 22 and the second electrode layer 24 contain crystals grown according to the surface roughness of the insulating layer 21
  • the horizontal crystal grain size of the first electrode layer 22 and the second electrode layer 24 is 500 nm or less
  • the seed layer 28 contains crystals grown by inheriting the crystals of the first electrode layer 22 and the second electrode layer 24.
  • the horizontal crystal grain size of the plating layer preferably a Ni plating layer
  • the horizontal crystal grain size of the plating layer that grows by inheriting the crystals of the seed layer 28 can be set to 500 nm or less.
  • the horizontal crystal grain size of the first electrode layer 22 above it can be controlled to 500 nm or less.
  • the horizontal crystal grain size of the seed layer 28 and plating layer 29 of the first external electrode 27A, which have grown by inheriting the crystals of the first electrode layer 22, can also be controlled to 500 nm or less.
  • the horizontal crystal grain size of the first electrode layer 22 thereon can be controlled to 500 nm or less, and further, the surface roughness of the dielectric film 23 above the first electrode layer 22 can also be controlled (preferably 5 nm or more and 500 nm or less).
  • the horizontal crystal grain size of the second electrode layer 24 above the dielectric film 23 can be controlled to 500 nm or less. Therefore, the horizontal crystal grain size of the seed layer 28 and plating layer 29 of the second electrode layer 24 that have grown by inheriting the crystals of the second electrode layer 24 can also be 500 nm or less.
  • the surface of the insulating layer 21 (e.g., SiO 2 ) under the first electrode layer 22 is not roughened by a normal film formation method such as thermal oxidation of Si, sputtering, CVD (chemical vapor deposition), or deposition, and the surface roughness Ra is less than 5 nm. If the surface roughness Ra of the insulating layer 21 is less than 5 nm, the crystals of the first electrode layer 22 and the second electrode layer 24 are not refined. Therefore, the surface roughness can be adjusted to a desired value by grinding or polishing the surface of the insulating layer 21, or etching the surface by dry etching such as reactive ion etching (RIE) or milling, or wet etching using hydrofluoric acid.
  • RIE reactive ion etching
  • surface roughness Ra can be measured as the arithmetic mean roughness Ra measured in accordance with JIS-B0601:2001.
  • the surface roughness Ra of the insulating layer 21 is preferably 5 nm or more and 500 nm or less, and more preferably 5 nm or more and 200 nm or less.
  • the period of the unevenness on the surface of the insulating layer 21 is preferably controlled to be 20 nm or more and 500 nm or less, and more preferably 20 nm or more and 200 nm or less.
  • the horizontal crystal grain size of the first electrode layer 22 and the second electrode layer 24 is preferably 5 nm or more and 500 nm or less, and more preferably 5 nm or more and 200 nm or less.
  • the substrate 10 is not particularly limited, but is preferably a semiconductor substrate such as a silicon substrate or a gallium arsenide substrate.
  • the insulating layer 21 is provided so as to cover the entirety of one of the main surfaces of the substrate 10.
  • the insulating layer 21 may be provided so as to cover a portion of one of the main surfaces of the substrate 10, but it must be provided in an area that is larger than the first electrode layer 22 and that overlaps the entirety of the first electrode layer 22.
  • the material constituting the insulating layer 21 is not particularly limited, but preferable examples include SiO2 , SiN, Al2O3 , HfO2 , Ta2O5 , ZrO2 , etc. All of these materials are amorphous.
  • the first electrode layer 22 is provided at a position away from the edge of the substrate 10. In other words, the edge of the first electrode layer 22 is located inside the edge of the substrate 10.
  • the first electrode layer 22 is made of Al or an Al alloy.
  • Al alloys include AlSi.
  • the dielectric film 23 is provided so as to cover the first electrode layer 22 except for the opening.
  • the end of the dielectric film 23 is also provided on the surface of the insulating layer 21 from the end of the first electrode layer 22 to the end of the substrate 10. The end of the dielectric film 23 does not have to be provided to the end of the substrate 10.
  • the material constituting the dielectric film 23 is not particularly limited, but preferably includes oxides or nitrides such as SiO2 , SiN , Al2O3 , HfO2 , and Ta2O5 .
  • the second electrode layer 24 is disposed opposite the first electrode layer 22 with the dielectric film 23 in between.
  • the second electrode layer 24 is made of Al or an Al alloy.
  • Al alloys include AlSi.
  • the moisture-resistant film 25 is provided so as to cover the dielectric film 23 and the second electrode layer 24 except for the opening. The provision of the moisture-resistant film 25 enhances the moisture resistance of the capacitor element, particularly the dielectric film 23.
  • the material constituting the moisture-resistant film 25 is not particularly limited, but preferably includes moisture-resistant materials such as SiO 2 and SiN.
  • the protective layer 26 has openings at positions overlapping the openings of the dielectric film 23 and moisture-resistant film 25 (openings overlapping the first electrode layer 22) and at a position overlapping the opening of the moisture-resistant film 25 (openings overlapping the second electrode layer 24).
  • the provision of the protective layer 26 protects the capacitor element, and in particular the dielectric film 23, from moisture. Note that the protective layer 26 does not necessarily have to be provided.
  • the material constituting the protective layer 26 is not particularly limited, but preferred examples include resin materials such as polyimide resin and solder resist resin.
  • the external electrodes 27 (first external electrode 27A and second external electrode 27B) have a multi-layer structure, and from the substrate 10 side, have a seed layer 28 and a plating layer 29.
  • the outermost surface of the external electrodes 27 is preferably made of Au or Sn.
  • the seed layer 28 is made of Cu/Ti, Cu/Cr, or Cu/Nichrome. Such a seed layer 28 can grow continuously while inheriting the crystallinity of the surface of the first electrode layer 22 or the second electrode layer 24.
  • element A/element B refers to a laminate in which a conductive layer made of element B and a conductive layer made of element A are laminated in this order from the substrate side.
  • the seed layer 28 may be a laminate in which a Ti layer 28a and a Cu layer 28b are laminated in this order from the substrate 10 side, as shown in Figures 8 and 9.
  • the seed layer 28 is formed by sputtering or vapor deposition.
  • the seed layer 28 for example a Cu/Ti layer
  • the Q value of the capacitor will deteriorate due to the resistance of the natural oxide film on the surface of this Al electrode layer. Therefore, by performing surface dry etching such as milling in a vacuum immediately before forming the seed layer 28 and then continuously forming the seed layer 28 in a vacuum, the influence of the natural oxide film on the surface of the Al electrode layer can be eliminated and the Al electrode layer and the seed layer 28 can be connected with low resistance.
  • the seed layer 28 grows by taking over the crystals on the surface of the Al electrode layer, so that the horizontal crystal grain size of the seed layer 28 can be controlled to 500 nm or less.
  • the seed layer 28 is formed on an electrode layer made of an Al alloy.
  • the plating layer 29 has, in order from the substrate 10 side, a first plating layer 30 and a second plating layer 31.
  • the material of the first plating layer 30 is not particularly limited, but it is preferable for it to include a Ni plating layer formed by electrolytic plating of Ni. As described above, if the deposition rate is increased, the surface of the Ni plating layer is likely to have protrusions, but in this embodiment, since the horizontal crystal grain size of the seed layer 28 is 500 nm or less, even if the deposition rate is increased, the crystal grain size of the Ni plating layer is also 500 nm or less, and the unevenness of the surface of the Ni plating layer can be effectively reduced.
  • the first plating layer 30 may be a single-layer structure of a Ni plating layer, or may be a laminated structure in which a Cu plating layer 30a and a Ni plating layer 30b are laminated in this order from the substrate 10 side, as shown in Figures 8 and 9.
  • Examples of materials that can be used for the second plating layer 31 include gold (Au) and tin (Sn).
  • an Au/Ni/Cu layer or an Au/Ni layer may be formed on the seed layer 28 by electrolytic plating.
  • the crystal grain size of the underlying electrode layer first electrode layer 22 or second electrode layer 24
  • the plating surface of the Cu or Ni layer becomes rough when the deposition rate is increased.
  • the crystal grain size of the underlying electrode layer to be small, the plating surface does not become rough even if the deposition rate is maximized below the current density at which the plating solution does not decompose.
  • the plating film that grows from the crystal grain boundaries of the seed layer 28 covers the grain boundaries at an early stage by making the crystal grain size of the seed layer 28 sufficiently small, and after the entire surface is covered, the entire surface grows at the same deposition rate. Similarly, the second and subsequent plating layers do not become rough.
  • the constituent materials of the first external electrode 27A and the second external electrode 27B may be the same or different.
  • the capacitor 1 shown in Figures 6 and 7 is manufactured, for example, by the method described in Patent Document 3.
  • the capacitor according to the second embodiment of the present invention differs from the first embodiment in that the surface roughness Ra of the Si single crystal substrate is controlled to be 5 nm or more and 500 nm or less.
  • the film thickness of the insulating layer 21 becomes non-uniform, which may cause the parasitic capacitance via the semiconductor substrate to become non-uniform, resulting in a deterioration in the capacitance accuracy of the capacitor 1.
  • FIG. 11 is a cross-sectional view showing a schematic example of a capacitor according to a second embodiment of the present invention, focusing on the first external electrode formation region.
  • FIG. 12 is a cross-sectional view showing a schematic example of a capacitor according to a second embodiment of the present invention, focusing on the second external electrode formation region.
  • the substrate 10 is a Si single crystal substrate 10a
  • the surface roughness Ra of the Si single crystal substrate 10a is 5 nm or more and 500 nm or less
  • the insulating layer 21 is formed along the surface of the Si single crystal substrate 10a.
  • the roughening of the Si single crystal substrate 10a can be adjusted to the desired surface roughness by grinding or polishing the flat surface of the Si single crystal substrate, or by etching using dry etching such as reactive ion etching (RIE) or milling, or wet etching using an organic alkaline solution.
  • RIE reactive ion etching
  • the insulating layer 21 on top of it can also have a similar surface roughness.
  • the surface roughness Ra of the Si single crystal substrate 10a is preferably 5 nm or more and 500 nm or less, and more preferably 5 nm or more and 200 nm or less.
  • the period of the unevenness on the surface of the Si single crystal substrate 10a is preferably controlled to 20 nm or more and 500 nm or less, and more preferably 20 nm or more and 200 nm or less.
  • the capacitor according to the third embodiment of the present invention differs from the first embodiment in that a polycrystalline Si layer having a surface roughness Ra controlled to 5 nm or more and 500 nm or less is formed on a single crystal Si substrate having a flat surface.
  • FIG. 13 is a cross-sectional view showing a schematic example of a capacitor according to a third embodiment of the present invention, focusing on the first external electrode formation region.
  • FIG. 14 is a cross-sectional view showing a schematic example of a capacitor according to a third embodiment of the present invention, focusing on the second external electrode formation region.
  • the substrate 10 has a flat surface of a single crystal Si substrate 10b and a polycrystalline Si layer 10c formed on the surface of the single crystal Si substrate 10b, and the surface roughness Ra of the polycrystalline Si layer 10c is 5 nm or more and 500 nm or less.
  • the polycrystalline Si layer 10c with a controlled surface roughness Ra below the insulating layer 21 and forming the insulating layer 21 along the surface of the polycrystalline Si layer 10c, it is possible to roughen the surface of the insulating layer 21 without degrading the film thickness accuracy of the insulating layer 21. Therefore, the capacitance variation of the capacitor due to the film thickness distribution of the insulating layer 21 can be reduced.
  • the grain size of the polycrystals can be controlled with precision. Therefore, the surface roughness Ra of the substrate 10 can be controlled more precisely (more uniformly and more constant) than when other methods such as etching or grinding are used as in the second embodiment.
  • the polycrystalline Si layer 10c is formed by depositing a polycrystalline Si film on the surface of a flat single crystal Si substrate 10b by a CVD method or the like.
  • the crystal grain size of the polycrystalline Si layer 10c can be easily controlled to a stable size compared to the amorphous insulating layer 21 and the single crystal Si substrate 10b.
  • the surface roughness of the insulating layer 21 formed thereon can be more easily controlled to the desired roughness.
  • the surface roughness Ra of the polycrystalline Si layer 10c By controlling the surface roughness Ra of the polycrystalline Si layer 10c to be 5 nm or more and 500 nm or less, the insulating layer 21 on top can also have an equivalent surface roughness.
  • the surface roughness Ra of the polycrystalline Si layer 10c is preferably 5 nm or more and 500 nm or less, and more preferably 5 nm or more and 200 nm or less.
  • the period of the unevenness on the surface of the polycrystalline Si layer 10c is preferably controlled to be 20 nm or more and 500 nm or less, and more preferably 20 nm or more and 200 nm or less.
  • the surface roughness Ra of the Si single crystal substrate 10b is not particularly limited, but the Si single crystal substrate 10b is usually mirror-finished and has a surface roughness Ra of less than 5 nm.
  • the capacitor according to the fourth embodiment of the present invention differs from the first embodiment in that the surfaces of the first and second electrode layers further include a dividing layer formed of a material that prevents the seed layer thereon from inheriting the crystallinity of the first and second electrode layers.
  • the surfaces of the first and second electrode layers usually have a natural oxide film of Al or an Al alloy, and forming a seed layer (e.g., a Cu/Ti layer) on top of it in this state results in a large resistance and deteriorates the Q value of the capacitor.
  • a seed layer e.g., a Cu/Ti layer
  • FIG. 15 is a cross-sectional view showing a schematic example of a capacitor according to a fourth embodiment of the present invention, focusing on the first external electrode formation region.
  • FIG. 16 is a cross-sectional view showing a schematic example of a capacitor according to a fourth embodiment of the present invention, focusing on the second external electrode formation region.
  • the surfaces of the first electrode layer 22 and the second electrode layer 24 are further provided with dividing layers 33 formed of a material that does not inherit the crystallinity of the first electrode layer 22 and the second electrode layer 24, in a pattern with a period of 500 nm or less, and the seed layer 28 thereon is made of a material that does not inherit the crystallinity of the first electrode layer 22 and the second electrode layer 24.
  • This makes it possible to make the horizontal crystal grain size of the seed layer 28 500 nm or less. Therefore, it becomes possible to inspect the capacitor 1, and in particular the external electrode 27, for visual defects using a visual inspection device.
  • the Cu/Ti layer grows as uniaxially oriented crystals with Ti at (0001) and Cu at (111) in the direction perpendicular to the oxide film of the Al electrode layer, and in the area where the oxide film has been removed, grows as crystals that inherit the random crystal orientation of the Al film.
  • the horizontal crystal grain size of the seed layer 28 can be made 500 nm or less.
  • the formation of the dividing layer 33 i.e., the patterning of the oxide film of the first electrode layer 22 and the second electrode layer 24, can be performed, for example, as follows. First, a metal oxide film (e.g., an Al oxide film) is additionally formed on the surface of the natural oxide film (e.g., an Al oxide film) of the first electrode layer 22 and the second electrode layer 24, and then the metal oxide film is patterned by photolithography and a dry etching method or a wet etching method. Then, just before depositing the seed layer 28 by sputtering, the natural oxide film that has been generated again is removed by a dry etching method by an amount corresponding to the thickness of the film, and the seed layer 28 is deposited.
  • a metal oxide film e.g., an Al oxide film
  • the natural oxide film that has been generated again is removed by a dry etching method by an amount corresponding to the thickness of the film, and the seed layer 28 is deposited.
  • Materials that can be formed on the surface of the natural oxide film (e.g., Al oxide film) on the surfaces of the first electrode layer 22 and the second electrode layer 24 may be Si, Ta, SiO 2 , SiN, etc., in addition to Al oxide film. This makes it possible to reduce the electrical resistance between the first electrode layer 22 and the second electrode layer 24 and the seed layer 28, and similarly makes it possible to make the horizontal crystal grain size of the plating layer 29 formed thereon 500 nm or less, thereby reducing the surface unevenness.
  • the period of the pattern of the dividing layer 33 is preferably greater than 0 nm and less than 500 nm, and more preferably greater than 20 nm and less than 200 nm.
  • FIG. 17 is a plan view showing a schematic example of the dividing layer shown in FIGS. 15 and 16.
  • FIG. 18 is a plan view showing a schematic example of another dividing layer shown in FIGS. 15 and 16.
  • the dividing layer 33 is preferably formed in a pattern in which dots 34, such as squares such as rectangles or circles, are periodically arranged in a two-dimensional manner.
  • each dot 34 is made of a material that does not inherit the crystals of the first electrode layer 22 and the second electrode layer 24, and the pitch between adjacent dots 34 is 500 nm or less.
  • the size of each dot 34 is preferably approximately the same as the desired crystal grain size in the horizontal direction of the seed layer 28 and the plating layer 29.
  • the exposed area of the first electrode layer 22 and the second electrode layer 24 (the area of the region not covered by the dividing layer 33 (dots 34)) is preferably 50% or more, and more preferably 70% or more.
  • Figures 17 and 18 show a case where all dots 34 have the same planar shape
  • the pattern of the dividing layer 33 may be a pattern in which dots of different planar shapes are mixed.
  • the horizontal crystal grain size of the underlying seed layer is 500 nm or less, it is possible to almost completely improve the detection of surface irregularities on the external electrode caused by crystal grain boundaries as defects. This is thought to be because the horizontal crystal grain size of the Ni plating layer is also 500 nm or less, just like the seed layer. It was also found that if the horizontal crystal grain size of the underlying seed layer is 200 nm or less, surface irregularities on the external electrode caused by crystal grain boundaries are not detected as defects. This is thought to be because the horizontal crystal grain size of the Ni plating layer is also 200 nm or less, just like the seed layer.
  • the semiconductor device of the present invention is preferably used as a capacitor in a matching circuit or a filter circuit.
  • a matching circuit or a filter circuit including the semiconductor device of the present invention is also one aspect of the present invention.
  • FIG. 19 is an explanatory diagram showing an example of a matching circuit equipped with the semiconductor device of the present invention.
  • the semiconductor device of the present invention can be used for the capacitor C of the matching circuit shown in FIG. 19.
  • FIG. 20 is an explanatory diagram showing an example of a filter circuit equipped with a semiconductor device of the present invention.
  • the semiconductor device of the present invention can be used for the capacitor C1 of the filter circuit shown in FIG. 20.
  • the external electrodes each have a seed layer made of Cu/Ti, Cu/Cr, or Cu/nichrome, and a plating layer provided on the seed layer, the seed layer has a horizontal crystal grain size of 500 nm or less;
  • the semiconductor device wherein the horizontal crystal grain size of the plating layer is 500 nm or less.
  • the surface roughness Ra of the insulating layer is 5 nm or more and 500 nm or less
  • the first electrode layer and the second electrode layer include crystals grown according to the surface roughness of the insulating layer
  • the first electrode layer and the second electrode layer have a horizontal crystal grain size of 500 nm or less
  • the substrate is a Si single crystal substrate,
  • the surface roughness Ra of the Si single crystal substrate is 5 nm or more and 500 nm or less,
  • the substrate has a single crystal Si substrate having a flat surface and a polycrystalline Si layer formed on the surface of the single crystal Si substrate;
  • the semiconductor device described in ⁇ 1> further comprises a dividing layer formed on the surfaces of the first electrode layer and the second electrode layer in a pattern with a period of 500 nm or less, and the seed layer thereon is made of a material that does not inherit the crystallinity of the first electrode layer and the second electrode layer.
  • a matching circuit comprising the semiconductor device according to any one of ⁇ 1> to ⁇ 5>.
  • a filter circuit comprising the semiconductor device according to any one of ⁇ 1> to ⁇ 5>.
  • Capacitor semiconductor device
  • REFERENCE SIGNS LIST 10
  • Polycrystalline Si layer 21 Insulating layer 22
  • First electrode layer 23 Dielectric film 24
  • Second electrode layer 25
  • Moisture-resistant film 26
  • Protective layer 27
  • External electrode 27A
  • First external electrode 27B
  • Second external electrode 28
  • Seed layer 28a
  • Ti layer 28b
  • Cu layer 29
  • Second plating layer 34

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  • Microelectronics & Electronic Packaging (AREA)
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  • Semiconductor Integrated Circuits (AREA)
PCT/JP2024/017953 2023-06-07 2024-05-15 半導体装置、マッチング回路及びフィルタ回路 Ceased WO2024252872A1 (ja)

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US19/406,145 US20260101527A1 (en) 2023-06-07 2025-12-02 Semiconductor device, matching circuit, and filter circuit

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08340091A (ja) * 1995-03-22 1996-12-24 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2007258713A (ja) * 2006-03-17 2007-10-04 Sychip Inc 集積受動デバイス基板
JP2008010875A (ja) * 2006-06-28 2008-01-17 Gennum Corp ペロブスカイト相またはパイロクロア相誘電体を有するコンデンサ用のハーメチックパッシベーション層構造
WO2022239722A1 (ja) * 2021-05-10 2022-11-17 株式会社村田製作所 半導体装置、マッチング回路及びフィルタ回路
WO2022239719A1 (ja) * 2021-05-10 2022-11-17 株式会社村田製作所 受動電子部品用の支持基板、受動電子部品、半導体装置、マッチング回路及びフィルタ回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08340091A (ja) * 1995-03-22 1996-12-24 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2007258713A (ja) * 2006-03-17 2007-10-04 Sychip Inc 集積受動デバイス基板
JP2008010875A (ja) * 2006-06-28 2008-01-17 Gennum Corp ペロブスカイト相またはパイロクロア相誘電体を有するコンデンサ用のハーメチックパッシベーション層構造
WO2022239722A1 (ja) * 2021-05-10 2022-11-17 株式会社村田製作所 半導体装置、マッチング回路及びフィルタ回路
WO2022239719A1 (ja) * 2021-05-10 2022-11-17 株式会社村田製作所 受動電子部品用の支持基板、受動電子部品、半導体装置、マッチング回路及びフィルタ回路

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