WO2024251043A1 - 像素驱动电路及驱动方法、显示基板、显示装置 - Google Patents

像素驱动电路及驱动方法、显示基板、显示装置 Download PDF

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Publication number
WO2024251043A1
WO2024251043A1 PCT/CN2024/096674 CN2024096674W WO2024251043A1 WO 2024251043 A1 WO2024251043 A1 WO 2024251043A1 CN 2024096674 W CN2024096674 W CN 2024096674W WO 2024251043 A1 WO2024251043 A1 WO 2024251043A1
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Prior art keywords
node
unit
control
signal terminal
control signal
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PCT/CN2024/096674
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English (en)
French (fr)
Inventor
黄耀
董向丹
胡明
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
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Publication of WO2024251043A1 publication Critical patent/WO2024251043A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular to a pixel driving circuit and driving method, a display substrate, and a display device.
  • OLED organic light emitting diode
  • OLED display devices have different requirements for the screen refresh frequency of display devices in different application scenarios. For example, in game application scenarios, the display device is required to have a higher screen refresh frequency to meet the game function requirements. In business application scenarios, the display device is required to have a lower screen refresh frequency to meet the requirements of lower power consumption and higher working time.
  • Embodiments of the present disclosure provide a pixel driving circuit and driving method, a display substrate, and a display device.
  • an embodiment of the present disclosure provides a pixel driving circuit, the pixel driving circuit comprising: a first light emitting control unit, a threshold compensation unit, a compensation delay unit, a second light emitting control unit, a data writing unit, a first reset unit, a driving unit, and a second reset unit;
  • the first reset unit, the threshold compensation unit and the driving unit are connected to a first node, the first light emitting control unit, the data writing unit, the compensation delay unit and the driving unit are connected to a second node, the threshold compensation unit, the second light emitting control unit and the driving unit are connected to a third node, the second light emitting control unit, the second reset unit and the light emitting unit are connected to a fourth node, and the second reset unit is also connected to the driving unit;
  • the first reset unit is also connected to the first control signal terminal and the first reset signal terminal, and is configured In response to the control of the first control signal provided by the first control signal terminal, writing the first reset voltage provided by the first reset signal terminal to the first node;
  • the data writing unit is also connected to the second control signal terminal and the data signal terminal, and is configured to write the data voltage provided by the data signal terminal to the second node in response to the control of the second control signal provided by the second control signal terminal, and also provide the data voltage to the compensation delay unit;
  • the threshold compensation unit is also connected to the first power supply terminal and the third control signal terminal, and is configured to electrically connect the first node and the third node in response to the control of the third control signal provided by the third control signal terminal, so that the voltage of the second node charges the first node through the driving unit, and the voltage of the first node is maintained at a preset voltage;
  • the compensation delay unit is also connected to the first power supply terminal, and is configured to store the data voltage provided by the data writing unit, and provide the stored data voltage to the second node, so as to continuously charge the first node through the driving unit;
  • the first light emitting control unit is also connected to the first power supply terminal and the fourth control signal terminal, and is configured to write the power supply voltage provided by the first power supply terminal to the second node in response to the control of the fourth control signal provided by the fourth control signal terminal;
  • the second light emitting control unit is further connected to the fourth control signal terminal and is configured to electrically connect the third node and the fourth node in response to the control of a fourth control signal provided by the fourth control signal terminal;
  • the driving unit is configured to respond to the control of the preset voltage provided by the first node and output a corresponding driving current according to the power supply voltage provided by the second node, and the driving current is provided to the fourth node through the second light emitting control unit to drive the light emitting unit to emit light;
  • the second reset unit is also connected to the fifth control signal terminal, the second reset signal terminal, and the third reset signal terminal, and is configured to write the second reset signal provided by the second reset signal terminal to the fourth node in response to the control of the fifth control signal provided by the fifth control signal terminal, and write the third reset signal provided by the third reset signal terminal to the second node or the third node.
  • the pixel driving circuit according to claim 1 is characterized in that the first reset unit comprises: a first transistor;
  • the control electrode of the first transistor is connected to the first control signal terminal, the first electrode is connected to the first reset signal terminal, and the second electrode is connected to the first node.
  • the threshold compensation unit includes: a first capacitor and a second transistor;
  • a first end of the first capacitor is connected to the first power supply end, and a second end is connected to the first node;
  • the control electrode of the second transistor is connected to the third control signal terminal, the first electrode is connected to the third node, and the second electrode is connected to the first node.
  • the driving unit includes: a third transistor
  • the control electrode of the third transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node.
  • the first light emitting control unit includes: a fifth transistor
  • the control electrode of the fifth transistor is connected to the fourth control signal terminal, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second node.
  • the second light emitting control unit includes: a sixth transistor
  • the control electrode of the sixth transistor is connected to the fourth control signal terminal, the first electrode is connected to the third node, and the second electrode is connected to the fourth node.
  • the second reset unit is connected to the driving unit at the second node, and the second reset unit includes: a seventh transistor and an eighth transistor;
  • the control electrode of the seventh transistor is connected to the fifth control signal terminal, the first electrode is connected to the second reset signal terminal, and the second electrode is connected to the fourth node;
  • the control electrode of the eighth transistor is connected to the fifth control signal terminal, the first electrode is connected to the third reset signal terminal, and the second electrode is connected to the second node.
  • the second reset unit and the driving unit are connected to the third node, and the second reset unit includes: a seventh transistor and an eighth transistor;
  • the control electrode of the seventh transistor is connected to the fifth control signal terminal, the first electrode is connected to the second reset signal terminal, and the second electrode is connected to the fourth node;
  • the control electrode of the eighth transistor is connected to the fifth control signal terminal, the first electrode is connected to the third reset signal terminal, and the second electrode is connected to the third node.
  • the compensation delay unit includes: a second capacitor
  • a first end of the second capacitor is connected to the first power supply end, and a second end of the second capacitor is connected to the second node.
  • the data writing unit includes: a fourth transistor
  • the control electrode of the fourth transistor is connected to the second control signal terminal, the first electrode is connected to the data signal terminal, and the second electrode is connected to the second node.
  • the pixel driving circuit further includes: a charging compensation control unit;
  • One end of the compensation delay unit is connected to the first power supply end, and the other end is connected to the second node through the charging compensation control unit;
  • the data writing unit is connected to the second node through the charging compensation control unit;
  • the compensation delay unit includes: a second capacitor, wherein a first end of the second capacitor is connected to the first power supply end, and a second end is connected to the charging compensation control unit.
  • FIG1 is a schematic structural diagram of a display substrate in an embodiment of the present disclosure.
  • FIG2 is a block diagram of a pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG3 is a block diagram of another pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG4 is a schematic diagram of a circuit structure of a pixel driving circuit in an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a circuit structure of another pixel driving circuit in an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a circuit structure of another pixel driving circuit in an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of a circuit structure of another pixel driving circuit in an embodiment of the present disclosure.
  • FIG8 is a working timing diagram of the pixel driving circuit shown in FIG4 or FIG5;
  • FIG9 is a schematic diagram showing a comparison of threshold voltage compensation effects
  • FIG. 10 is a schematic flow chart of a driving method of a pixel driving circuit provided in an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same or similar characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode.
  • transistors can be divided into N-type transistors and P-type transistors; when the transistor is an N-type transistor, its on-voltage is a high-level voltage and its off-voltage is a low-level voltage; when the transistor is a P-type transistor, its on-voltage is a low-level voltage and its off-voltage is a high-level voltage.
  • the "effective level” refers to the voltage that can control the conduction of the corresponding transistor
  • the “ineffective level” refers to the voltage that can control the cutoff of the corresponding transistor; therefore, when the transistor is an N-type transistor, the effective level refers to the high level, and the ineffective level refers to the low level; when the transistor is a P-type transistor, the effective level refers to the low level, and the ineffective level refers to the high level.
  • the embodiments of the present disclosure are described using a P-type transistor.
  • the first electrode is the drain of the P-type transistor, and the second electrode is the source of the P-type transistor.
  • the N-type is the opposite.
  • the embodiments of the present disclosure may also use N-type transistors to implement the technical solutions of the following embodiments, which is something that a person skilled in the art can easily think of without creative work, and is therefore also within the protection scope of the embodiments of the present disclosure.
  • all transistors in the pixel driving circuit are N-type transistors or N-type transistors.
  • the case where the transistors are P-type transistors is only a preferred solution in the embodiments of the present disclosure.
  • all transistors in the pixel driving circuit can be prepared simultaneously based on the same process, which is beneficial to shorten the preparation cycle.
  • some transistors in the pixel driving circuit can be N-type transistors, and some transistors can be P-type transistors.
  • Figure 1 is a schematic diagram of the structure of a display substrate in an embodiment of the present disclosure.
  • the display substrate includes a base substrate (not shown in the figure) and a plurality of pixel units located on the base substrate, and each pixel unit includes a plurality of sub-pixels P.
  • a plurality of pixel units may be arranged in an array, and a plurality of sub-pixels P in each pixel unit may also be arranged in an array.
  • FIG1 only exemplarily shows a situation where a plurality of sub-pixels P are arranged in an array, and the embodiments of the present disclosure include but are not limited to this, and the plurality of sub-pixels P in the embodiments of the present disclosure may also be arranged in other arrangements.
  • the display substrate further includes a plurality of gate lines Gate extending along the row direction and a plurality of data lines Data extending along the column direction, wherein the gate lines Gate and the data lines Data are arranged to cross and define sub-pixels P.
  • the gate lines Gate are used to provide gate scanning signals to the correspondingly connected sub-pixels P
  • the data lines Data are used to provide the required data signals Vdata to the correspondingly connected sub-pixels P.
  • Figure 1 only exemplarily shows a situation in which each row of gate lines Gate is connected to a row of sub-pixels P and each column of data lines Data is connected to a column of sub-pixels P.
  • the embodiments of the present disclosure include but are not limited to this.
  • two rows of gate lines Gate may be set corresponding to each row of sub-pixels P.
  • some sub-pixels P are connected to a corresponding row of gate lines gate, and another part of the sub-pixels P are connected to another corresponding row of gate lines Gate.
  • the display substrate further includes a plurality of power supply lines extending along the column direction, wherein each column of sub-pixels P may be provided with a corresponding power supply line, and the power supply line is used to provide the required power supply voltage VDD to the correspondingly connected sub-pixels P.
  • FIG1 only exemplarily shows a situation where each column of sub-pixels P may be provided with a corresponding power supply line, and the embodiment of the present disclosure includes but is not limited to this, and a power supply line may also be provided for each plurality of columns (e.g., 2 columns, 3 columns, etc.) of sub-pixels P.
  • each sub-pixel P includes a pixel driving circuit and a light-emitting device, wherein the pixel driving circuit is connected to a corresponding gate line Gate, a corresponding data line Data, a corresponding power supply line, and a corresponding light-emitting device, and the pixel driving circuit can provide a driving current to the light-emitting device according to a data signal Vdata provided by the data line Data and a power supply voltage VDD provided by the power supply line, so as to drive the light-emitting device.
  • the device emits light;
  • the light-emitting device may be a current-driven light-emitting device, for example, the light-emitting device may be an OLED light-emitting device or an AMOLED (Active-Matrix Organic Light-Emitting Diode) light-emitting device, etc.
  • OLED Organic Light-Emitting Diode
  • Figure 2 is a block diagram of the composition of a pixel driving circuit in an embodiment of the present disclosure.
  • the pixel driving circuit of each sub-pixel P may include: a first light-emitting control unit 21, a threshold compensation unit 22, a compensation delay unit 23, a second light-emitting control unit 24, a data writing unit 25, a first reset unit 26, a driving unit 27 and a second reset unit 28.
  • the first reset unit 26, the threshold compensation unit 22 and the driving unit 27 are connected to the first node N1
  • the first light-emitting control unit 21, the data writing unit 25, the compensation delay unit 23 and the driving unit 27 are connected to the second node N2
  • the threshold compensation unit 22, the second light-emitting control unit 24 and the driving unit 27 are connected to the third node N3
  • the second light-emitting control unit 24, the second reset unit 28 and the light-emitting unit 29 are connected to the fourth node N4, and the second reset unit 28 is also connected to the driving unit 27.
  • the first reset unit 26 is also connected to the first control signal terminal RESET and the first reset signal terminal INIT1, and is configured to respond to the control of the first control signal provided by the first control signal terminal RESET, and write the first reset voltage Vinit1 provided by the first reset signal terminal INIT1 to the first node N1 to reset the voltage of the first node N1.
  • the data writing unit 25 is also connected to the second control signal terminal Gate1 and the data signal terminal Data, and is configured to write the data voltage Vdata provided by the data signal terminal Data to the second node N2 in response to the control of the second control signal provided by the second control signal terminal Gate1, and also provide the data voltage Vdata to the compensation delay unit 23.
  • the threshold compensation unit 22 is also connected to the first power supply terminal U1 and the third control signal terminal EM2_N, and is configured to electrically connect the first node N1 and the third node N3 in response to the control of the third control signal provided by the third control signal terminal EM2_N, so that the voltage of the second node N2 charges the first node N1 through the driving unit 27, and maintains the voltage of the first node N1 at a preset voltage.
  • the compensation delay unit 23 is also connected to the first power supply terminal U1 , and is configured to store the data voltage Vdata provided by the data writing unit 25 , and provide the data voltage Vdata to the second node N2 , so as to continuously charge the first node N1 through the driving unit 27 .
  • the first light emitting control unit 21 is also connected to the first power supply terminal U1 and the fourth control signal terminal EM1, and is configured to write the power supply voltage VDD provided by the first power supply terminal U1 to the second node N2 in response to the control of the fourth control signal provided by the fourth control signal terminal EM1.
  • the second light emitting control unit 24 is also connected to the fourth control signal terminal EM1, and is configured to respond to The fourth control signal provided by the fourth control signal terminal EM1 controls the third node N3 and the fourth node N4 to be electrically connected, thereby making the driving unit 27 and the light emitting unit 29 electrically connected.
  • the driving unit 27 is configured to respond to the control of the preset voltage provided by the first node N1 and output a corresponding driving current I according to the power supply voltage VDD provided by the second node N2.
  • the driving current I is provided to the fourth node N4 through the second light-emitting control unit 24 to drive the light-emitting unit 29 to emit light.
  • the light emitting unit 29 is connected to the fourth node N4 , and the other end is connected to the second power supply terminal U2 .
  • the light emitting unit 29 is configured to emit light under the action of the driving current I provided by the driving unit 27 .
  • the charging compensation control unit 30 is also connected to the third control signal terminal EM2_N, and is configured to electrically connect the data writing unit 25 to the second node N2 and the compensation delay unit 23 to the second node N2 in response to the control of the third control signal provided by the third control signal terminal EM2_N.
  • FIG4 is a schematic diagram of a circuit structure of a pixel driving circuit in an embodiment of the present disclosure.
  • the first reset unit 26 includes: a first transistor T1, the control electrode of the first transistor T1 is connected to the first control signal terminal RESET, the first electrode is connected to the first reset signal terminal INIT1, The second electrode is connected to the first node N1.
  • the first end of the first capacitor C1 is connected to the first power supply terminal U1, and the second end is connected to the first node N1;
  • the control electrode of the second transistor T2 is connected to the third control signal terminal EM2_N, the first electrode is connected to the third node N3, and the second electrode is connected to the first node N1.
  • the driving unit 27 includes: a third transistor T3 ; the control electrode of the third transistor T3 is connected to the first node N1 , the first electrode is connected to the second node N2 , and the second electrode is connected to the third node N3 .
  • the data writing unit 25 includes: a fourth transistor T4 ; the control electrode of the fourth transistor T4 is connected to the second control signal terminal Gate1 , the first electrode is connected to the data signal terminal Data, and the second electrode is connected to the second node N2 .
  • the second light emitting control unit 24 includes: a sixth transistor T6 ; the control electrode of the sixth transistor T6 is connected to the fourth control signal terminal EM1 , the first electrode is connected to the third node N3 , and the second electrode is connected to the fourth node N4 .
  • the second reset unit 28 includes a seventh transistor T7 and an eighth transistor T8 .
  • control electrode of the seventh transistor T7 is connected to the fifth control signal terminal Gate2, the first electrode is connected to the second reset signal terminal INIT2, and the second electrode is connected to the fourth node N4;
  • control electrode of the eighth transistor T8 is connected to the fifth control signal terminal Gate2, the first electrode is connected to the third reset signal terminal INIT3, and the second electrode is connected to the second node N2.
  • the compensation delay unit 23 includes: a second capacitor C2 ; a first end of the second capacitor C2 is connected to the first power supply terminal U1 , and a second end of the second capacitor C2 is connected to the second node N2 .
  • FIG5 is a schematic diagram of a circuit structure of another pixel driving circuit in an embodiment of the present disclosure.
  • the pixel driving circuit shown in FIG5 is different from the pixel driving circuit shown in FIG4 in that the second The connection mode of the internal structure of the reset unit 28, specifically, as shown in Figures 2 and 5, the second reset unit 28 includes: a seventh transistor T7 and an eighth transistor T8, wherein the control electrode of the seventh transistor T7 is connected to the fifth control signal terminal Gate2, the first electrode is connected to the second reset signal terminal INIT2, and the second electrode is connected to the fourth node N4; the control electrode of the eighth transistor T8 is connected to the fifth control signal terminal Gate2, the first electrode is connected to the third reset signal terminal INIT3, and the second electrode is connected to the third node N3.
  • Figure 6 is a circuit structure diagram of another pixel driving circuit in an embodiment of the present disclosure.
  • the difference between the pixel driving circuit shown in Figure 6 and the pixel driving circuit shown in Figure 4 is that the pixel driving circuit also includes a charging compensation control unit, and as shown in Figures 3 and 6, the data writing unit 25 includes: a fourth transistor T4; the charging compensation control unit 30 includes: a ninth transistor T9.
  • control electrode of the fourth transistor T4 is connected to the second control signal terminal Gate1, the first electrode is connected to the data signal terminal Data, and the second electrode is connected to the first electrode of the ninth transistor T9; the control electrode of the ninth transistor T9 is connected to the third control signal terminal EM2_N, and the second electrode of the ninth transistor T9 is connected to the second node N2.
  • the compensation delay unit 23 includes: a second capacitor C2 ; a first end of the second capacitor C2 is connected to the first power supply end U1 , and a second end is connected to the first electrode of the ninth transistor T9 .
  • Figure 7 is a circuit structure diagram of another pixel driving circuit in an embodiment of the present disclosure.
  • the difference between the pixel driving circuit shown in Figure 7 and the pixel driving circuit shown in Figure 5 is that the pixel driving circuit also includes a charging compensation control unit, and as shown in Figures 3 and 7, the data writing unit 25 includes: a fourth transistor T4; the charging compensation control unit 30 includes: a ninth transistor T9.
  • control electrode of the fourth transistor T4 is connected to the second control signal terminal Gate1, the first electrode is connected to the data signal terminal Data, and the second electrode is connected to the first electrode of the ninth transistor T9; the control electrode of the ninth transistor T9 is connected to the third control signal terminal EM2_N, and the second electrode of the ninth transistor T9 is connected to the second node N2.
  • the compensation delay unit 23 includes: a second capacitor C2 ; a first end of the second capacitor C2 is connected to the first power supply end U1 , and a second end is connected to the first electrode of the ninth transistor T9 .
  • FIG8 is a working timing diagram of the pixel driving circuit shown in FIG4 or FIG5.
  • the pixel driving circuit shown in FIG4 is taken as an example below. In combination with FIG4 and FIG8, the working process of the pixel driving circuit provided in the embodiment of the present disclosure is described in detail.
  • the display period of each row of sub-pixels may include an initialization phase t1, a data writing and compensation phase t2, a light emitting phase t3, and a light emitting reset phase t4. That is, the working process of the pixel driving circuit of each row of sub-pixels includes: an initialization phase t1, a data writing and compensation phase t2, a light emitting phase t3, and a light emitting resetting phase t4.
  • each transistor (T1 ⁇ T7) is described as a P-type transistor. In this case, it can be understood that each transistor (T1 ⁇ T7) is turned on when the control pole is in a low level state, and is turned off when the control pole is in a high level state.
  • the first control signal terminal RESET provides a low level signal
  • the second control signal terminal Gate1 provides a high level signal
  • the third control signal terminal EM2_N provides a high level signal
  • the fourth control signal terminal EM1 provides a high level signal
  • the fifth control signal terminal Gate2 provides a high level signal.
  • the first transistor T1 Under the action of the low level signal provided by the first control signal terminal RESET, the first transistor T1 is turned on, and the first reset signal Vinit1 is written to the first node N1 through the turned-on first transistor T1, that is, the voltage of the first node N1 is reset, that is, the control electrode of the driving transistor DTFT (T3) is reset.
  • the transistors T2, T4, T5, T6, T7, and T8 are all turned off.
  • the first control signal terminal RESET provides a low level signal for a time greater than a scanning time of a row of pixels, so as to reset the control electrode of the driving transistor DTFT (T3) for a long time.
  • the first control signal terminal RESET provides a high level signal
  • the second control signal terminal Gate1 first provides a low level signal, and after a period of time, it changes to provide a high level signal
  • the third control signal terminal EM2_N first provides a high level signal, and then provides a low level signal after a certain period of time
  • the fourth control signal terminal EM1 provides a high level signal
  • the fifth control signal terminal Gate2 provides a high level signal.
  • the first transistor T1 Since the first control signal terminal RESET provides a high level signal, the first transistor T1 is turned off. At the same time, under the action of the low level signal provided by the second control signal terminal Gate1, the fourth transistor T4 is turned on, and the data voltage Vdata provided by the data signal terminal Data is written to the second node N2 through the turned-on fourth transistor T4 to charge the second node N2, and the data voltage Vdata is stored in the second capacitor C2; in addition, under the action of the low level signal provided by the third control signal terminal EM2_N, the second transistor T2 is turned on, and the driving transistor DTFT (T3) is in the turned-on state at this time.
  • the voltage of the second node N2 charges the first node N1 through the turned-on driving transistor DTFT (T3) and the turned-on second transistor T2 until the voltage at the first node N1 is charged to the preset voltage, the driving transistor DTFT (T3) is turned off, the charging is completed, and the first capacitor C1 stores the preset voltage.
  • the preset voltage is Vdata+Vth
  • Vdata is the data voltage
  • Vth is the threshold voltage of the driving transistor DTFT (T3).
  • the second transistor T2 can be continuously turned on to continuously charge the first node N1, thereby maintaining The threshold voltage Vth of the driving transistor T3 is continuously compensated to improve the threshold voltage compensation effect of the driving transistor, thereby improving the display quality in the refresh frequency working mode.
  • FIG9 is a schematic diagram showing a comparison of the threshold voltage compensation effect.
  • waveform 1 in FIG9 is a waveform diagram of a voltage signal at a control electrode (first node N1) of a driving transistor DTFT (T3) in a pixel driving circuit including a first capacitor C1 and a second capacitor C2
  • waveform 2 is a waveform diagram of a voltage signal at a control electrode (first node N1) of a driving transistor DTFT (T3) in a pixel driving circuit including only the first capacitor C1.
  • the driving transistor DTFT (T3) when the driving transistor DTFT (T3) outputs current to charge the first node N1, the sixth transistor T6 is turned off, thereby preventing the light emitting device OLED from emitting light by mistake, thereby improving the display effect.
  • the sixth transistor T6 may not be required.
  • the first control signal terminal RESET provides a high level signal
  • the second control signal terminal Gate1 provides a high level signal
  • the third control signal terminal EM2_N provides a high level signal
  • the fourth control signal terminal EM1 provides a low level signal
  • the fifth control signal terminal Gate2 provides a high level signal
  • the power line provides the power voltage VDD to the first power terminal U1.
  • the driving transistor DTFT (T3) outputs a driving current I according to the voltage at the first node N1 and the power supply voltage VDD provided by the power supply line, so as to drive the light emitting device D to emit light.
  • the constant K (1/2)* ⁇ n *C ox *(W/L) related to the process parameters and geometric dimensions of the driving transistor DTFT (T3), Vgs is the gate-source voltage of the driving transistor DTFT (T3), and Vth is the threshold voltage of the driving transistor DTFT (T3).
  • the driving current of the driving transistor DTFT (T3) is only related to the data voltage Vdata and the power supply voltage VDD, but has nothing to do with the threshold voltage Vth of the driving transistor DTFT (T3), thereby achieving compensation for the threshold voltage Vth, thereby preventing the driving current flowing through the light-emitting device D from being affected by the unevenness and drift of the threshold voltage, thereby effectively improving the uniformity of the driving current I flowing through the light-emitting device D.
  • the first control signal terminal RESET provides a high level signal
  • the second control signal terminal Gate1 provides a high level signal
  • the third control signal terminal EM2_N provides a high level signal
  • the fourth control signal terminal EM1 provides a low level signal
  • the fifth control signal terminal Gate2 provides a low level signal.
  • the seventh transistor T7 and the eighth transistor T8 are turned on, and the second reset signal Vinit2 provided by the second reset signal terminal INIT2 is written into the fourth node N4 through the turned-on seventh transistor T7 to reset the voltage of the fourth node N4 (i.e., the first pole of the light-emitting device D); at the same time, the third reset signal Vinit3 provided by the third reset signal terminal INIT3 is written into the second node N2 through the turned-on eighth transistor T8 to reset the voltage of the second node N2 (i.e., the first pole of the driving transistor T3).
  • the voltage of the second node N2 and the fourth node N4 is continuously reset by the seventh transistor T7 and the eighth transistor T8, so that in the low-frequency time period, the brightness difference during the low-frequency scanning period can be reduced.
  • the pixel driving circuit shown in Figure 6 also includes a ninth transistor T9, which controls the electrical conduction or disconnection between the fourth transistor T4 and the second node N2, and controls the electrical conduction or disconnection between the second capacitor C2 and the second node N2; wherein the working timing of the control electrode of the ninth transistor T9 is the same as the working timing of the control electrode of the second transistor T2, and is turned on in the data writing and compensation stage t2 to electrically connect the fourth transistor T4 and the second node N2, and to electrically connect the second capacitor C2 and the second node N2.
  • the fourth transistor T4 of the data writing unit can write the data voltage Vdata to the second capacitor C2 in advance.
  • the first node can be charged through the second capacitor C2, that is, the first capacitor C1 is charged.
  • the charging time at this time is independent of the pixel row scanning time. Therefore, the time for compensating the threshold voltage Vth of the driving transistor T3 can be appropriately extended as needed, thereby improving the threshold voltage compensation effect of the driving transistor, and then improving the display quality in the high refresh rate working mode.
  • the capacitance value of the second capacitor C2 is greater than the capacitance value of the first capacitor C1, which is more suitable for products with medium and large pixel resolution PPI.
  • this pixel driving circuit is also compatible with low-frequency characteristics and can meet high and low refresh frequency driving.
  • an embodiment of the present disclosure further provides a display device, which includes a display substrate provided by any of the aforementioned embodiments of the present disclosure.
  • a display substrate provided by any of the aforementioned embodiments of the present disclosure.
  • the display substrate please refer to the description of any of the aforementioned embodiments of the present disclosure, which will not be repeated here.
  • FIG10 is a flow chart of a driving method of a pixel driving circuit provided in an embodiment of the present disclosure.
  • the present disclosure further provides a driving method of a pixel driving circuit.
  • the pixel driving circuit includes the pixel driving circuit provided in any of the above embodiments.
  • the driving method of the pixel driving circuit includes:
  • Step S91 in the initialization phase, the first reset unit writes the first reset voltage provided by the first reset signal terminal to the first node in response to the control of the first control signal provided by the first control signal terminal.
  • Step S92 in the data writing and compensation stage, the data writing unit responds to the control of the second control signal provided by the second control signal terminal, writes the data voltage provided by the data signal terminal to the second node, and also provides the data voltage to the compensation delay unit;
  • the threshold compensation unit responds to the control of the third control signal provided by the third control signal terminal, electrically connects the first node and the third node, so that the voltage of the second node charges the first node through the driving unit, and maintains the voltage of the first node at a preset voltage;
  • the compensation delay unit stores the data voltage provided by the data writing unit, and provides the stored data voltage to the second node, so as to continuously charge the first node through the driving unit.
  • Step S94 in the light-emitting reset stage, the second reset unit responds to the control of the fifth control signal provided by the fifth control signal terminal, writes the second reset signal provided by the second reset signal terminal to the fourth node, and writes the third reset signal provided by the third reset signal terminal to the second node or the third node.

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Abstract

本公开提供一种及驱动方法、显示基板、显示装置，像素驱动电路包括：第一重置单元，被配置为响应于第一控制信号的控制将第一重置电压写入第一节点；数据写入单元，被配置为响应于第二控制信号的控制将数据电压写入第二节点；阈值补偿单元，被配置为响应于第三控制信号的控制将第一节点和第三节点电导通，以对第一节点进行充电；补偿延时单元，被配置为对数据电压进行存储并将数据电压提供至第二节点，以对第一节点持续进行充电；驱动单元，被配置为响应于第一节点的电压的控制输出相应的驱动电流，以驱动发光单元进行发光；第二重置单元，被配置为响应于第五控制信号的控制将第二重置信号写入至第四节点，并将第三重置信号写入第二节点或第三节点。

Description

像素驱动电路及驱动方法、显示基板、显示装置
相关申请的交叉引用
本公开要求于2023年6月6日提交的中国专利公开No.202310664576.7的优先权，所公开的内容以引用的方式合并于此。
技术领域
本公开实施例涉及显示技术领域，特别涉及一种像素驱动电路及驱动方法、显示基板、显示装置。
背景技术
一般而言，有机发光二极管(Organic Light Emitting Diode，OLED)显示器件能够发光是由驱动晶体管在饱和状态时产生的电流所驱动，但因为输入相同的灰阶电压时，不同的阈值电压会产生不同的驱动电流，造成电流的不一致性。
OLED显示器件在不同应用场景中，对显示器件的屏幕刷新频率有着不同的需求，例如，在游戏应用场景下，需要显示器件具有较高的屏幕刷新频率，以满足游戏功能需求，在商务应用场景下，需要显示器件具有较低的屏幕刷新频率，以满足较低的功耗以及较高的工作时间的需求。
发明内容
本公开实施例提供了一种像素驱动电路及驱动方法、显示基板、显示装置。
第一方面，本公开实施例提供了一种像素驱动电路，该像素驱动电路包括：第一发光控制单元、阈值补偿单元、补偿延时单元、第二发光控制单元、数据写入单元、第一重置单元、驱动单元、第二重置单元；
所述第一重置单元、所述阈值补偿单元和所述驱动单元连接于第一节点，所述第一发光控制单元、所述数据写入单元、所述补偿延时单元和所述驱动单元连接于第二节点，所述阈值补偿单元、所述第二发光控制单元和所述驱动单元与连接于第三节点，所述第二发光控制单元、所述第二重置单元和发光单元连接于第四节点，所述第二重置单元还与所述驱动单元连接；
所述第一重置单元还与第一控制信号端和第一重置信号端连接，其被配置 为响应于所述第一控制信号端所提供的第一控制信号的控制，将所述第一重置信号端所提供的第一重置电压写入至所述第一节点；
所述数据写入单元还与第二控制信号端和数据信号端连接，其被配置为响应于所述第二控制信号端所提供的第二控制信号的控制，将所述数据信号端所提供的数据电压写入至所述第二节点，并且还将所述数据电压提供至所述补偿延时单元；
所述阈值补偿单元还与第一电源端和第三控制信号端连接，其被配置为响应于所述第三控制信号端所提供的第三控制信号的控制，将所述第一节点和所述第三节点电导通，以使所述第二节点的电压通过所述驱动单元对所述第一节点进行充电，并将所述第一节点的电压保持为预设电压；
所述补偿延时单元还与第一电源端连接，其被配置为对所述数据写入单元提供的数据电压进行存储，并将存储的所述数据电压提供至所述第二节点，以通过所述驱动单元对所述第一节点持续进行充电；
所述第一发光控制单元还与所述第一电源端和第四控制信号端连接，其被配置为响应于所述第四控制信号端所提供的第四控制信号的控制，将所述第一电源端所提供的电源电压写入至所述第二节点；
所述第二发光控制单元，还与所述第四控制信号端连接，其被配置为响应于所述第四控制信号端所提供的第四控制信号的控制，将所述第三节点和所述第四节点电导通；
所述驱动单元被配置为响应于所述第一节点所提供的预设电压的控制，根据所述第二节点提供的电源电压输出相应的驱动电流，所述驱动电流通过所述第二发光控制单元提供至所述第四节点，以驱动所述发光单元进行发光；
所述第二重置单元还与第五控制信号端、第二重置信号端、第三重置信号端连接，其被配置为响应于所述第五控制信号端提供的第五控制信号的控制，将所述第二重置信号端提供的第二重置信号写入至所述第四节点，以及将所述第三重置信号端提供的第三重置信号写入所述第二节点或所述第三节点。
在一些实施例中，根据权利要求1所述的像素驱动电路，其特征在于，所述第一重置单元包括：第一晶体管；
所述第一晶体管的控制极连接所述第一控制信号端，第一极连接所述第一重置信号端，第二极连接至所述第一节点。
在一些实施例中，所述阈值补偿单元包括：第一电容和第二晶体管；
所述第一电容的第一端连接所述第一电源端，第二端连接至所述第一节点；
所述第二晶体管的控制极连接所述第三控制信号端，第一极连接至所述第三节点，第二极连接至所述第一节点。
在一些实施例中，所述驱动单元包括：第三晶体管；
所述第三晶体管的控制极连接至所述第一节点，第一极连接至所述第二节点，第二极连接至所述第三节点。
在一些实施例中，所述第一发光控制单元包括：第五晶体管；
所述第五晶体管的控制极连接所述第四控制信号端，第一极连接所述第一电源端，第二极连接至所述第二节点。
在一些实施例中，所述第二发光控制单元包括：第六晶体管；
所述第六晶体管的控制极连接所述第四控制信号端，第一极连接至所述第三节点，第二极连接至所述第四节点。
在一些实施例中，所述第二重置单元与所述驱动单元连接于所述第二节点，且所述第二重置单元包括：第七晶体管和第八晶体管；
所述第七晶体管的控制极连接所述第五控制信号端，第一极连接所述第二重置信号端，第二极连接至所述第四节点；
所述第八晶体管的控制极连接所述第五控制信号端，第一极连接所述第三重置信号端，第二极连接至所述第二节点。
在一些实施例中，所述第二重置单元与所述驱动单元连接于所述第三节点，且所述第二重置单元包括：第七晶体管和第八晶体管；
所述第七晶体管的控制极连接所述第五控制信号端，第一极连接所述第二重置信号端，第二极连接至所述第四节点；
所述第八晶体管的控制极连接所述第五控制信号端，第一极连接所述第三重置信号端，第二极连接至所述第三节点。
在一些实施例中，所述补偿延时单元包括：第二电容；
所述第二电容的第一端连接所述第一电源端，第二端连接至所述第二节点。
在一些实施例中，所述数据写入单元包括：第四晶体管；
所述第四晶体管的控制极连接至所述第二控制信号端，第一极连接所述数据信号端，第二极连接至所述第二节点。
在一些实施例中，所述像素驱动电路还包括：充电补偿控制单元；
所述补偿延时单元的一端连接所述第一电源端，另一端通过所述充电补偿控制单元连接于所述第二节点；
所述数据写入单元通过所述充电补偿控制单元连接于所述第二节点；
所述充电补偿控制单元还与所述第三控制信号端连接，其被配置为响应于所述第三控制信号端所提供的第三控制信号的控制，将所述数据写入单元与所述第二节点电导通，以及将所述补偿延时单元与所述第二节点电导通。
在一些实施例中，所述补偿延时单元包括：第二电容，其中所述第二电容的第一端连接所述第一电源端，第二端与所述充电补偿控制单元连接。
在一些实施例中，所述充电补偿控制单元，包括：第九晶体管，其中，
所述第九晶体管的控制极连接所述第三控制信号端，所述第九晶体管的第二极连接至所述第二节点，以及所述第九晶体管的第一极连接至所述第二电容的第二端。
在一些实施例中，所述数据写入单元包括：第四晶体管；
所述第四晶体管的控制极连接至所述第二控制信号端，第一极连接至所述数据信号端，第二极连接至所述第九晶体管的第一极。
第二方面，本公开实施例提供一种显示基板，该显示基板包括上述实施例提供的像素驱动电路。
第三方面，本公开实施例提供一种显示装置，该显示装置包括上述实施例提供的显示基板。
第四方面，本公开实施例提供一种像素驱动电路的驱动方法，该像素驱动电路包括上述实施例提供的像素驱动电路，该驱动方法包括：
在初始化阶段，第一重置单元响应于第一控制信号端所提供的第一控制信号的控制，将第一重置信号端所提供的第一重置电压写入至第一节点；
在数据写入及补偿阶段，数据写入单元响应于第二控制信号端所提供的第二控制信号的控制，将数据信号端所提供的数据电压写入至第二节点，并且还将数据电压提供至补偿延时单元；阈值补偿单元响应于第三控制信号端所提供的第三控制信号的控制，将第一节点和第三节点电导通，以使第二节点的电压通过驱动单元对第一节点进行充电，并将第一节点的电压保持为预设电压；以及，补偿延时单元对数据写入单元提供的数据电压进行存储，并将存储的数据 电压提供至第二节点，以通过驱动单元对第一节点持续进行充电；
在发光阶段，第一发光控制单元响应于第四控制信号端所提供的第四控制信号的控制，将第一电源端所提供的电源电压写入至第二节点；以及，第二发光控制单元响应于第四控制信号端所提供的第四控制信号的控制，将第三节点和第四节点电导通；以及，驱动单元响应于第一节点所提供的预设电压的控制，根据第二节点提供的电源电压输出相应的驱动电流，并将该驱动电流通过第二发光控制单元提供至第四节点，以驱动发光单元进行发光；
在发光重置阶段，第二重置单元响应于第五控制信号端提供的第五控制信号的控制，将第二重置信号端提供的第二重置信号写入至第四节点，以及将第三重置信号端提供的第三重置信号写入第二节点或第三节点。
附图说明
图1为本公开实施例中的一种显示基板的结构示意图；
图2为本公开实施例提供的一种像素驱动电路的组成框图；
图3为本公开实施例提供的另一种像素驱动电路的组成框图；
图4为本公开实施例中的一种像素驱动电路的电路结构示意图；
图5为本公开实施例中的另一种像素驱动电路的电路结构示意图；
图6为本公开实施例中的另一种像素驱动电路的电路结构示意图；
图7为本公开实施例中的另一种像素驱动电路的电路结构示意图；
图8为图4或图5所示像素驱动电路的一种工作时序图；
图9为阈值电压补偿效果对比示意图；
图10为本公开实施例提供的像素驱动电路的驱动方法的流程示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开实施例的技术方案，下面将结合本公开实施例的附图对本公开实施例所提供的像素驱动电路及驱动方法、显示基板、显示装置的技术方案进行清楚、完整地描述。
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“包含”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其他特征、整体、步骤、操作、元件、组件和/或其群组。
将理解的是，虽然本文可以使用术语第一、第二等来描述各种元件/结构，但这些元件/结构不应当受限于这些术语。这些术语仅用于区分一个元件/结构和另一元件/结构。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
需要说明的是，在本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他具有相同、类似特性的器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。
此外，按照晶体管特性，可将晶体管分为N型晶体管和P型晶体管；当晶体管为N型晶体管时，其导通电压为高电平电压，截止电压为低电平电压；当晶体管为P型晶体管时，其导通电压为低电平电压，截止电压为高电平电压。本发明中的“有效电平”是指能够控制相应晶体管导通的电压，“非有效电平”是指能够控制相应晶体管截止的电压；因此，当晶体管为N型晶体管时，有效电平是指高电平，非有效电平是指低电平；当晶体管为P型晶体管时，有效电平是指低电平，非有效电平是指高电平。
本公开实施例中是以P型晶体管进行说明的，当采用P型晶体管时，第一极为P型晶体管的漏极，第二极为P型晶体管的源极，N型则相反。
可以想到的是，本公开实施例还可以采用N型晶体管来实现下述实施例的技术方案，这是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开实施例的保护范围内。
在本公开实施例中，像素驱动电路中的全部晶体管同时为N型晶体管或同 时为P型晶体管的情况，仅为本公开实施例中的优选方案，此时该像素驱动电路中的全部晶体管可基于相同的工艺得以同时制备，有利于缩短制备周期；在一些实施例中，像素驱动电路中部分晶体管可以为N型晶体管，部分晶体管可以为P型晶体管。
图1为本公开实施例中的一种显示基板的结构示意图，如图1所示，在本公开实施例中，显示基板包括衬底基板(图中未示出)和位于衬底基板上的多个像素单元，每个像素单元包括多个子像素P。
其中，如图1所示，多个像素单元可以呈阵列排布，每个像素单元中的多个子像素P也可以呈阵列排布。需要说明的是，图1中仅示例性的示出了多个子像素P呈阵列排布的情形，本公开实施例包括但不限于此，本公开实施例中的多个子像素P还可以采用其他排布方式排布。
如图1所示，在本公开实施例中，显示基板还包括沿行方向延伸设置的多条栅线Gate和沿列方向延伸设置的多条数据线Data，其中，栅线Gate和数据线Data交叉设置且限定出子像素P。其中，栅线Gate用于向对应连接的子像素P提供栅极扫描信号，数据线Data用于向对应连接的子像素P提供所需的数据信号Vdata。
需要说明的是，图1仅示例性的示出了每行栅线Gate对应连接一行子像素P、每列数据线Data对应连接一列子像素P的情形，本公开实施例包括但不限于此，例如，本公开实施例中，还可以是每行子像素P对应设置两行栅线Gate，每行子像素P中，部分子像素P与对应的一行栅线gate连接，另一部分子像素P与对应的另一行栅线Gate连接。
如图1所示，在本公开实施例中，显示基板还包括沿列方向延伸设置的多条电源走线，其中，每列子像素P可以对应设置有一条电源走线，电源走线用于向对应连接的子像素P提供所需的电源电压VDD。需要说明的是，图1仅示例性的示出了每列子像素P可以对应设置有一条电源走线的情形，本公开实施例包括但不限于此，还可以是每多列(例如2列、3列等)子像素P对应设置一条电源走线。
在本公开实施例中，每个子像素P均包括像素驱动电路和发光器件，其中，像素驱动电路与对应的栅线Gate、对应的数据线Data、对应的电源走线以及对应的发光器件连接，像素驱动电路能够根据数据线Data所提供的数据信号Vdata和电源走线所提供的电源电压VDD向发光器件提供驱动电流，以驱动发光 器件发光；发光器件可以为电流驱动型发光器件，例如发光器件可以为OLED发光器件或者AMOLED(Active-Matrix Organic Light-Emitting Diode，有源矩阵有机发光二极管)发光器件等。
图2为本公开实施例中的一种像素驱动电路的组成框图，如图1和图2所示，在本公开实施例中，每个子像素P的像素驱动电路可以包括：第一发光控制单元21、阈值补偿单元22、补偿延时单元23、第二发光控制单元24、数据写入单元25、第一重置单元26、驱动单元27和第二重置单元28。
其中，第一重置单元26、阈值补偿单元22和驱动单元27连接于第一节点N1，第一发光控制单元21、数据写入单元25、补偿延时单元23和驱动单元27连接于第二节点N2，阈值补偿单元22、第二发光控制单元24和驱动单元27连接于第三节点N3，第二发光控制单元24、第二重置单元28和发光单元29连接于第四节点N4，第二重置单元28还与驱动单元27连接。
其中，第一重置单元26还与第一控制信号端RESET和第一重置信号端INIT1连接，其被配置为响应于第一控制信号端RESET所提供的第一控制信号的控制，将第一重置信号端INIT1所提供的第一重置电压Vinit1写入至第一节点N1，以对第一节点N1的电压进行重置复位。
数据写入单元25还与第二控制信号端Gate1和数据信号端Data连接，其被配置为响应于第二控制信号端Gate1所提供的第二控制信号的控制，将数据信号端Data所提供的数据电压Vdata写入至第二节点N2，同时还将数据电压Vdata提供至补偿延时单元23。
阈值补偿单元22还与第一电源端U1和第三控制信号端EM2_N连接，其被配置为响应于第三控制信号端EM2_N所提供的第三控制信号的控制，将第一节点N1和第三节点N3电导通，以使第二节点N2的电压通过驱动单元27对第一节点N1进行充电，并将第一节点N1的电压保持为预设电压。
补偿延时单元23还与第一电源端U1连接，其被配置为对数据写入单元25提供的数据电压Vdata进行存储，并将数据电压Vdata提供至第二节点N2，以通过驱动单元27对第一节点N1持续进行充电。
第一发光控制单元21还与第一电源端U1和第四控制信号端EM1连接，其被配置为响应于第四控制信号端EM1所提供的第四控制信号的控制，将第一电源端U1所提供的电源电压VDD写入至第二节点N2。
第二发光控制单元24，还与第四控制信号端EM1连接，其被配置为响应于 第四控制信号端EM1所提供的第四控制信号的控制，将第三节点N3和第四节点N4电导通，从而使得驱动单元27与发光单元29电导通。
驱动单元27其被配置为响应于第一节点N1所提供的预设电压的控制，根据第二节点N2提供的电源电压VDD输出相应的驱动电流I，驱动电流I通过第二发光控制单元24提供至第四节点N4，以驱动发光单元29进行发光。
发光单元29的一端连接至第四节点N4，另一端连接第二电源端U2，其被配置为在驱动单元27提供的驱动电流I的作用下进行发光。
第二重置单元28还与第五控制信号端Gate2、第二重置信号端INIT2、第三重置信号端INIT3连接，其被配置为响应于第五控制信号端Gate2提供的第五控制信号的控制，将第二重置信号端INIT2提供的第二重置信号写入至第四节点N4，以对第四节点N4的电压进行重置，以及将第三重置信号端INIT3提供的第三重置信号写入第二节点N2或第三节点N3，以对第二节点N2或第三节点N3的电压进行重置。
在本公开实施例中，第一电源U1所提供的电源电压VDD为直流高电平信号，第二电源端U1所提供的信号为直流低电平信号Vss；第一控制信号端RESET输出的信号为脉冲信号，第一控制信号为脉冲信号中处于有效电平状态的信号，例如，处于有效电平状态的信号为低电平信号；第二控制信号端Gate1与第一栅线(Gate1)连接，其输出的信号为脉冲信号，第二控制信号为脉冲信号中处于有效电平状态的信号，例如，处于有效电平状态的信号为低电平信号；数据信号端Data与数据线(Data)连接，其所提供的数据电压Vdata为脉冲信号；第一重置信号端INIT1所提供的第一重置信号Vinit1、第二重置信号端INIT2所提供的第二重置信号Vinit2、第三重置信号端INIT3所提供的第三重置信号Vinit3均为直流低电平信号；第三控制信号端EM2_N所提供的信号为脉冲信号，第三控制信号为脉冲信号中处于有效电平状态的信号，例如，处于有效电平状态的信号为低电平信号；第四控制信号端EM1所提供的信号为脉冲信号，第四控制信号为脉冲信号中处于有效电平状态的信号，例如，处于有效电平状态的信号为低电平信号；第五控制信号端Gate2与第二栅线(Gate)连接，其输出的信号为脉冲信号，第五控制信号为脉冲信号中处于有效电平状态的信号，例如，处于有效电平状态的信号为低电平信号。
根据本公开实施例提供的像素驱动电路的技术方案，在一方面，在数据写入单元将数据电压写入第二节点以通过驱动单元和阈值补偿单元对第一节点进 行充电时，通过补偿延时单元存储数据电压，补偿延时单元存储的数据电压可以通过驱动单元和阈值补偿单元对第一节点持续进行充电，以对驱动单元的阈值电压进行持续补偿，从而改善驱动单元的阈值电压的补偿效果，进而有利于改善高刷新频率工作模式下的显示画质；在另一方面，在发光单元发光之后，通过第二重置单元对第二节点或第三节点电压进行复位重置，以及对第四节点电压进行复位重置，从而可以有效改善因驱动单元的迟滞效应造成低刷新频率工作模式下以及高低刷新频率切换时存在显示亮度差异以及显示画面闪烁的问题，
在一些实施例中，如图2所示，补偿延时单元23的一端连接第一电源端U1，另一端直接连接至第二节点N2；第二重置单元28与驱动单元27连接于第二节点N2，此时，第二重置单元28响应于第五控制信号端提供的第五控制信号的控制，将第三重置信号端INIT3提供的第三重置信号写入第二节点N2。
在一些实施例中，如图2所示，补偿延时单元23的一端连接第一电源端U1，另一端直接连接至第二节点N2；第二重置单元28与驱动单元27相连接，例如，第二重置单元28与驱动单元27相连接于第三节点N3，此时，第二重置单元28响应于第五控制信号端提供的第五控制信号的控制，将第三重置信号端INIT3提供的第三重置信号写入第三节点N3。
图3为本公开实施例提供的另一种像素驱动电路的组成框图，在一些实施例中，如图3所示，像素驱动电路还包括：充电补偿控制单元30。
其中，补偿延时单元23的一端连接第一电源端U1，另一端通过充电补偿控制单元30连接第二节点N2；数据写入单元25通过充电补偿控制单元30连接第二节点N2；第二重置单元28与驱动单元27相连接，更具体的，第二重置单元28与驱动单元27可以连接于第二节点N2或者第三节点N3，例如，图3仅示例性示出了第二重置单元28与驱动单元27连接于第二节点N2的情形，在本公开实施例中，第二重置单元28与驱动单元27还可以连接于第三节点N3。
充电补偿控制单元30还与第三控制信号端EM2_N连接，其被配置为响应于第三控制信号端EM2_N所提供的第三控制信号的控制，将数据写入单元25与第二节点N2电导通，以及将补偿延时单元23与第二节点N2电导通。
图4为本公开实施例中的一种像素驱动电路的电路结构示意图，在一些实施例中，如图2和图4所示，第一重置单元26包括：第一晶体管T1，第一晶体管T1的控制极连接第一控制信号端RESET，第一极连接第一重置信号端INIT1， 第二极连接至第一节点N1。
在一些实施例中，如图2和图4所示，阈值补偿单元22包括：第一电容C1和第二晶体管T2。
其中，第一电容C1的第一端连接第一电源端U1，第二端连接至第一节点N1；第二晶体管T2的控制极连接第三控制信号端EM2_N，第一极连接至第三节点N3，第二极连接至第一节点N1。
在一些实施例中，如图2和图4所示，驱动单元27包括：第三晶体管T3；第三晶体管T3的控制极连接至第一节点N1，第一极连接至第二节点N2，第二极连接至第三节点N3。
在一些实施例中，如图2和图4所示，数据写入单元25包括：第四晶体管T4；第四晶体管T4的控制极连接至第二控制信号端Gate1，第一极连接数据信号端Data，第二极连接至第二节点N2。
在一些实施例中，如图2和图4所示，第一发光控制单元21包括：第五晶体管T5；第五晶体管T5的控制极连接第四控制信号端EM1，第一极连接第一电源端U1，第二极连接至第二节点N2。
在一些实施例中，如图2和图4所示，第二发光控制单元24包括：第六晶体管T6；第六晶体管T6的控制极连接第四控制信号端EM1，第一极连接至第三节点N3，第二极连接至第四节点N4。
在一些实施例中，如图2和图4所示，第二重置单元28包括：第七晶体管T7和第八晶体管T8。
其中，第七晶体管T7的控制极连接第五控制信号端Gate2，第一极连接第二重置信号端INIT2，第二极连接至第四节点N4；第八晶体管T8的控制极连接第五控制信号端Gate2，第一极连接第三重置信号端INIT3，第二极连接至第二节点N2。
在一些实施例中，如图2和图4所示，补偿延时单元23包括：第二电容C2；第二电容C2的第一端连接第一电源端U1，第二端连接至第二节点N2。
在一些实施例中，如图2和图4所示，发光单元29包括发光器件D，发光器件D的第一极连接至第四节点N4，第二极连接第二电源端U2。在一些实施例中，发光器件D为OLED发光器件，其第一极为阳极，其第二极为阴极。
图5为本公开实施例中的另一种像素驱动电路的电路结构示意图，在一些实施例中，图5所示像素驱动电路与图4所示像素驱动电路的区别在于第二重 置单元28的内部结构的连接方式，具体的，如图2和图5所示，第二重置单元28包括：第七晶体管T7和第八晶体管T8，其中，第七晶体管T7的控制极连接第五控制信号端Gate2，第一极连接第二重置信号端INIT2，第二极连接至第四节点N4；第八晶体管T8的控制极连接第五控制信号端Gate2，第一极连接第三重置信号端INIT3，第二极连接至第三节点N3。
图6为本公开实施例中的另一种像素驱动电路的电路结构示意图，在一些实施例中，图6所示像素驱动电路与图4所示像素驱动电路的区别在于：像素驱动电路还包括充电补偿控制单元，并且如图3和图6所示，数据写入单元25包括：第四晶体管T4；充电补偿控制单元30包括：第九晶体管T9。
其中，第四晶体管T4的控制极连接至第二控制信号端Gate1，第一极连接数据信号端Data，第二极与第九晶体管T9的第一极连接；第九晶体管T9的控制极连接第三控制信号端EM2_N，第九晶体管T9的第二极连接至第二节点N2。
在一些实施例中，如图3和图6所示，补偿延时单元23包括：第二电容C2；第二电容C2的第一端连接第一电源端U1，第二端与第九晶体管T9的第一极连接。
图7为本公开实施例中的另一种像素驱动电路的电路结构示意图，在一些实施例中，图7所示像素驱动电路与图5所示像素驱动电路的区别在于：像素驱动电路还包括充电补偿控制单元，并且如图3和图7所示，数据写入单元25包括：第四晶体管T4；充电补偿控制单元30包括：第九晶体管T9。
其中，第四晶体管T4的控制极连接至第二控制信号端Gate1，第一极连接数据信号端Data，第二极与第九晶体管T9的第一极连接；第九晶体管T9的控制极连接第三控制信号端EM2_N，第九晶体管T9的第二极连接至第二节点N2。
在一些实施例中，如图3和图7所示，补偿延时单元23包括：第二电容C2；第二电容C2的第一端连接第一电源端U1，第二端与第九晶体管T9的第一极连接。
图8为图4或图5所示像素驱动电路的一种工作时序图，为便于本领域技术人员更好的理解本发明的技术方案，下面以图4所示像素驱动电路为例，将结合图4和图8，对本公开实施例所提供的像素驱动电路的工作过程进行详细描述。
如图4和图8所示，在本公开实施例中，每行子像素的显示时段可以包括初始化阶段t1、数据写入及补偿阶段t2、发光阶段t3以及发光重置阶段t4， 即每行子像素的像素驱动电路的工作过程包括：初始化阶段t1、数据写入及补偿阶段t2、发光阶段t3、发光重置阶段t4。
在下述描述中，均以各晶体管(T1～T7)为P型晶体管为例进行描述，此种情形下，可以理解的是，各晶体管(T1～T7)在控制极为低电平状态下导通，而在控制极为高电平状态下截止。
在初始化阶段t1，第一控制信号端RESET提供低电平信号，第二控制信号端Gate1提供高电平信号，第三控制信号端EM2_N提供高电平信号，第四控制信号端EM1提供高电平信号，第五控制信号端Gate2提供高电平信号。
在第一控制信号端RESET提供的低电平信号的作用下，第一晶体管T1导通，第一重置信号Vinit1通过导通的第一晶体管T1写入至第一节点N1，即对第一节点N1电压进行重置，也即实现对驱动晶体管DTFT(T3)的控制极的重置处理。与此同时，由于其他控制信号端均提供的高电平信号，因此晶体管T2、T4、T5、T6、T7、T8均截止。
在一些实施例中，第一控制信号端RESET提供低电平信号的时间大于一行像素的扫描时间，以对驱动晶体管DTFT(T3)的控制极进行长时间重置。
在数据写入及补偿阶段t2，第一控制信号端RESET提供高电平信号，第二控制信号端Gate1首先提供低电平信号，经过一段时间后变为提供高电平信号，第三控制信号端EM2_N首先高电平信号，然后经过一定时间后提供低电平信号，第四控制信号端EM1提供高电平信号，第五控制信号端Gate2提供高电平信号。
由于第一控制信号端RESET提供高电平信号，因此第一晶体管T1截止。与此同时，在第二控制信号端Gate1提供的低电平信号的作用下，第四晶体管T4导通，数据信号端Data提供的数据电压Vdata通过导通的第四晶体管T4写入至第二节点N2，以对第二节点N2进行充电，且数据电压Vdata存入第二电容C2；此外，在第三控制信号端EM2_N提供的低电平信号的作用下，第二晶体管T2导通，此时驱动晶体管DTFT(T3)处于导通状态，第二节点N2的电压通过导通的驱动晶体管DTFT(T3)和导通的第二晶体管T2对第一节点N1进行充电，直至第一节点N1处的电压充电至预设电压，驱动晶体管DTFT(T3)截止，充电结束，第一电容C1存储该预设电压。其中，预设电压为Vdata+Vth，Vdata为数据电压，Vth为驱动晶体管DTFT(T3)的阈值电压。
通过第二电容C2的设置，在数据写入及补偿阶段t2，即使第四晶体管T4关闭，第二晶体管T2可以持续开启，以持续对第一节点N1进行充电，从而持 续不断对驱动晶体管T3的阈值电压Vth进行补偿，改善驱动晶体管的阈值电压补偿效果，从而提高刷新频率工作模式下的显示画质。
图9为阈值电压补偿效果对比示意图，如图9所示，图9中波形1为包含第一电容C1和第二电容C2的像素驱动电路中驱动晶体管DTFT(T3)的控制极(第一节点N1)处的电压信号的波形图，波形2为仅包含有第一电容C1的像素驱动电路中驱动晶体管DTFT(T3)的控制极(第一节点N1)处的电压信号的波形图，对比波形1和波形2，可以很明显看到像素驱动电路在增设第二电容C2之后，在数据写入及补偿阶段t2，第一节点N1处的电位增高，阈值电压Vth补偿更充分。
需要说明的是，在驱动晶体管DTFT(T3)输出电流对第一节点N1进行充电过程中，由于第六晶体管T6截止，因此可避免发光器件OLED误发光，以提升显示效果。当然，在一些实施例中，也可以无需设置第六晶体管T6。
在发光阶段t3，第一控制信号端RESET提供高电平信号，第二控制信号端Gate1提供高电平信号，第三控制信号端EM2_N提供高电平信号，第四控制信号端EM1提供低电平信号，第五控制信号端Gate2提供高电平信号，电源走线提供电源电压VDD给第一电源端U1。
在第四控制信号端EM1提供的低电平信号作用下，第五晶体管T5和第六晶体管T6导通，驱动晶体管DTFT(T3)根据第一节点N1处的电压和电源走线提供的电源电压VDD输出驱动电流I，以驱动发光器件D发光。其中，根据驱动晶体管DTFT(T3)的饱和驱动电流公式可得：I＝K*(Vgs-Vth)2＝K*(Vdata+Vth-VDD-Vth)2＝K*(VDD-Vdata)2。
其中，与驱动晶体管DTFT(T3)的工艺参数和几何尺寸有关的常数K＝(1/2)*μn*Cox*(W/L)，Vgs为驱动晶体管DTFT(T3)的栅源电压，Vth为驱动晶体管DTFT(T3)的阈值电压。通过上式可知，驱动晶体管DTFT(T3)的驱动电流仅与数据电压Vdata和电源电压VDD相关，而与驱动晶体管DTFT(T3)的阈值电压Vth无关，实现了对阈值电压Vth的补偿，从而可避免流过发光器件D的驱动电流受到阈值电压不均匀和漂移的影响，进而有效的提高了流过发光器件D的驱动电流I的均匀性。
在发光重置阶段t4，第一控制信号端RESET提供高电平信号，第二控制信号端Gate1提供高电平信号，第三控制信号端EM2_N提供高电平信号，第四控制信号端EM1提供低电平信号，第五控制信号端Gate2提供低电平信号。
在第五控制信号端Gate2提供的低电平信号的作用下，第七晶体管T7和第八晶体管T8导通，第二重置信号端INIT2提供的第二重置信号Vinit2通过导通的第七晶体管T7写入第四节点N4，以对第四节点N4(即发光器件D的第一极)的电压进行重置；同时，第三重置信号端INIT3提供的第三重置信号Vinit3通过导通的第八晶体管T8写入第二节点N2，以对第二节点N2(即驱动晶体管T3的第一极)的电压进行重置。本实施例中，通过第七晶体管T7和第八晶体管T8持续对第二节点N2和第四节点N4进行电压重置，从而在低频时间段中，能够降低低频扫描期间的亮度差异。
需要说明的是，图6所示像素驱动电路与图4所示像素驱动电路的区别在于图6所示像素驱动电路还包括第九晶体管T9，通过第九晶体管T9控制第四晶体管T4与第二节点N2之间的电导通或断开，以及控制第二电容C2与第二节点N2之间的电导通或断开；其中，第九晶体管T9的控制极的工作时序与第二晶体管T2的控制极的工作时序相同，且在数据写入及补偿阶段t2导通，以将第四晶体管T4与第二节点N2之间电导通，以及将第二电容C2与第二节点N2之间电导通。
同时，通过第九晶体管T9的设置，数据写入单元的第四晶体管T4可以提前将数据电压Vdata写入至第二电容C2，在第二晶体管T2和第九晶体管T9开启后，可以通过第二电容C2对第一节点进行充电，即对第一电容C1进行充电，此时的充电时间与像素行扫描时间无关，因此可以根据需要适当延长对驱动晶体管T3的阈值电压Vth补偿的时间，从而改善驱动晶体管的阈值电压补偿效果，进而提升高刷新频率工作模式下的显示画质。
图6所示像素驱动电路和图7所示像素驱动电路中，第二电容C2的电容值大于第一电容C1的电容值，较适用于中大尺寸像素分辨率PPI的产品，同时此像素驱动电路同样兼容低频特性，能够满足高低刷新频率驱动。
在本公开实施例中，每个子像素P的发光器件D均包括阳极(图中未示出)、有机发光层(图中未示出)和阴极(图中未示出)。其中，阳极即为前述发光器件D的第一极，其与第七晶体管T7的第二极、第六晶体管T6的第二极连接；阴极即为前述发光器件D的第二极，其与用于提供低电平电压Vss的第二电源端U2连接。
本公开实施例还提供一种显示基板，该显示基板包括上述任一实施例提供的像素驱动电路，关于该像素驱动电路的具体描述可参见上述任一实施例中对 像素驱动电路的相关描述，此处不再赘述。
在本公开实施例中，显示基板可以为OLED显示基板。
此外，本公开实施例还提供一种显示装置，该显示装置包括前述任一本公开实施例所提供的显示基板，关于该显示基板的具体描述可参见前述任一本公开实施例的描述，此处不再赘述。
图10为本公开实施例提供的像素驱动电路的驱动方法的流程示意图，本公开实施例还提供一种像素驱动电路的驱动方法，在本公开实施例中，该像素驱动电路包括上述任一实施例提供的像素驱动电路，如图10所示，该像素驱动电路的驱动方法包括：
步骤S91、在初始化阶段，第一重置单元响应于第一控制信号端所提供的第一控制信号的控制，将第一重置信号端所提供的第一重置电压写入至第一节点。
步骤S92、在数据写入及补偿阶段，数据写入单元响应于第二控制信号端所提供的第二控制信号的控制，将数据信号端所提供的数据电压写入至第二节点，并且还将数据电压提供至补偿延时单元；阈值补偿单元响应于第三控制信号端所提供的第三控制信号的控制，将第一节点和第三节点电导通，以使第二节点的电压通过驱动单元对第一节点进行充电，并将第一节点的电压保持为预设电压；以及，补偿延时单元对数据写入单元提供的数据电压进行存储，并将所存储的数据电压提供至第二节点，以通过驱动单元对第一节点持续进行充电。
步骤S93、在发光阶段，第一发光控制单元响应于第四控制信号端所提供的第四控制信号的控制，将第一电源端所提供的电源电压写入至第二节点；以及，第二发光控制单元响应于第四控制信号端所提供的第四控制信号的控制，将第三节点和第四节点电导通；以及，驱动单元响应于第一节点所提供的预设电压的控制，根据第二节点提供的电源电压输出相应的驱动电流，并将该驱动电流通过第二发光控制单元提供至第四节点，以驱动发光单元进行发光。
步骤S94、在发光重置阶段，第二重置单元响应于第五控制信号端提供的第五控制信号的控制，将第二重置信号端提供的第二重置信号写入至第四节点，以及将第三重置信号端提供的第三重置信号写入第二节点或第三节点。
对于上述各步骤的具体描述和像素驱动电路的具体描述可参见前述任一实施例中相应内容，此处不再详细描述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (17)

  1. 一种像素驱动电路，其特征在于，包括：第一发光控制单元、阈值补偿单元、补偿延时单元、第二发光控制单元、数据写入单元、第一重置单元、驱动单元、第二重置单元；
    所述第一重置单元、所述阈值补偿单元和所述驱动单元连接于第一节点，所述第一发光控制单元、所述数据写入单元、所述补偿延时单元和所述驱动单元连接于第二节点，所述阈值补偿单元、所述第二发光控制单元和所述驱动单元与连接于第三节点，所述第二发光控制单元、所述第二重置单元和发光单元连接于第四节点，所述第二重置单元还与所述驱动单元连接；
    所述第一重置单元还与第一控制信号端和第一重置信号端连接，其被配置为响应于所述第一控制信号端所提供的第一控制信号的控制，将所述第一重置信号端所提供的第一重置电压写入至所述第一节点；
    所述数据写入单元还与第二控制信号端和数据信号端连接，其被配置为响应于所述第二控制信号端所提供的第二控制信号的控制，将所述数据信号端所提供的数据电压写入至所述第二节点，并且还将所述数据电压提供至所述补偿延时单元；
    所述阈值补偿单元还与第一电源端和第三控制信号端连接，其被配置为响应于所述第三控制信号端所提供的第三控制信号的控制，将所述第一节点和所述第三节点电导通，以使所述第二节点的电压通过所述驱动单元对所述第一节点进行充电，并将所述第一节点的电压保持为预设电压；
    所述补偿延时单元还与所述第一电源端连接，其被配置为对所述数据写入单元提供的数据电压进行存储，并将存储的所述数据电压提供至所述第二节点，以通过所述驱动单元对所述第一节点持续进行充电；
    所述第一发光控制单元还与所述第一电源端和第四控制信号端连接，其被配置为响应于所述第四控制信号端所提供的第四控制信号的控制，将所述第一电源端所提供的电源电压写入至所述第二节点；
    所述第二发光控制单元还与所述第四控制信号端连接，其被配置为响应于所述第四控制信号端所提供的第四控制信号的控制，将所述第三节点和所述第四节点电导通；
    所述驱动单元被配置为响应于所述第一节点所提供的预设电压的控制，根据所述第二节点提供的电源电压输出相应的驱动电流，所述驱动电流通过所述 第二发光控制单元提供至所述第四节点，以驱动所述发光单元进行发光；
    所述第二重置单元还与第五控制信号端、第二重置信号端和第三重置信号端连接，其被配置为响应于所述第五控制信号端提供的第五控制信号的控制，将所述第二重置信号端提供的第二重置信号写入至所述第四节点，以及将所述第三重置信号端提供的第三重置信号写入所述第二节点或所述第三节点。
  2. 根据权利要求1所述的像素驱动电路，其特征在于，所述第一重置单元包括：第一晶体管；
    所述第一晶体管的控制极连接所述第一控制信号端，第一极连接所述第一重置信号端，第二极连接至所述第一节点。
  3. 根据权利要求1至2中任一项所述的像素驱动电路，其特征在于，所述阈值补偿单元包括：第一电容和第二晶体管；
    所述第一电容的第一端连接所述第一电源端，第二端连接至所述第一节点；
    所述第二晶体管的控制极连接所述第三控制信号端，第一极连接至所述第三节点，第二极连接至所述第一节点。
  4. 根据权利要求1至3中任一项所述的像素驱动电路，其特征在于，所述驱动单元包括：第三晶体管；
    所述第三晶体管的控制极连接至所述第一节点，第一极连接至所述第二节点，第二极连接至所述第三节点。
  5. 根据权利要求1至4中任一项所述的像素驱动电路，其特征在于，所述第一发光控制单元包括：第五晶体管；
    所述第五晶体管的控制极连接所述第四控制信号端，第一极连接所述第一电源端，第二极连接至所述第二节点。
  6. 根据权利要求1至5中任一项所述的像素驱动电路，其特征在于，所述第二发光控制单元包括：第六晶体管；
    所述第六晶体管的控制极连接所述第四控制信号端，第一极连接至所述第 三节点，第二极连接至所述第四节点。
  7. 根据权利要求1至6中任一项所述的像素驱动电路，其特征在于，所述第二重置单元与所述驱动单元连接于所述第二节点，且所述第二重置单元包括：第七晶体管和第八晶体管；
    所述第七晶体管的控制极连接所述第五控制信号端，第一极连接所述第二重置信号端，第二极连接至所述第四节点；
    所述第八晶体管的控制极连接所述第五控制信号端，第一极连接所述第三重置信号端，第二极连接至所述第二节点。
  8. 根据权利要求1至6中任一项所述的像素驱动电路，其特征在于，所述第二重置单元与所述驱动单元连接于所述第三节点，且所述第二重置单元包括：第七晶体管和第八晶体管；
    所述第七晶体管的控制极连接所述第五控制信号端，第一极连接所述第二重置信号端，第二极连接至所述第四节点；
    所述第八晶体管的控制极连接所述第五控制信号端，第一极连接所述第三重置信号端，第二极连接至所述第三节点。
  9. 根据权利要求1至8中任一项所述的像素驱动电路，其特征在于，所述补偿延时单元包括：第二电容；
    所述第二电容的第一端连接所述第一电源端，第二端连接至所述第二节点。
  10. 根据权利要求1至9中任一项所述的像素驱动电路，其特征在于，所述数据写入单元包括：第四晶体管；
    所述第四晶体管的控制极连接至所述第二控制信号端，第一极连接所述数据信号端，第二极连接至所述第二节点。
  11. 根据权利要求1至8中任一项所述的像素驱动电路，其特征在于，所述像素驱动电路还包括：充电补偿控制单元；
    所述补偿延时单元的一端连接所述第一电源端，另一端通过所述充电补偿 控制单元连接于所述第二节点；
    所述数据写入单元通过所述充电补偿控制单元连接于所述第二节点；
    所述充电补偿控制单元还与所述第三控制信号端连接，其被配置为响应于所述第三控制信号端所提供的第三控制信号的控制，将所述数据写入单元与所述第二节点电导通，以及将所述补偿延时单元与所述第二节点电导通。
  12. 根据权利要求11所述的像素驱动电路，其特征在于，所述补偿延时单元包括：第二电容，其中所述第二电容的第一端连接所述第一电源端，第二端与所述充电补偿控制单元连接。
  13. 根据权利要求12所述的像素驱动电路，其特征在于，所述充电补偿控制单元，包括：第九晶体管，其中，
    所述第九晶体管的控制极连接所述第三控制信号端，所述第九晶体管的第二极连接至所述第二节点，以及所述第九晶体管的第一极连接至所述第二电容的第二端。
  14. 根据权利要求13所述的像素驱动电路，其特征在于，所述数据写入单元包括：第四晶体管；
    所述第四晶体管的控制极连接至所述第二控制信号端，第一极连接至所述数据信号端，第二极连接至所述第九晶体管的第一极。
  15. 一种显示基板，其特征在于，包括如权利要求1-14中任一项所述的像素驱动电路。
  16. 一种显示装置，其特征在于，包括如权利要求15所述的显示基板。
  17. 一种像素驱动电路的驱动方法，其特征在于，所述像素驱动电路包括如权利要求1-14中任一项所述的像素驱动电路，所述驱动方法包括：
    在初始化阶段，第一重置单元响应于所述第一控制信号端所提供的第一控制信号的控制，将所述第一重置信号端所提供的第一重置电压写入至所述第一节点；
    在数据写入及补偿阶段，所述数据写入单元响应于所述第二控制信号端所提供的第二控制信号的控制，将所述数据信号端所提供的数据电压写入至所述第二节点，并且还将数据电压提供至所述补偿延时单元；所述阈值补偿单元响应于所述第三控制信号端所提供的第三控制信号的控制，将所述第一节点和所述第三节点电导通，以使所述第二节点的电压通过所述驱动单元对所述第一节点进行充电，并将所述第一节点的电压保持为预设电压；以及，所述补偿延时单元对所述数据写入单元提供的数据电压进行存储，并将所存储的数据电压提供至所述第二节点，以通过所述驱动单元对所述第一节点持续进行充电；
    在发光阶段，所述第一发光控制单元响应于所述第四控制信号端所提供的第四控制信号的控制，将所述第一电源端所提供的电源电压写入至第二节点；以及，所述第二发光控制单元响应于第四控制信号端所提供的第四控制信号的控制，将所述第三节点和第四节点电导通；以及，所述驱动单元响应于所述第一节点所提供的预设电压的控制，根据所述第二节点提供的电源电压输出相应的驱动电流，并将所述驱动电流通过第二发光控制单元提供至所述第四节点，以驱动所述发光单元进行发光；以及
    在发光重置阶段，所述第二重置单元响应于所述第五控制信号端提供的第五控制信号的控制，将所述第二重置信号端提供的第二重置信号写入至所述第四节点，以及将所述第三重置信号端提供的第三重置信号写入第二节点或第三节点。
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