WO2024189685A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2024189685A1
WO2024189685A1 PCT/JP2023/009363 JP2023009363W WO2024189685A1 WO 2024189685 A1 WO2024189685 A1 WO 2024189685A1 JP 2023009363 W JP2023009363 W JP 2023009363W WO 2024189685 A1 WO2024189685 A1 WO 2024189685A1
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Prior art keywords
barrier metal
metal
semiconductor substrate
semiconductor device
barrier
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PCT/JP2023/009363
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English (en)
French (fr)
Japanese (ja)
Inventor
弘一郎 西澤
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三菱電機株式会社
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Priority to JP2025506241A priority Critical patent/JPWO2024189685A1/ja
Priority to PCT/JP2023/009363 priority patent/WO2024189685A1/ja
Priority to TW113100725A priority patent/TW202437394A/zh
Publication of WO2024189685A1 publication Critical patent/WO2024189685A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

Definitions

  • This disclosure relates to a semiconductor device and a method for manufacturing the same.
  • III-V semiconductor devices such as GaAs are used in communication devices and the like.
  • Copper which has high electrical conductivity, is used as an electrode material for semiconductor devices.
  • copper diffuses into the semiconductor substrate and deteriorates the characteristics of the semiconductor device. Therefore, a barrier metal is formed between the semiconductor substrate and the copper film.
  • a heat treatment is performed to diffuse the metal atoms of the barrier metal into the semiconductor substrate, forming a diffusion layer between the barrier metal and the semiconductor substrate. It is known that the barrier metal is formed by nickel electroless plating (see, for example, Patent Document 1).
  • This disclosure has been made to solve the problems described above, and its purpose is to obtain a semiconductor device and a method for manufacturing the same that can provide high barrier properties against copper diffusion.
  • the semiconductor device comprises a semiconductor substrate, a barrier metal formed on the semiconductor substrate and made of a metal material co-deposited with phosphorus or boron, and a copper film formed on the barrier metal, the barrier metal having a first barrier metal in contact with the semiconductor substrate and a second barrier metal formed on the first barrier metal, the first barrier metal and the second barrier metal being made of the same material, the first barrier metal being polycrystalline, and the second barrier metal being of an amorphous structure.
  • the second barrier metal has an amorphous structure, so that a high barrier property against the diffusion of copper atoms in the copper film can be obtained.
  • FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment
  • 1A to 1C are cross-sectional views showing a manufacturing method of a semiconductor device according to a first embodiment.
  • 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a comparative example.
  • 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a comparative example.
  • FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment.
  • 11A to 11C are cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment.
  • 11A to 11C are cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment.
  • 11A to 11C are cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment.
  • Embodiment 1. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment.
  • a semiconductor substrate 1 is made of a III-V group semiconductor such as GaAs.
  • a barrier metal 2 made of a metallic material co-deposited with phosphorus (P) or boron (B) is formed on the semiconductor substrate 1.
  • a copper film 3 is formed on the barrier metal 2.
  • the barrier metal 2 is, for example, a nickel alloy (Ni-P) co-deposited with phosphorus.
  • Ni-P indicates an alloy of nickel and phosphorus, and hyphens will be used hereafter to indicate the alloy.
  • the barrier metal 2 may be any alloy in which phosphorus or boron is co-deposited with at least one of nickel (Ni), cobalt (Co), and tungsten (W).
  • the barrier metal 2 may be any of Ni-P, Ni-W-P, Ni-Co-P, Co-P, Co-W-P, Ni-B, Ni-W-B, Ni-Co-B, Co-B, and Co-W-B.
  • These alloys can be formed by electroless plating, and have high barrier properties against the diffusion of copper (Cu) from the copper film 3.
  • the crystallinity of the barrier metal 2 can also be controlled by the liquid composition or processing conditions.
  • the barrier metal 2 has a first barrier metal 2a in contact with the semiconductor substrate 1 and a second barrier metal 2b formed on the first barrier metal 2a.
  • a diffusion prevention layer 4 is formed between the first barrier metal 2a and the second barrier metal 2b.
  • the diffusion prevention layer 4 has at least one of gold (Au), silver (Ag), copper (Cu), palladium (Pd), platinum (Pt), titanium (Ti), and aluminum (Al).
  • the diffusion prevention layer 4 made of these materials can prevent the diffusion of nickel, cobalt, or tungsten, which is the metallic material of the second barrier metal 2b, and has high adhesion to nickel alloys, cobalt alloys, and tungsten alloys.
  • the internal stress and linear expansion of the metal film are determined by the material. Therefore, the first barrier metal 2a and the second barrier metal 2b are formed from the same material. This reduces the stress that occurs at the interface due to the difference in internal stress or linear expansion between the two, and makes it possible to prevent interfacial peeling caused by stress.
  • the metallic material of the first barrier metal 2a diffuses into the semiconductor substrate 1, forming a diffusion layer 5 between the first barrier metal 2a and the semiconductor substrate 1.
  • the diffusion layer 5 has a higher adhesion to the barrier metal 2 and the semiconductor substrate 1 than the sputtered film and the evaporated film. Therefore, by forming the diffusion layer 5, it is possible to improve the adhesion between the semiconductor substrate 1 and the barrier metal 2.
  • the first barrier metal 2a is a polycrystal such as Ni3P , Ni12P5 , or Ni7P3 .
  • the crystal grains of the polycrystal are nanoscale.
  • the second barrier metal 2b is not a polycrystal but has a uniform amorphous structure. In the amorphous structure, phosphorus or boron enters between the lattices of the nickel crystals and distorts the crystals.
  • FIG. 2 is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.
  • hydrophilization and activator treatment are performed as pretreatment.
  • oxygen plasma treatment or ozone treatment is performed to modify the surface of the semiconductor substrate 1 to be hydrophilic.
  • an activated solution for electroless plating reaction containing Pd ions the surface of the semiconductor substrate 1 dissolves due to the effect of galvanic corrosion and Pd precipitates.
  • the Pd ion concentration is 10 ppm to 100 ppm
  • the solution temperature is 0°C to 50°C
  • the immersion time is 1 minute to 5 minutes.
  • the amount of Pd precipitate is too small, the Ni plating film that is subsequently formed will not be formed, and if it is too large, the adhesion between the films will deteriorate.
  • the ease of Pd precipitation differs depending on the type of semiconductor, it is necessary to adjust the amount within the above range depending on the type of substrate.
  • the substrate is immersed in an electroless Ni plating solution containing hypophosphorous acid as the main component.
  • the solution temperature is set to 70°C to 90°C.
  • the plating reaction can be stabilized by circulating, filtering, and shaking the solution, resulting in a smooth plating film.
  • Ni ions become Ni and are precipitated by the catalytic action of Pd, and P, a component of the solution, is co-precipitated to form a Ni-P alloy film.
  • Pd is used as an example of the catalytic metal here, but if any metal has catalytic activity for electroless plating deposition, such as Au, Ag, Pt, Ni, Sn, or Ru, a Ni alloy film can be obtained in the same manner.
  • a first barrier metal 2a with an amorphous structure is formed on the semiconductor substrate 1 by electroless plating.
  • the first barrier metal 2a may be formed by other means, such as PVD or vapor deposition. In that case, the pretreatment process of precipitating a catalytically active metal such as Pd is not necessary.
  • the wafer After removing the wafer from the electroless Ni plating solution and rinsing it with water, the wafer is immersed in the electroless Pd plating solution while still wet to form the diffusion prevention layer 4 on the first barrier metal 2a.
  • the thickness of the diffusion prevention layer 4 is, for example, 0.01 ⁇ m. If it is thicker than 0.1 ⁇ m, it will peel off at the boundary with the first barrier metal 2a, so it is designed to be 0.1 ⁇ m or less. If it is less than 0.01 microns, the deposition is not stable, so it is designed to be 0.01 ⁇ m or more.
  • the material of the diffusion prevention layer 4 is not limited to Pd, and other materials may be used as long as they can prevent interdiffusion.
  • plating of metals that have catalytic activity for electroless plating deposition such as Au, Ag, Pt, Sn, and Ru, can be used.
  • electroless plating is a simple and easy-to-use method for forming the diffusion prevention layer 4, but sputtering or vapor deposition may also be used.
  • a second barrier metal 2b having an amorphous structure is formed on the diffusion prevention layer 4 by electroless plating.
  • the method for forming the second barrier metal 2b is the same as the method for forming the first barrier metal 2a.
  • the wafer and copper plate are immersed in a copper sulfate plating solution, and electricity is passed through the outer periphery of the wafer as the cathode and the copper plate as the anode, forming a copper film 3 on the second barrier metal 2b in proportion to the amount of electricity supplied.
  • the temperature of the solution is set to 30°C.
  • electroless plating can also be used instead of electroplating.
  • the copper film 3 can also be formed by adjusting the additives.
  • Ni plating, Pd plating, and Au plating can be performed in sequence by electroless plating or electroplating in post-treatment. This improves the adhesion of the die bond or wire bond.
  • the first barrier metal 2a and the second barrier metal 2b are made of the same material, for example, a Ni-P film.
  • a Ni-P film When a Ni-P film is formed with a P concentration of 10 at. % to 25 at. %, it has an amorphous structure. Therefore, the first barrier metal 2a and the second barrier metal 2b to be formed have an amorphous structure with a co-deposited amount of phosphorus or boron of 10 at. % or more.
  • a heat treatment is performed at 150°C to 300°C. This causes the metallic material of the first barrier metal 2a to diffuse into the semiconductor substrate 1, forming a diffusion layer 5 between the first barrier metal 2a and the semiconductor substrate 1.
  • the first barrier metal 2a whose metallic material has diffused into the semiconductor substrate 1, crystallizes due to an increase in the co-deposition of P or B.
  • the diffusion prevention layer 4 prevents the diffusion of metallic atoms in the second barrier metal 2b, so the second barrier metal 2b maintains an amorphous structure even after the heat treatment with no change in film composition. Therefore, the second barrier metal 2b has high barrier properties against the diffusion of copper atoms in the copper film 3.
  • heat treatment can also be used to remove defective products before shipping.
  • Figures 3 and 4 are cross-sectional views showing a manufacturing method of a semiconductor device according to the comparative example.
  • one layer of barrier metal 6 is formed on a semiconductor substrate 1, and a copper film 3 is formed thereon.
  • the barrier metal 6 has an amorphous structure when formed.
  • a heat treatment is performed at 150°C to 300°C, the metal atoms of the barrier metal 6 diffuse into the semiconductor substrate 1, forming a diffusion layer 5, as shown in Figure 4.
  • the barrier metal 6 into which the metal atoms have diffused is entirely crystallized due to an increase in the codeposition of phosphorus or boron. As a result, the barrier metal 6 after the heat treatment has deteriorated barrier properties against the diffusion of copper atoms from the copper film 3.
  • the diffusion prevention layer 4 prevents the diffusion of metal atoms in the second barrier metal 2b, so the second barrier metal 2b does not crystallize even after heat treatment. Therefore, since the second barrier metal 2b has an amorphous structure, it is possible to obtain high barrier properties against the diffusion of copper atoms in the copper film 3.
  • the nickel diffusion layer 5 is thinner than when the barrier metal is a single layer of nickel alloy, so the stress caused by the diffusion layer 5 is reduced.
  • barrier metal 2 must be 0.1 ⁇ m or more to provide a barrier against the diffusion of copper atoms. However, if the thickness of barrier metal 2 is thicker than 0.5 ⁇ m, the device will bend due to stress. Therefore, the thickness of barrier metal 2 must be 0.1 ⁇ m or more and 0.5 ⁇ m or less.
  • Embodiment 2. 5 is a cross-sectional view showing a semiconductor device according to a second embodiment. This embodiment differs from the first embodiment in that there is no diffusion prevention layer 4 and a second barrier metal 2b is formed directly on a first barrier metal 2a. The other configurations are the same as those of the first embodiment.
  • Figures 6 to 8 are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment.
  • a first barrier metal 2a is formed on a semiconductor substrate 1 by electroless plating.
  • the first barrier metal 2a has an amorphous structure.
  • a heat treatment at 150°C to 300°C is performed to diffuse the metal atoms of the first barrier metal 2a into the semiconductor substrate 1, forming a diffusion layer 5 between the first barrier metal 2a and the semiconductor substrate 1.
  • the first barrier metal 2a is polycrystalline. Furthermore, a depth analysis confirmed that the P concentration in the Ni-P is uniform throughout the film even after Ni diffusion. Therefore, the concentration of the metal material and co-deposit of the first barrier metal 2a is uniform throughout the film after the heat treatment.
  • the second barrier metal 2b is formed directly on the first barrier metal 2a by electroless plating.
  • the first barrier metal 2a and the second barrier metal 2b are formed of the same material. If the first barrier metal 2a is polycrystallized, the elements of the two layers will not interdiffuse even if the second barrier metal 2b, which is composed of the same Ni and P, is laminated on the first barrier metal 2a. This is because the polycrystallized Ni-P crystal structure of the first barrier metal 2a is energetically stable compared to amorphous, and is in a state in which the structure is less likely to change.
  • the second barrier metal 2b has an amorphous structure.
  • An amorphous Ni-P film with a low concentration of phosphorus (10 at.% to 25 at.%) does not crystallize when heated to 300°C or lower. Therefore, the amorphous structure of the second barrier metal 2b is maintained if the heat treatment or usage environment is 300°C or lower.
  • a copper film 3 is formed on the second barrier metal 2b by electroless plating, thereby manufacturing the semiconductor device shown in FIG. 5.
  • the second barrier metal 2b remains in an amorphous structure. This makes it possible to obtain a high barrier property against the diffusion of copper atoms in the copper film 3.
  • the process of forming the diffusion prevention layer 4 between the first barrier metal 2a and the second barrier metal 2b is not required.
  • the diffusion layer 5 can be made thinner than when the barrier metal is formed in a single layer. Since the diffusion layer 5 is subject to high stress, making the diffusion layer 5 thinner can reduce the stress.
  • the first barrier metal 2a and the second barrier metal 2b are made of the same material, so they have high adhesion to each other.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
PCT/JP2023/009363 2023-03-10 2023-03-10 半導体装置及びその製造方法 WO2024189685A1 (ja)

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JP2025506241A JPWO2024189685A1 (enrdf_load_stackoverflow) 2023-03-10 2023-03-10
PCT/JP2023/009363 WO2024189685A1 (ja) 2023-03-10 2023-03-10 半導体装置及びその製造方法
TW113100725A TW202437394A (zh) 2023-03-10 2024-01-08 半導體裝置及其製造方法

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050104216A1 (en) * 2003-11-18 2005-05-19 International Business Machines Corporation Electroplated CoWP composite structures as copper barrier layers
JP2011044546A (ja) * 2009-08-20 2011-03-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2013166998A (ja) * 2012-02-16 2013-08-29 Jx Nippon Mining & Metals Corp 無電解Ｎｉめっき被膜を有する構造物、半導体ウェハ及びその製造方法
JP2014112634A (ja) * 2012-10-30 2014-06-19 Mitsubishi Electric Corp 半導体素子の製造方法、半導体素子
US20150311150A1 (en) * 2014-04-25 2015-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Contact Structure and Method of Forming the Same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050104216A1 (en) * 2003-11-18 2005-05-19 International Business Machines Corporation Electroplated CoWP composite structures as copper barrier layers
JP2011044546A (ja) * 2009-08-20 2011-03-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2013166998A (ja) * 2012-02-16 2013-08-29 Jx Nippon Mining & Metals Corp 無電解Ｎｉめっき被膜を有する構造物、半導体ウェハ及びその製造方法
JP2014112634A (ja) * 2012-10-30 2014-06-19 Mitsubishi Electric Corp 半導体素子の製造方法、半導体素子
US20150311150A1 (en) * 2014-04-25 2015-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Contact Structure and Method of Forming the Same

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JPWO2024189685A1 (enrdf_load_stackoverflow) 2024-09-19

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