WO2024176988A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024176988A1
WO2024176988A1 PCT/JP2024/005655 JP2024005655W WO2024176988A1 WO 2024176988 A1 WO2024176988 A1 WO 2024176988A1 JP 2024005655 W JP2024005655 W JP 2024005655W WO 2024176988 A1 WO2024176988 A1 WO 2024176988A1
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WO
WIPO (PCT)
Prior art keywords
resin
semiconductor device
coil
insulating layer
resin portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2024/005655
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English (en)
French (fr)
Japanese (ja)
Inventor
文悟 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2025502699A priority Critical patent/JPWO2024176988A1/ja
Publication of WO2024176988A1 publication Critical patent/WO2024176988A1/ja
Priority to US19/296,601 priority patent/US20250364404A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • This disclosure relates to a semiconductor device.
  • semiconductor devices include a transformer that is used as an insulating element in transmitting signals and power.
  • the transformer includes a pair of coils that are arranged facing each other in the vertical direction (see, for example, Patent Document 1).
  • a semiconductor device includes a semiconductor element including a first element surface and a second element surface facing opposite each other in the thickness direction, a plurality of element side surfaces intersecting the first element surface and the second element surface, an element insulating layer including an insulating surface constituting the first element surface, and a first conductor provided in the element insulating layer, a first resin surface facing the same direction as the first element surface, a first resin part covering the first element surface, a second conductor formed on the first resin surface, and a second resin part including a second resin surface facing the same direction as the first resin surface and covering the first resin surface and the second conductor, the first conductor and the second conductor facing each other in the thickness direction with the element insulating layer and the first resin part sandwiched therebetween, and at least one of the plurality of element side surfaces is exposed without being covered by both the first resin part and the second resin part.
  • the semiconductor device according to one aspect of the present disclosure can improve the dielectric strength voltage.
  • FIG. 1 is a circuit diagram showing a schematic configuration of a signal transmission device.
  • FIG. 2 is a perspective view showing a schematic diagram of the signal transmission device of FIG.
  • FIG. 3 is a schematic perspective view showing the semiconductor device of FIG.
  • FIG. 4 is a schematic perspective view of the semiconductor device of FIG. 3 as viewed from a different direction.
  • FIG. 5 is a schematic plan view showing the configuration of the semiconductor device of FIG.
  • FIG. 6 is a schematic plan view showing a configuration related to the first coil of the semiconductor device of FIG.
  • FIG. 7 is a schematic plan view showing a configuration related to the second coil of the semiconductor device of FIG.
  • FIG. 8 is a schematic cross-sectional view taken along line 8-8 in FIG.
  • FIG. 9 is a schematic cross-sectional view taken along line 9-9 in FIG.
  • FIG. 10 is a schematic cross-sectional view showing an example of a manufacturing process of a semiconductor device.
  • FIG. 11 is a schematic plan view showing a semiconductor device according to a modified example.
  • FIG. 12 is a schematic cross-sectional view showing a semiconductor device according to a modified example.
  • FIG. 13 is a schematic cross-sectional view showing a semiconductor device according to a modified example.
  • At least one means “one or more” of the desired options.
  • at least one means “only one option” or “both of two options” if the number of options is two.
  • at least one means “only one option” or “any combination of two or more options” if the number of options is three or more.
  • FIG. 1 shows a simplified example of the circuit configuration of the signal transmission device 900.
  • Figure 2 is a perspective view showing the signal transmission device 900.
  • the signal transmission device 900 is a device that transmits a pulse signal while electrically isolating a first terminal 901 and a second terminal 902.
  • the signal transmission device 900 is, for example, a digital isolator.
  • the signal transmission device 900 includes a first circuit 911 electrically connected to the first terminal 901, a second circuit 912 electrically connected to the second terminal 902, and a transformer 913 that electrically isolates the first circuit 911 and the second circuit 912.
  • the first circuit 911 is a circuit configured to operate when a first voltage V1 is applied.
  • the first circuit 911 is electrically connected to, for example, an external control device (not shown).
  • the first circuit 911 includes a transmission circuit 911A.
  • the second circuit 912 is a circuit configured to operate when a second voltage V2 different from the first voltage V1 is applied.
  • the second voltage V2 is, for example, higher than the first voltage V1.
  • the first voltage V1 and the second voltage V2 are DC voltages.
  • the second circuit 912 is electrically connected to, for example, a drive circuit that is controlled by the control device.
  • An example of a drive circuit is a switching circuit.
  • the second circuit 912 includes a reception circuit 912A.
  • the ground of the first circuit 911 and the ground of the second circuit 912 are provided independently of each other.
  • the transformer 913 is connected between the transmitting circuit 911A and the receiving circuit 912A.
  • the transformer 913 includes two coils 913A and 913B.
  • the coil 913A is connected to the transmitting circuit 911A, and the coil 913B is connected to the receiving circuit 912A.
  • a control signal from a control device is input to the transmitting circuit 911A of the first circuit 911 through the first terminal 901.
  • the control signal passes from the transmitting circuit 911A of the first circuit 911 through the transformer 913 and is received by the receiving circuit 912A of the second circuit 912.
  • the signal transmitted to the second circuit 912 is output from the second circuit 912 to the drive circuit through the second terminal 902.
  • the first terminal 901 can be considered an input terminal that inputs a signal to the signal transmission device 900.
  • the second terminal 902 can be considered an output terminal from which a signal is output from the signal transmission device 900.
  • the first circuit 911 and the second circuit 912 are electrically insulated by the transformer 913. More specifically, the transformer 913 regulates the transmission of DC voltage between the first circuit 911 and the second circuit 912. Furthermore, while the transformer 913 regulates the transmission of DC voltage between the first circuit 911 and the second circuit 912, it allows the transmission of a pulse signal.
  • the state in which the first circuit 911 and the second circuit 912 are insulated means a state in which the transmission of DC voltage between the first circuit 911 and the second circuit 912 is blocked, while the transmission of a pulse signal from the first circuit 911 to the second circuit 912 is permitted.
  • the second circuit 912 is configured to receive a signal from the first circuit 911.
  • the signal transmission device 900 includes a substrate 920 and a plurality of semiconductor devices 931 , 932 , and 10 .
  • the substrate 920 is formed, for example, in a quadrangular plate shape.
  • the substrate 920 includes a substrate front surface 921 and a substrate back surface 922 facing the opposite side to the substrate front surface 921.
  • the substrate front surface 921 and the substrate back surface 922 are, for example, rectangular in shape.
  • a plurality of first terminals 941 and a plurality of second terminals 942 are formed on the substrate surface 921.
  • the plurality of first terminals 941 and the plurality of second terminals 942 are formed of a material containing, for example, Cu (copper).
  • the plurality of first terminals 941 are disposed at a first end 923 of the substrate 920.
  • the plurality of second terminals 942 are disposed at a second end 924 of the substrate 920 opposite the first end 923.
  • the multiple first terminals 941 include a power supply terminal that supplies the first voltage V1 shown in FIG. 1, a ground terminal that is connected to the ground of the first circuit 911, and the first terminal 901.
  • the multiple second terminals 942 include a power supply terminal that supplies the second voltage V2 shown in FIG. 1, a ground terminal that is connected to the ground of the second circuit 912, and the second terminal 902.
  • the semiconductor devices 931, 932, and 10 are mounted on a substrate surface 921 of the substrate 920.
  • the semiconductor devices 931, 932, and 10 are connected to pads (not shown) formed on the substrate surface 921.
  • the pads are connected to a first terminal 941 and a second terminal 942 by wiring (not shown).
  • the substrate 920 may be, for example, a semiconductor substrate, an insulating substrate formed from a material containing epoxy resin or the like, an insulating substrate formed from a material containing glass, an insulating substrate formed from a material containing ceramics such as alumina, or the like.
  • Semiconductor device 931 includes a first circuit 911 shown in FIG. 1.
  • Semiconductor device 932 includes a second circuit 912 shown in FIG. 1.
  • Semiconductor device 10 includes a transformer 913 shown in FIG. 1.
  • Semiconductor devices 931, 932, and 10 can be referred to as semiconductor chips.
  • Signal transmission device 900 can be referred to as a semiconductor module.
  • Signal transmission device 900 can also be referred to as a multi-chip module including multiple semiconductor chips.
  • the semiconductor device 10 including the transformer 913 can be said to be an insulating chip that provides insulation between the semiconductor device 931 including the first circuit 911 and the semiconductor device 932 including the second circuit 912.
  • the semiconductor devices 931, 932, and 10 are arranged in the order of the semiconductor device 931 including the first circuit 911, the semiconductor device 10 including the transformer 913, and the semiconductor device 932 including the second circuit 912 from the first terminal 941 to the second terminal 942.
  • the signal transmission device 900 may include a sealing member that seals the multiple semiconductor devices 931, 932, and 10 mounted on the substrate surface 921.
  • the sealing member may be, for example, a case that houses the substrate 920 and the multiple semiconductor devices 931, 932, and 10.
  • the case may be filled with a resin such as silicone resin.
  • the sealing member may be a sealing resin that covers at least the multiple semiconductor devices 931, 932, and 10.
  • the sealing resin may be, for example, a molded resin containing epoxy resin or the like.
  • FIGS. 3 and 4 are perspective views showing the appearance of the semiconductor device 10, where FIG. 3 is a perspective view of the semiconductor device 10 seen from the top side, and FIG. 4 is a perspective view of the semiconductor device 10 seen from the bottom side.
  • FIG. 5 is a plan view of the semiconductor device 10 seen from the bottom side. Note that FIG. 5 shows the sealing resin 80 and the element insulating layer 22 in a see-through manner.
  • FIG. 6 is a plan view showing the semiconductor device 10. Note that FIG. 6 shows the element insulating layer 22 in a see-through manner.
  • FIG. 7 is a plan view showing the conductive part 40. Note that FIG.
  • FIG. 7 shows the sealing resin 80 in a see-through manner.
  • FIG. 8 is a schematic cross-sectional view of the semiconductor device 10 taken along line 8-8 in FIG. 5.
  • FIG. 9 is a schematic cross-sectional view of the semiconductor device 10 taken along line 9-9 in FIG. 5. Note that, for convenience, in FIGS. 8 and 9, members that are not on the line showing the cross-sectional position may be shown, or the positions and sizes of members may differ from those in FIGS. 5 to 7.
  • the semiconductor device 10 is, for example, a rectangular parallelepiped.
  • the thickness direction of the semiconductor device 10 is defined as the z direction.
  • the direction perpendicular to the z direction is defined as the x direction, and the direction perpendicular to the z direction and the x direction is defined as the y direction. Viewing an object from the z direction is referred to as viewing it in a planar view.
  • the semiconductor device 10 includes a device top surface 10S, a device bottom surface 10R, and multiple device side surfaces 11, 12, 13, and 14.
  • the device top surface 10S and the device bottom surface 10R face in opposite directions from each other in the z direction.
  • the multiple device side surfaces 11, 12, 13, and 14 intersect the device top surface 10S and the device bottom surface 10R.
  • the device side surfaces 11 and 12 face in opposite directions from each other in the x direction.
  • the device side surfaces 13 and 14 face in opposite directions from each other in the y direction.
  • the semiconductor device 10 includes an external connection member SB.
  • the external connection member SB is provided on the underside 10R of the device.
  • the external connection member SB is, for example, a solder ball formed from solder.
  • the semiconductor device 10 is mounted on the substrate 920 shown in FIG. 2 by the external connection member SB.
  • the semiconductor device 10 includes a semiconductor element 20, a surface resin layer 30, a conductive portion 40, and a sealing resin 80.
  • the semiconductor element 20 includes a first coil 26.
  • the conductive portion 40 includes a second coil 43 and external connection terminals 51A, 51B, 61A, and 61B.
  • the first coil 26 and the second coil 43 correspond to the coils 913A and 913B shown in Fig. 1.
  • the semiconductor element 20 is mounted on the conductive portion 40, and the first coil 26 of the semiconductor element 20 faces the second coil 43 of the conductive portion 40 in the z-direction.
  • the external connection terminals 51A, 51B, 61A, and 61B are exposed from the surface 30S of the surface resin layer 30.
  • the semiconductor element 20 includes an element front surface 20S, an element rear surface 20R, and element side surfaces 201, 202, 203, and 204.
  • the element front surface 20S corresponds to the "first element surface”.
  • the element rear surface 20R corresponds to the "second element surface”.
  • the element front surface 20S and the element rear surface 20R face in opposite directions in the z direction.
  • the element front surface 20S faces in the same direction as the resin rear surface 80R.
  • the semiconductor element 20 is disposed so that the element front surface 20S faces in the same direction as the resin lower surface.
  • the element side surfaces 201, 202, 203, and 204 intersect with the element front surface 20S and the element rear surface 20R.
  • the element side surfaces 201, 202, 203, and 204 are orthogonal to the element front surface 20S and the element rear surface 20R.
  • the element side surfaces 201 and 202 face in opposite directions in the x direction.
  • the element side surfaces 203 and 204 face in opposite directions in the y direction.
  • a semiconductor device 20 includes a device substrate 21 .
  • the element substrate 21 is a semiconductor substrate and is made of a material containing, for example, silicon (Si).
  • the element substrate 21 is a Si substrate.
  • the element substrate 21 has a substrate surface 21S, a substrate back surface 21R, and multiple substrate side surfaces 211, 212, 213, and 214.
  • the substrate surface 21S and the substrate back surface 21R face opposite each other in the Z direction.
  • the substrate side surfaces 211 and 212 face opposite each other in the X direction.
  • the substrate side surfaces 213 and 214 face opposite each other in the Y direction.
  • the substrate surface 21S corresponds to the "first substrate surface.”
  • the substrate back surface 21R corresponds to the "second substrate surface.”
  • the element insulating layer 22 is formed to cover the substrate surface 21S.
  • the element insulating layer 22 includes an insulating surface 22S, an insulating back surface 22R, and multiple insulating side surfaces 221, 222, 223, and 224.
  • the insulating surface 22S of the element insulating layer 22 faces the same direction as the substrate surface 21S.
  • the insulating back surface 22R of the element insulating layer 22 faces the opposite side to the insulating surface 22S of the element insulating layer 22.
  • the insulating back surface 22R of the element insulating layer 22 faces the substrate surface 21S side and is in contact with the substrate surface 21S.
  • Each of the insulating side surfaces 221, 222, 223, and 224 of the element insulating layer 22 faces the same direction as each of the element side surfaces 201, 202, 203, and 204.
  • the insulating surface 22S of the element insulating layer 22 constitutes the element surface 20S of the semiconductor element 20.
  • the substrate back surface 21R of the element substrate 21 constitutes the element back surface 20R of the semiconductor element 20.
  • the substrate side surfaces 211-214 of the element substrate 21 and the insulating side surfaces 221-224 of the element insulating layer 22 constitute the element side surfaces 201-204 of the semiconductor element 20.
  • the semiconductor element 20 includes a first coil 26.
  • the first coil 26 corresponds to a "first conductor.”
  • the first coil 26 is formed in a spiral shape in a plan view.
  • the first coil 26 includes an outer first end 26A and an inner second end 26B.
  • the first end 26A corresponds to an "outer end.”
  • the second end 26B corresponds to an "inner end.”
  • the first coil 26 is provided in the element insulating layer 22.
  • the element insulating layer 22 includes three insulating layers 23, 24, and 25.
  • the insulating layers 23, 24, and 25 are stacked in this order from the substrate surface 21S of the element substrate 21.
  • the first coil 26 is formed on the surface 24S of the second insulating layer 24.
  • the first coil 26 and the surface 24S of the second insulating layer 24 are covered by the third insulating layer 25.
  • the element insulating layer 22 has insulating properties.
  • the first insulating layer 23, the second insulating layer 24, and the third insulating layer 25 are made of a material containing, for example, Si (silicon).
  • the first insulating layer 23, the second insulating layer 24, and the third insulating layer 25 are made of, for example, SiO 2 (silicon oxide), SiN (silicon nitride), or the like.
  • the materials constituting the first insulating layer 23, the second insulating layer 24, and the third insulating layer 25 may be changed as appropriate.
  • the first insulating layer 23, the second insulating layer 24, and the third insulating layer 25 may be made of an insulating resin such as, for example, polyimide resin, phenolic resin, or epoxy resin.
  • the semiconductor element 20 includes a plurality of connection pads 27A, 27B.
  • the connection pads 27A, 27B correspond to "element pads”.
  • the plurality of connection pads 27A, 27B are arranged in the same position as the first coil 26 in the z direction.
  • the plurality of connection pads 27A, 27B are provided on the surface 24S of the second insulating layer 24.
  • the third insulating layer 25 is formed so as to cover the periphery of the connection pads 27A, 27B.
  • the third insulating layer 25 includes an opening 25X that exposes a portion of the connection pads 27A, 27B.
  • the insulating layers 23, 24 correspond to the "first insulating layer”.
  • the insulating layer 25 corresponds to the "second insulating layer”.
  • connection pad 27A is electrically connected to the first end 26A of the first coil 26.
  • the connection pad 27B is electrically connected to the second end 26B of the first coil 26 by the element wiring 28.
  • the element wiring 28 corresponds to the "first wiring layer.” Therefore, the first coil 26 is connected between the connection pad 27A and the connection pad 27B.
  • the element wiring 28 is formed on the surface 23S of the first insulating layer 23.
  • the element wiring 28 is formed of a material including, for example, Cu, Al (aluminum), etc.
  • a first end 28A of the element wiring 28 is electrically connected to the first coil 26 by a via 29A.
  • a second end 28B of the element wiring 28 is electrically connected to the connection pad 27B by a via 29B.
  • the vias 29A and 29B penetrate the second insulating layer 24.
  • the vias 29A and 29B are formed of a material including, for example, Cu, Al, W (tungsten), etc.
  • the surface resin layer 30 is provided on an insulating surface 22S of the element insulating layer 22.
  • the element insulating layer 22 includes a first insulating layer 23, a second insulating layer 24, and a third insulating layer 25.
  • the surface resin layer 30 is provided on a surface 25S of the third insulating layer 25.
  • the surface resin layer 30 includes a first resin part 31 and a second resin part 32.
  • the first resin part 31 is provided on the insulating surface 22S of the element insulating layer 22.
  • the first resin part 31 contacts the insulating surface 22S of the element insulating layer 22.
  • the first resin part 31 includes a first resin surface 31S facing the z direction and a first resin back surface 31R facing the opposite side to the first resin surface 31S.
  • the first resin surface 31S corresponds to the "first resin surface.”
  • the first resin back surface 31R of the first resin part 31 contacts the insulating surface 22S of the element insulating layer 22.
  • the first resin part 31 includes first resin side surfaces 311, 312, 313, and 314.
  • the first resin side surfaces 311 to 314 intersect with the first resin surface 31S and the first resin back surface 31R.
  • the first resin side surfaces 311 to 314 are perpendicular to the first resin surface 31S and the first resin back surface 31R.
  • the first resin side surfaces 311 and 312 face in opposite directions to each other in the x direction.
  • the first resin side surfaces 313 and 314 face in opposite directions to each other in the y direction.
  • the second resin part 32 includes a second resin surface 32S facing the z direction and a second resin back surface 32R facing the opposite side to the second resin surface 32S.
  • the second resin surface 32S corresponds to the "second resin surface.”
  • the second resin back surface 32R of the second resin part 32 contacts the first resin surface 31S of the first resin part 31.
  • the second resin part 32 includes a plurality of second resin side surfaces 321, 322, 323, 324.
  • the second resin side surfaces 321 to 324 intersect with the second resin surface 32S and the second resin back surface 32R. In one example, the second resin side surfaces 321 to 324 are perpendicular to the second resin surface 32S and the second resin back surface 32R.
  • the second resin side surfaces 321, 322 face in opposite directions to each other in the x direction.
  • the second resin side surfaces 323, 324 face in opposite directions to each other in the y direction.
  • the first resin part 31 and the second resin part 32 are made of a resin having insulating properties.
  • the resin having insulating properties is, for example, polyimide resin, phenolic resin, epoxy resin, etc.
  • the material making up the first resin part 31 may be different from the material making up the second resin part 32.
  • the material making up the first resin part 31 and the material making up the second resin part 32 may have different pressure resistances.
  • the first resin part 31 may be made of a material having a higher pressure resistance than the second resin part 32.
  • the material making up the first resin part 31 and the material making up the second resin part 32 may have different adhesion.
  • the first resin part 31 may be made of a material having a higher adhesion than the second resin part 32.
  • the first resin part 31 and the second resin part 32 are formed to have the same size as the element substrate 21 and the element insulating layer 22 when viewed from the z direction. Therefore, the first resin side surface 311 of the first resin part 31, the second resin side surface 321 of the second resin part 32, the insulating side surface 221 of the element insulating layer 22, and the substrate side surface 211 of the element substrate 21 are at the same position in the x direction, that is, they are flush. Similarly, the first resin side surface 312 of the first resin part 31, the second resin side surface 322 of the second resin part 32, the insulating side surface 222 of the element insulating layer 22, and the substrate side surface 212 of the element substrate 21 are at the same position in the x direction, that is, they are flush.
  • the first resin side surface 313 of the first resin part 31, the second resin side surface 323 of the second resin part 32, the insulating side surface 223 of the element insulating layer 22, and the substrate side surface 213 of the element substrate 21 are at the same position in the y direction, that is, they are flush.
  • the first resin side surface 314 of the first resin part 31, the second resin side surface 324 of the second resin part 32, the insulating side surface 224 of the element insulating layer 22, and the substrate side surface 214 of the element substrate 21 are at the same position in the y direction, i.e., they are flush.
  • At least one of the element side surfaces 201-204 of the semiconductor element 20 is exposed without being covered by both the first resin part 31 and the second resin part 32. In one example, all of the multiple element side surfaces 201-204 are exposed from both the first resin part 31 and the second resin part 32.
  • the thickness T22 of the first resin part 31 is greater than the thickness T23 of the second resin part 32.
  • the thickness T22 of the first resin part 31 may be equal to the thickness T23 of the second resin part 32.
  • the thickness T22 of the first resin part 31 may be smaller than the thickness T23 of the second resin part 32.
  • the conductive portion 40 includes a first wiring member 41, a second wiring member 42, and a second coil 43.
  • the conductive portion 40 is embedded in the surface resin layer 30.
  • the first wiring member 41 includes a first external connection terminal 51A, a second external connection terminal 51B, a first pad connection portion 53A, a second pad connection portion 53B, a first connection wiring 54A, a second connection wiring 54B, a first terminal connection portion 55A, and a second terminal connection portion 55B.
  • the second wiring member 42 includes a third external connection terminal 61A, a fourth external connection terminal 61B, a third terminal connection portion 65A, a fourth terminal connection portion 65B, and a third connection wiring 64.
  • the third terminal connection portion 65A, the fourth terminal connection portion 65B, and the third connection wiring 64 correspond to the "second lead-out wiring.”
  • the first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B are formed in a rectangular shape in a plan view.
  • the shapes of the first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B can be changed to any shape, such as a circle or a polygon, in a plan view.
  • the first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B can be made of a material containing Cu, for example.
  • the first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B can include a conductive layer (plating layer) such as an Au (gold) layer, a Ni (nickel) Pd (palladium) layer, etc.
  • the first pad connection portion 53A, the second pad connection portion 53B, the first connection wiring 54A, the second connection wiring 54B, the first terminal connection portion 55A, and the second terminal connection portion 55B are formed on the first resin surface 31S of the first resin part 31.
  • the third terminal connection portion 65A, the fourth terminal connection portion 65B, and the third connection wiring 64 are formed on the first resin surface 31S of the first resin part 31.
  • the first external connection terminal 51A and the second external connection terminal 51B are arranged along the device side surface 12 of the semiconductor device 10, in one example.
  • the first external connection terminal 51A and the second external connection terminal 51B are arranged at a distance in the y direction.
  • the first external connection terminal 51A and the second external connection terminal 51B are arranged side by side in the y direction in a plan view.
  • the first external connection terminal 51A is arranged at a corner portion formed by the device side surface 12 and the device side surface 13 of the semiconductor device 10.
  • the second external connection terminal 51B is arranged at a corner portion formed by the device side surface 12 and the device side surface 14 of the semiconductor device 10.
  • the first pad connection portion 53A and the second pad connection portion 53B are arranged in a position overlapping the connection pads 27A, 27B in the z direction.
  • the first pad connection portion 53A and the second pad connection portion 53B are electrically connected to the connection pads 27A, 27B by the through-wires 46A, 46B.
  • the through-wires 46A, 46B are provided in the through-holes 31X that penetrate the first resin portion 31.
  • the first pad connection portion 53A and the second pad connection portion 53B are formed in a rectangular shape when viewed in a plane. Note that the shape of the first pad connection portion 53A and the second pad connection portion 53B can be changed to any shape, such as a circle or a polygon, when viewed in a plane.
  • the first pad connection portion 53A is electrically connected to the first external connection terminal 51A by a first connection wiring 54A.
  • the second pad connection portion 53B is electrically connected to the second external connection terminal 51B by a second connection wiring 54B.
  • the third external connection terminal 61A is disposed on the side of the device side 11 of the semiconductor device 10. In one example, the third external connection terminal 61A is disposed in the center of the device side 11 in the y direction in a plan view. The position of the third external connection terminal 61A can be changed as desired. For example, the third external connection terminal 61A may be disposed in a corner formed by the device side 11 and device side 13 of the semiconductor device 10, or in a corner formed by the device side 11 and device side 14.
  • the fourth external connection terminal 61B is disposed in the center of the semiconductor device 10 in a plan view.
  • the third external connection terminal 61A is disposed in the same position as the fourth external connection terminal 61B in the y direction in a plan view.
  • the third external connection terminal 61A and the fourth external connection terminal 61B are disposed side by side in the x direction in a plan view.
  • the second coil 43 is formed in a spiral shape in a plan view.
  • the second coil 43 includes an outer first end 43A and an inner second end 43B.
  • the first end 43A corresponds to the "outer end”.
  • the second end 43B corresponds to the "inner end”.
  • the first end 43A of the second coil 43 is electrically connected to the third external connection terminal 61A via the third connection wiring 64.
  • the second end 43B of the second coil 43 is electrically connected to the fourth external connection terminal 61B.
  • the second coil 43 is provided on the first resin surface 31S of the first resin part 31.
  • the first resin part 31 covers the insulating surface 22S of the element insulating layer 22.
  • the first coil 26 is embedded in the element insulating layer 22.
  • the second coil 43 is arranged so as to overlap the first coil when viewed from the z direction. Therefore, the first coil 26 and the second coil 43 face each other in the z direction, sandwiching the element insulating layer 22 and the first resin part 31 between them.
  • the width W1 of the first coil 26 in a direction parallel to the element surface 20S is defined as, for example, the width in the y direction.
  • the width W2 of the second coil 43 in a direction parallel to the element surface 20S is defined as, for example, the width in the y direction.
  • the width W1 of the first coil 26 corresponds to the "first width dimension”
  • the width W2 of the second coil 43 corresponds to the "second width dimension”.
  • the width W1 of the first coil 26 is equal to the width W2 of the second coil 43.
  • the width W1 of the first coil 26 may be smaller than the width W2 of the second coil 43.
  • the width W1 of the first coil 26 may be larger than the width W2 of the second coil 43.
  • the thickness T12 of the second coil 43 in the z direction is greater than the thickness T11 of the first coil 26.
  • the thickness T11 of the first coil 26 may be equal to the thickness T12 of the second coil 43.
  • the thickness T12 of the second coil 43 may be smaller than the thickness T11 of the first coil 26.
  • the thickness T22 of the first resin part 31 is greater than the thickness of the third insulating layer 25 covering the first coil 26 of the semiconductor element 20. More specifically, the thickness T22 of the first resin part 31 is greater than the thickness T21 of the element resin part 25A of the third insulating layer 25 from the first coil 26 to the element surface 20S.
  • the thickness T22 of the first resin part 31 of the surface resin layer 30 corresponds to the thickness of the first resin part 31 interposed between the first coil 26 and the second coil 43.
  • the thickness T21 of the element resin part 25A of the third insulating layer 25 corresponds to the thickness of the element insulating layer 22 interposed between the first coil 26 and the second coil 43.
  • the sum of the thickness T22 of the first resin part 31 and the thickness T21 of the element insulating layer 22 corresponds to the distance D12 between the first coil 26 and the second coil 43 in the z direction.
  • the semiconductor device 10 includes a sealing resin 80.
  • the sealing resin 80 is provided on the substrate rear surface 21R of the element substrate 21.
  • the sealing resin 80 includes a resin surface 80S, a resin rear surface 80R, and multiple resin side surfaces 81, 82, 83, and 84.
  • the resin surface 80S and the resin rear surface 80R face in opposite directions to each other in the z direction.
  • the resin side surfaces 81 to 84 intersect with the resin surface 80S and the resin rear surface 80R.
  • the resin side surfaces 81 to 84 are perpendicular to the resin surface 80S and the resin rear surface 80R.
  • the resin side surfaces 81 and 82 face in opposite directions to each other in the x direction.
  • the resin side surfaces 83 and 84 face in opposite directions to each other in the y direction.
  • the resin back surface 80R of the sealing resin 80 contacts the substrate back surface 21R of the element substrate 21. Therefore, the sealing resin 80 covers the element back surface 20R of the semiconductor element 20.
  • the resin front surface 80S of the sealing resin 80 constitutes the device top surface 10S of the semiconductor device 10.
  • the element side surfaces 201 to 204 of the semiconductor element 20 are exposed from the sealing resin 80.
  • the semiconductor device 10 is formed by a process of singulation. 10 is a schematic cross-sectional view showing the semiconductor device 10 formed by the singulation process.
  • the members forming the semiconductor device 10 are denoted by the same reference numerals as the components of the semiconductor device 10 and will be described.
  • the base material 21 is a substrate (Si substrate), for example, in a wafer state.
  • the base material 21 includes a base material front surface 21S and a base material rear surface 21R facing opposite each other.
  • An element insulating layer 22, a front surface resin layer 30, a first coil 26, a second coil 43, etc. are formed on the base material front surface 21S.
  • a sealing resin 80 is formed on the base material rear surface 21R.
  • the semiconductor device 10 includes a semiconductor element 20.
  • the semiconductor element 20 includes an element front surface 20S and an element back surface 20R facing opposite to each other in the z direction, and a plurality of element side surfaces 201 to 204 intersecting the element front surface 20S and the element back surface 20R.
  • the semiconductor element 20 includes an element insulating layer 22 including an insulating surface 22S constituting the element front surface 20S, and a first coil 26 provided in the element insulating layer 22.
  • the semiconductor device 10 includes a first resin part 31, a second resin part 32, and a second coil 43.
  • the first resin part 31 covers the element surface 20S of the semiconductor element 20.
  • the first resin part 31 includes a first resin surface 31S that faces the same direction as the element surface 20S of the semiconductor element 20.
  • the second coil 43 is formed on the first resin surface 31S.
  • the second resin part 32 includes a second resin surface 32S that faces the same direction as the first resin surface 31S, and covers the first resin surface 31S and the second coil 43.
  • the first coil 26 and the second coil 43 face each other in the z direction, sandwiching the element insulating layer 22 and the first resin part 31 between them. At least one element side surface of the multiple element side surfaces 201 to 204 is exposed without being covered by both the first resin part 31 and the second resin part 32.
  • the dielectric strength of the semiconductor device 10 is determined by the distance D12 between the first coil 26 and the second coil 43 in the z direction.
  • the element insulating layer 22 and the first resin part 31 of the surface resin layer 30 are interposed between the first coil 26 and the second coil 43. Therefore, by increasing the thickness of the element insulating layer 22 and the first resin part 31 between the first coil 26 and the second coil 43, the dielectric strength of the semiconductor device 10 can be improved.
  • the semiconductor device 10 can be made smaller than a semiconductor device in which the element side surfaces 201-204 are covered with a sealing resin.
  • the semiconductor device 10 includes a semiconductor element 20.
  • the semiconductor element 20 includes an element front surface 20S and an element back surface 20R that face in opposite directions in the z direction, and a plurality of element side surfaces 201 to 204 that intersect with the element front surface 20S and the element back surface 20R.
  • the semiconductor element 20 includes an element insulating layer 22 that includes an insulating surface 22S that constitutes the element front surface 20S, and a first coil 26 provided in the element insulating layer 22.
  • the semiconductor device 10 includes a first resin part 31, a second resin part 32, and a second coil 43. The first resin part 31 covers the element front surface 20S of the semiconductor element 20.
  • the first resin part 31 includes a first resin surface 31S that faces the same direction as the element front surface 20S of the semiconductor element 20.
  • the second coil 43 is formed on the first resin surface 31S.
  • the second resin part 32 includes a second resin surface 32S facing in the same direction as the first resin surface 31S, and covers the first resin surface 31S and the second coil 43.
  • the first coil 26 and the second coil 43 face each other in the z direction with the element insulating layer 22 and the first resin part 31 between them. At least one of the multiple element side surfaces 201 to 204 is exposed without being covered by both the first resin part 31 and the second resin part 32.
  • the dielectric strength of the semiconductor device 10 is determined by the distance D12 between the first coil 26 and the second coil 43 in the z direction.
  • the element insulating layer 22 and the first resin part 31 of the surface resin layer 30 are interposed between the first coil 26 and the second coil 43. Therefore, by increasing the thickness of the element insulating layer 22 and the first resin part 31 between the first coil 26 and the second coil 43, the dielectric strength of the semiconductor device 10 can be improved.
  • the semiconductor device 10 In the semiconductor device 10, at least one of the multiple element side surfaces 201-204 is exposed and not covered by either the first resin part 31 or the second resin part 32. Therefore, the semiconductor device 10 can be made smaller than a semiconductor device in which the element side surfaces 201-204 are covered with a sealing resin.
  • FIG. 11 shows a schematic plan view of a semiconductor device 110 according to a modified example.
  • the position of the third external connection terminal 61A is changed compared to the semiconductor device 10 described above.
  • the third external connection terminal 61A is disposed at a corner portion formed by the device side surface 11 and the device side surface 13 of the semiconductor device 110. It is preferable that a dummy terminal connection portion 65C and a dummy external connection terminal 61C are provided at a corner portion formed by the device side surface 11 and the device side surface 14 of the semiconductor device 110.
  • the dummy terminal connection portion 65C and the dummy external connection terminal 61C suppress the inclination of the semiconductor device 110 when the semiconductor device 110 is mounted on the substrate 920 shown in FIG. 2, for example.
  • the surface resin layer 30 may be composed of three or more resin parts. 12, the semiconductor device 210 includes a surface resin layer 230.
  • the surface resin layer 230 includes a first resin part 231 and a second resin part 32.
  • the first resin part 231 can include a first resin layer 231A and a second resin layer 231B.
  • the material constituting the first resin layer 231A can be the same as the material constituting the second resin layer 231B. Note that the material constituting the first resin layer 231A and the material constituting the second resin layer 231B may be different from each other.
  • a semiconductor element capacitor chip that uses a capacitor to provide insulation between the first circuit 911 and the second circuit 912 can be used.
  • a capacitor chip that includes a capacitor is an example of a semiconductor device that includes an insulated configuration.
  • the semiconductor device 310 shown in FIG. 13 includes a first electrode plate 326 and a second electrode plate 343.
  • the first electrode plate 326 corresponds to the "first conductor.”
  • the second electrode plate 343 corresponds to the "second conductor.”
  • the first electrode plate 326 is embedded in the element insulating layer 22.
  • the element insulating layer 22 includes a first insulating layer 23, a second insulating layer 24, and a third insulating layer 25.
  • the first electrode plate 326 is provided on the surface 24S of the second insulating layer 24 of the element insulating layer 22.
  • the first electrode plate 326 and the surface 24S of the second insulating layer 24 are covered by the third insulating layer 25.
  • the second electrode plate 343 is embedded in the surface resin layer 30.
  • the surface resin layer 30 includes a first resin part 31 and a second resin part 32.
  • the second electrode plate 343 is provided on the first resin surface 31S of the first resin part 31.
  • the second electrode plate 343 and the first resin surface 31S of the first resin part 31 are covered by the second resin part 32.
  • the first electrode plate 326 and the second electrode plate 343 are arranged so as to overlap each other when viewed from the z direction.
  • the first electrode plate 326 and the second electrode plate 343 are arranged so as to face each other in the z direction.
  • the first electrode plate 326 and the second electrode plate 343 form a capacitor.
  • the semiconductor device 310 is a capacitor chip including a capacitor. With this modified semiconductor device 310, the same effects as those of the semiconductor device 10 described above can be obtained.
  • each semiconductor device can be used for other purposes.
  • it may be used in a direct current voltage conversion circuit (DC-DC converter), a digital isolator, an isolated AD conversion circuit, etc.
  • DC-DC converter direct current voltage conversion circuit
  • AD conversion circuit an isolated AD conversion circuit
  • a first layer is formed on a second layer is intended to mean that in some embodiments, the first layer may be in contact with the second layer and disposed directly on the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer.
  • the term “on” does not exclude a structure in which another layer is formed between the first and second layers.
  • the Z-axis direction used in this disclosure does not necessarily have to be vertical, nor does it have to be perfectly aligned with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1) are not limited to the "up” and “down” in the Z-axis direction described in this specification being "up” and “down” in the vertical direction.
  • the X-axis direction may be vertical, or the Y-axis direction may be vertical.
  • (Appendix 1) a semiconductor element including a first element surface (20S) and a second element surface (20R) facing in opposite directions in a thickness direction, a plurality of element side surfaces (201-204) intersecting the first element surface (20S) and the second element surface (20R), an element insulating layer (22) including an insulating surface (22S) constituting the first element surface (20S), and a first conductor (26, 326) provided in the element insulating layer (22); a first resin portion (31, 231) including a first resin surface (31S) facing the same direction as the first element surface (20S) and covering the first element surface (20S); A second conductor (43, 343) formed on the first resin surface (31S); a second resin portion (32) including a second resin surface (32S) facing in the same direction as the first resin surface (31S) and covering the first resin surface (31S) and the second conductor (43); Including, the first conductor (26, 326) and the second conductor (43, 343) face each other in the thickness direction with
  • the first conductor is a first coil (26) formed in a spiral shape when viewed from the thickness direction
  • the second conductor is a second coil (43) formed in a spiral shape when viewed from the thickness direction.
  • the first conductor is a first electrode plate (326) extending in a direction parallel to the first element surface (20S),
  • the second conductor is a second electrode plate (343) extending in a direction parallel to the first element surface (20S),
  • the first electrode plate (326) and the second electrode plate (343) form a capacitor.
  • the thickness of the first resin portion (31) is greater than the thickness of the second resin portion (32). 5.
  • the semiconductor device according to claim 1
  • the thickness of the first resin portion (31) is thinner than the thickness of the second resin portion (32). 5.
  • the semiconductor device according to claim 1
  • the first resin portion (31) is made of a material having a higher pressure resistance than the second resin portion (32). 7.
  • the semiconductor device according to claim 1
  • the first resin portion (31) is made of a material having higher adhesion than the second resin portion (32). 8. The semiconductor device according to claim 1 ,
  • the first resin portion (231) is composed of a plurality of resin layers (231A, 231B).
  • the semiconductor device is The semiconductor substrate (21) has a first substrate surface (21S) facing in the same direction as the first element surface (20S) and a second substrate surface (21R) constituting the second element surface (20R), and the element insulating layer (22) is formed on the first substrate surface (21S),
  • the element insulating layer (22) is a first insulating film (23, 24) formed on the first substrate surface (21S); a second insulating film (25) formed on the first insulating film (23, 24); Including,
  • the first conductor (26, 326) is formed on the first insulating film (23, 24) and is covered with the second insulating film (25).
  • the semiconductor element includes a first wiring layer (28) provided in the first insulating film (23, 24) and electrically connected to the first conductor (26), and an element pad (27A, 27B) electrically connected to the first wiring layer (28) and exposed from an opening formed in the second insulating film (25). 11.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
PCT/JP2024/005655 2023-02-21 2024-02-19 半導体装置 Ceased WO2024176988A1 (ja)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006319094A (ja) * 2005-05-12 2006-11-24 Fujikura Ltd 半導体装置およびその製造方法
JP2010109269A (ja) * 2008-10-31 2010-05-13 Panasonic Corp 半導体装置
JP2011253944A (ja) * 2010-06-02 2011-12-15 Toshiba Corp 半導体装置及びその製造方法
WO2014132937A1 (ja) * 2013-02-28 2014-09-04 株式会社村田製作所 Ｅｓｄ保護デバイス
WO2014155478A1 (ja) * 2013-03-25 2014-10-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20160260796A1 (en) * 2015-03-04 2016-09-08 Tower Semiconductor Ltd. Die including a high voltage capacitor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006319094A (ja) * 2005-05-12 2006-11-24 Fujikura Ltd 半導体装置およびその製造方法
JP2010109269A (ja) * 2008-10-31 2010-05-13 Panasonic Corp 半導体装置
JP2011253944A (ja) * 2010-06-02 2011-12-15 Toshiba Corp 半導体装置及びその製造方法
WO2014132937A1 (ja) * 2013-02-28 2014-09-04 株式会社村田製作所 Ｅｓｄ保護デバイス
WO2014155478A1 (ja) * 2013-03-25 2014-10-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20160260796A1 (en) * 2015-03-04 2016-09-08 Tower Semiconductor Ltd. Die including a high voltage capacitor

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