WO2024142673A1 - 積層セラミックコンデンサ - Google Patents

積層セラミックコンデンサ Download PDF

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Publication number
WO2024142673A1
WO2024142673A1 PCT/JP2023/041748 JP2023041748W WO2024142673A1 WO 2024142673 A1 WO2024142673 A1 WO 2024142673A1 JP 2023041748 W JP2023041748 W JP 2023041748W WO 2024142673 A1 WO2024142673 A1 WO 2024142673A1
Authority
WO
WIPO (PCT)
Prior art keywords
internal electrode
electrode layer
laminate
multilayer ceramic
ceramic capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/041748
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
明 石塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to CN202380089401.6A priority Critical patent/CN120457506A/zh
Priority to KR1020257012301A priority patent/KR20250073184A/ko
Priority to JP2024567291A priority patent/JP7852745B2/ja
Publication of WO2024142673A1 publication Critical patent/WO2024142673A1/ja
Priority to US19/251,871 priority patent/US20250329496A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/24—Distinguishing marks, e.g. colour coding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor

Definitions

  • the objective of the present invention is to provide a multilayer ceramic capacitor with high mounting reliability that can more reliably suppress and prevent the occurrence of tombstone phenomenon than conventional multilayer ceramic capacitors.
  • the present invention provides a laminate including an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately laminated, the laminate forming a first main surface and a second main surface opposed to each other in a lamination direction, a first end surface and a second end surface opposed to each other in a length direction intersecting with the lamination direction, and a first side surface and a second side surface opposed to each other in a width direction intersecting with the lamination direction and the width direction; a plurality of external electrodes disposed on either one of the two end faces or the two side faces of the laminate and connected to the internal electrode layers;
  • a multilayer ceramic capacitor comprising: When a cross section of the laminate is cut along a plane perpendicular to the longitudinal direction at a position where the external electrodes are not disposed, This is a multilayer ceramic capacitor, in which a distance T1 between an end portion on the first side surface side of an internal electrode layer located closest to the first main surface side and an end portion on the first side surface side of an internal electrode layer located
  • the present invention makes it possible to suppress or prevent the occurrence of tombstone phenomenon during mounting, and to provide a multilayer ceramic capacitor with high mounting reliability.
  • FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor 1 (first embodiment).
  • 2 is a cross-sectional view of the multilayer ceramic capacitor 1 (first embodiment) taken along line II-II shown in FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 (first embodiment) taken along line III-III shown in FIG. 1 is an exploded perspective view illustrating a laminated state of an inner layer portion 11 of a multilayer ceramic capacitor 1 (first embodiment).
  • FIG. 2 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 (first embodiment).
  • 1 is a perspective view of a material sheet 203 having an internal electrode layer pattern 103 that will become the internal electrode layer 15 of the multilayer ceramic capacitor 1 (first embodiment) printed on the surface of a ceramic green sheet 101.
  • FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor 1 (first embodiment).
  • 2 is a cross-sectional view of the multilayer ceramic capacitor 1 (first embodiment) taken along line II-II shown in FIG.
  • FIG. 2 is a perspective view showing a state in which ceramic paste 102 is placed on a material sheet 203.
  • FIG. 8 is a partial cross-sectional view of FIG. 7 .
  • 10 is a diagram illustrating a stacked state of material sheets 203.
  • FIG. 1 is a diagram showing a mounted state of a multilayer ceramic capacitor 1 (first embodiment).
  • FIG. 2 is a schematic perspective view of a multilayer ceramic capacitor 300 (second embodiment).
  • 1 is an exploded perspective view illustrating a state of an internal electrode layer 15 in an internal layer portion 11 of a multilayer ceramic capacitor 300 (second embodiment).
  • FIG. 1 is an exploded perspective view illustrating the arrangement of ceramic pastes 102A, 102B in an inner layer portion 11 of a multilayer ceramic capacitor 300 (second embodiment).
  • FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor 1 of the first embodiment.
  • FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of the first embodiment taken along line II-II shown in FIG. 1.
  • FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of the first embodiment taken along line III-III shown in FIG. 1.
  • first main surface Aa and the second main surface Ab when there is no need to distinguish between the first main surface Aa and the second main surface Ab, they will be collectively referred to as the main surface A, when there is no need to distinguish between the first side surface Ba and the second side surface Bb, they will be collectively referred to as the side surface B, and when there is no need to distinguish between the first end surface Ca and the second end surface Cb, they will be collectively referred to as the end surface C.
  • the laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the stacking direction T.
  • the dimensions of the laminate 2 are not particularly limited, but it is preferable that the length direction L dimension is 0.6 mm or more and 3.2 mm or less, the width direction W dimension is 0.3 mm or more and 2.5 mm or less, and the stacking direction T dimension is 0.3 mm or more and 2.5 mm or less.
  • the end of the internal electrode layer 15 on the first side face Ba side is spaced apart from the other end in the stacking direction T as shown in Fig. 3.
  • the distance T1 between the end of the first side face Ba side of the top internal electrode layer 15 as the internal electrode layer 15 located closest to the first main face Aa and the end of the first side face Ba of the bottom internal electrode layer 15 as the internal electrode layer 15 located closest to the second main face Ab is longer than the distance T2 between the end of the second side face Bb of the top internal electrode layer 15 as the internal electrode layer 15 located closest to the first main face Aa and the end of the second side face Bb of the bottom internal electrode layer 15 as the internal electrode layer 15 located closest to the second main face Ab.
  • the distance T1 between the end of the first side surface Ba of the uppermost internal electrode layer 15 as the internal electrode layer 15 located closest to the first main surface Aa and the end of the first side surface Ba of the lowermost internal electrode layer 15 as the internal electrode layer 15 located closest to the second main surface Ab, and the distance T2 between the end of the second side surface Bb of the uppermost internal electrode layer 15 as the internal electrode layer 15 located closest to the first main surface Aa and the end of the second side surface Bb of the lowermost internal electrode layer 15 as the internal electrode layer 15 located closest to the second main surface Ab can be measured using a scanning electron microscope (SEM) or a metallurgical microscope on a cross section of the multilayer ceramic capacitor 1 polished perpendicular to the longitudinal direction to a position that is 1/2 of the longitudinal dimension of the multilayer ceramic capacitor 1.
  • SEM scanning electron microscope
  • a metallurgical microscope on a cross section of the multilayer ceramic capacitor 1 polished perpendicular to the longitudinal direction to a position that is 1/2 of the longitudinal dimension of the multilayer ceramic capacitor 1.
  • the internal electrode layer 15 is divided into a central region including a central portion, a first side surface side region located on the first side surface Ba side of the central region, and a second side surface side region located on the second side surface Bb side of the central region, it is preferable that the distance t1 in the stacking direction at any position in the first side surface side region between two adjacent internal electrode layers 15 is longer than the distance t2 in the stacking direction at any position in the second side surface side region.
  • the distance t1 in the stacking direction at any position in the first side region and the distance t2 in the stacking direction at any position in the second side region can be measured using a scanning electron microscope (SEM) or a metallurgical microscope on a cross section of the multilayer ceramic capacitor 1 polished to a position that is 1/2 the longitudinal dimension of the laminate, perpendicular to the longitudinal length.
  • SEM scanning electron microscope
  • a metallurgical microscope on a cross section of the multilayer ceramic capacitor 1 polished to a position that is 1/2 the longitudinal dimension of the laminate, perpendicular to the longitudinal length.
  • the first side face Ba is arranged facing the substrate, it is preferable to provide an identification means for identifying the direction in which the end face external electrode 3 is arranged.
  • the identification means is not particularly limited, but examples include means for making the shape and length of the surface on the second side face Bb side of the end face external electrode 3 different from the shape of the first side face Ba.
  • the baked layer is formed by applying a conductive paste containing glass and metal to the laminate and baking it, and may be baked simultaneously with the internal electrodes or after the internal electrodes are baked.
  • the baking temperature is preferably 700 to 900° C.
  • the glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc.
  • the metal includes at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.
  • the conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto a baking layer or a laminate, and then performing a heat treatment at a temperature of 250 to 550°C or higher to thermally cure the resin and form a conductive resin layer.
  • the atmosphere during the heat treatment is preferably a N2 atmosphere.
  • the reason for using Ag conductive metal powder as the conductive metal is that Ag has a relatively low resistivity among metals, making it suitable as an electrode material, and because Ag is a precious metal, it does not oxidize and is highly stable.
  • the reason for using Ag-coated metal is that it is possible to make the base metal cheaper while maintaining the above-mentioned properties of Ag.
  • the metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the conductive fillers come into contact with each other, an electrical path is formed inside the conductive resin layer.
  • the plating layer preferably contains at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing the metal.
  • the direct plating layer is preferably formed using Cu, which has good bonding properties with Ni.
  • the internal electrode layer pattern 103 which becomes the internal electrode layer 15 is formed by using a conductive paste on the ceramic green sheet 101 which becomes the dielectric layer 14.
  • Fig. 6 is a perspective view of a material sheet 203 in which the internal electrode layer pattern 103 which becomes the internal electrode layer 15 is printed on the surface of the ceramic green sheet 101.
  • the internal electrode layer pattern 103 is formed by printing such as screen printing, gravure printing, letterpress printing or the like.
  • the internal electrode layer pattern 103 forms a step 104 on the ceramic green sheet 101 due to its thickness.
  • the step 104 is an inclined surface.
  • the ceramic paste 102 forming the dielectric layer is placed on the material sheet 203 so as to fill the step 104 due to the thickness of the internal electrode layer pattern 103 and to overlap at a certain width with one side on the first side face Ba side of the internal electrode layer pattern 103.
  • the ceramic paste 102 forming the dielectric layer on the outer periphery where the internal electrode layer pattern 103 is to be formed may be placed on the material sheet 203 first, and the internal electrode may be placed later so as to overlap at a certain width with one side on the first side face Ba side of the internal electrode layer pattern 103.
  • Fig. 7 is a perspective view showing a state in which the ceramic paste 102 is placed on the material sheet 203.
  • the ceramic paste 102 is applied by printing, such as screen printing, gravure printing, letterpress printing, etc.
  • the ceramic paste 102 may have a different component ratio from the dielectric material serving as the material of the ceramic green sheet 101, may have the same component ratio, or may contain different components.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
PCT/JP2023/041748 2022-12-28 2023-11-21 積層セラミックコンデンサ Ceased WO2024142673A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202380089401.6A CN120457506A (zh) 2022-12-28 2023-11-21 层叠陶瓷电容器
KR1020257012301A KR20250073184A (ko) 2022-12-28 2023-11-21 적층 세라믹 콘덴서
JP2024567291A JP7852745B2 (ja) 2022-12-28 2023-11-21 積層セラミックコンデンサ
US19/251,871 US20250329496A1 (en) 2022-12-28 2025-06-27 Multilayer ceramic capacitor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-212597 2022-12-28
JP2022212597 2022-12-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US19/251,871 Continuation US20250329496A1 (en) 2022-12-28 2025-06-27 Multilayer ceramic capacitor

Publications (1)

Publication Number Publication Date
WO2024142673A1 true WO2024142673A1 (ja) 2024-07-04

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PCT/JP2023/041748 Ceased WO2024142673A1 (ja) 2022-12-28 2023-11-21 積層セラミックコンデンサ

Country Status (5)

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US (1) US20250329496A1 (https=)
JP (1) JP7852745B2 (https=)
KR (1) KR20250073184A (https=)
CN (1) CN120457506A (https=)
WO (1) WO2024142673A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014160693A (ja) * 2012-12-11 2014-09-04 Samsung Electro-Mechanics Co Ltd 積層セラミックキャパシタ及びその製造方法
JP2014222749A (ja) * 2013-05-13 2014-11-27 サムソン エレクトロ−メカニックス カンパニーリミテッド． 積層セラミック電子部品及びその実装基板
JP2015170849A (ja) * 2014-03-07 2015-09-28 サムソン エレクトロ−メカニックス カンパニーリミテッド． 積層セラミック電子部品及び積層セラミック電子部品の実装基板
JP2022053271A (ja) * 2020-09-24 2022-04-05 株式会社村田製作所 積層セラミックコンデンサ
JP2022075191A (ja) * 2020-11-06 2022-05-18 株式会社村田製作所 積層セラミックコンデンサ及び積層セラミックコンデンサの製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5047699B2 (ja) 2007-06-08 2012-10-10 ルネサスエレクトロニクス株式会社 増幅回路、デジタルアナログ変換回路及び表示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014160693A (ja) * 2012-12-11 2014-09-04 Samsung Electro-Mechanics Co Ltd 積層セラミックキャパシタ及びその製造方法
JP2014222749A (ja) * 2013-05-13 2014-11-27 サムソン エレクトロ−メカニックス カンパニーリミテッド． 積層セラミック電子部品及びその実装基板
JP2015170849A (ja) * 2014-03-07 2015-09-28 サムソン エレクトロ−メカニックス カンパニーリミテッド． 積層セラミック電子部品及び積層セラミック電子部品の実装基板
JP2022053271A (ja) * 2020-09-24 2022-04-05 株式会社村田製作所 積層セラミックコンデンサ
JP2022075191A (ja) * 2020-11-06 2022-05-18 株式会社村田製作所 積層セラミックコンデンサ及び積層セラミックコンデンサの製造方法

Also Published As

Publication number Publication date
KR20250073184A (ko) 2025-05-27
CN120457506A (zh) 2025-08-08
JP7852745B2 (ja) 2026-04-28
JPWO2024142673A1 (https=) 2024-07-04
US20250329496A1 (en) 2025-10-23

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